A fast dynamic DC-link power-balancing scheme for a PWMconverter-inverter system

The authors propose a new power converter control scheme for a converter-inverter system. The strategy is to fully utilize the inverter dynamics in controlling the converter dynamics. The authors obtain the power dynamics for both converter and inverter systems, and control the converter power so that it matches the required inverter power exactly. Then, in the ideal case, no power flows through the DC-link capacitors and, thus, the DC-link voltage does not fluctuate even though a very small amount of the DC-link capacitance is used. In forcing the converter power to match the inverter power, the authors utilize the master-slave control concept. They control the DC-link voltage level indirectly through the stored capacitor energy in order to exploit the advantage of the linear dynamic behavior of the capacitor energy. This helps them to circumvent a complex control method in regulating the DC-link voltage. Through simulation and experimental results, the superiority of the proposed converter control scheme is demonstrated     

A new control scheme for single-phase PWM multilevel rectifier withpower-factor correction

A new control scheme for a single-phase bridge rectifier with three-level pulsewidth modulation is proposed to achieve high power factor and low current distortion. The main circuit consists of a diode-bridge rectifier, a boost inductor, two AC power switches, and two capacitors. According to the proposed control scheme based on a voltage comparator and hysteresis current control technique, the output capacitor voltages are balanced and the line current will follow the supply current command. The supply current command is derived from a DC-link voltage regulator and an output power estimator. The major advantage of using a three-level rectifier is that the blocking voltage of each AC power device is clamping to half of the DC-link voltage and the generated harmonics of the three-level rectifier are less than those of the conventional two-level rectifier. There are five voltage levels (0, ±V_DC/2, ±V_DC) on the AC side of the diode rectifier. The high power factor and low harmonic currents at the input of the rectifier are verified by software simulations and experimental tests     

A novel PWM scheme for single-phase three-levelpower-factor-correction circuit

This paper presents a control scheme for a single-phase AC-to-DC power converter with three-level pulsewidth modulation. A single-phase power-factor-correction circuit is proposed to improve the power quality. The hysteresis current control technique for a diode bridge, with two power switches is adopted to achieve a high power factor and low harmonic distortion. A control scheme is presented where the line current is driven to follow the reference sinusoidal current which is derived from the DC-link voltage regulator, the capacitor voltage balance compensator and the output power estimator. The blocking voltage of each power device is clamped to half of the DC-link voltage. The high power factor and low current total harmonic distortion are verified by computer simulations and hardware tests     

Loss-Free Balancing Circuit for Series Connection of Electrolytic Capacitors Using an Auxiliary Switch-Mode Power Supply

Most of today's power converters such as three-phase variable-speed drives, uninterruptible power systems, welding converters, and telecom and server power supplies are based on voltage-source converters equipped with bulky dc-link electrolytic capacitors. To be able to handle full dc bus voltage, the dc bus capacitor is arranged as series-connected electrolytic capacitors rated at lower voltage. An electrolytic capacitor, however, is not an ideal capacitor. It has significant leakage current that strongly depends on the capacitor temperature, voltage, and ageing conditions. To compensate large dispersion of the leakage current and ensure acceptable sharing of the total dc bus voltage among the series-connected capacitors, a passive balancing circuit is often used. Drawbacks of the ordinary passive balancing circuit, such as size, significant losses, and standby consumption are discussed in this paper. An active loss-free balancing circuit, which utilizes an auxiliary switch-mode power supply (SMPS) to equalize the capacitor voltages, is proposed. The capacitors midpoint (MP) is connected to the SMPS via two devices; namely a current injection device and a compensation device. The current injection device injects current into the capacitors MP, while the compensation device sinks the difference between the capacitor leakage currents and the injected current. As a result, the capacitor voltages are controlled and maintained in the desired ratio. The proposed balancing technique is theoretically analyzed and experimentally verified on a laboratory setup. The results are presented and discussed.      

A multilevel inverter approach providing DC-link balancing, ride-through enhancement, and common-mode voltage elimination

This paper presents a simple control method for balancing the DC-link voltage of three-level neutral-point-clamped inverters, while providing enhanced ride-through and common-mode voltage (CMV) elimination. The method uses DC-DC power converter technology on the DC link for balancing and ride-through enhancement, and a modified pulsewidth-modulation switching algorithm for CMV elimination. Simulation and experimental results are supplied to confirm the validity of the proposed method, which includes full digital signal processor control.     

Single-phase high power factor pre-regulator with three-level modulation scheme

A control scheme for the single-phase three-level pulse-width modulation active rectifier is proposed. A hysteresis current control scheme is used to draw the sinusoidal line current in phase with the mains voltage. The line current command is derived from a voltage controller and a phase-locked loop circuit. The blocking voltage of each power device is clamped to half of the DC-link voltage in the proposed active rectifier. In order to generate the three-level voltage pattern on the DC side of the active rectifier, the region detector of the line voltage, capacitor voltage compensator and hysteresis current comparator are employed in the adopted control algorithm to achieve high input power factor and low current distortion. To investigate the proposed control algorithm, the adopted rectifier is simulated and experimental tests from a laboratory prototype undertaken.     

A novel control scheme for the multilevel rectifier/inverter

A novel three-level pulsewidth modulation (PWM) rectifier/inverter is proposed: this single-phase three-level rectifier with power factor correction and current harmonic reduction is proposed to improve power quality. A three-phase three-level neutral point clamped (NPC) inverter is adopted to reduce the harmonic content of the inverter output voltages and currents. In the adopted rectifier, a switching mode rectifier with two AC power switches is adopted to draw a sinusoidal line current in phase with mains voltage. The switching functions of the power switches are based on a look-up table. To achieve a balanced DC-link capacitor voltage, a capacitor voltage compensator is employed. In the NPC inverter, the three-level PWM techniques based on the sine-triangle PWM and space vector modulation are used to reduce the voltage harmonics and to drive an induction motor. The advantages of the adopted th-ree-level rectifier/inverter are (1) the blocking voltage of power devices (T1, T2, S_a1-S_c4) is clamped to half of the DC-link voltage, (2) low conduction loss with low conduction resistance due to low voltage stress, (3) low electromagnetic interference, and (4) low voltage harmonics in the inverter output. Based on the proposed control strategy, the rectifier can draw a high power factor line current and achieve two balance capacitor voltages. The current harmonics generated from the adopted rectifier can meet the international requirements. Finally, the proposed control algorithm is illustrated through experimental results based on the laboratory prototype.     

箝位二极管承受低电压的有源箝位谐振直流环节逆变器

为解决无源箝位谐振直流环节逆变器辅助电路中采用耦合电感辅助换流（即抽头电感法）所引起的箝位二极管两端承受的电压应力过大问题,提出一种箝位二极管承受低电压的有源箝位谐振直流环节逆变器,该逆变器采用有源箝位的方法可使箝位二极管两端承受的最大反向电压不超过直流母线电压的最大值.且该逆变器的辅助谐振电路中只有一个辅助开关器件,箝位电路中无需设置箝位开关,控制简单且硬件成本较低.此外,在箝位电路的作用下可将逆变器的直流母线电压箝位在输入直流电压的1.1~1.3倍,有效地降低了电压应力.以各个阶段下的等效电路为基础,对电路的工作过程进行了分析,并进行了实验验证,实验结果表明开关器件实现了软开关,且在额定功率3kW条件下,逆变器的效率达到96.5%.因此,该拓扑结构能够有效地提高工作效率.     

Optimal-regulator-based control of NPC boost rectifiers for unitypower factor and reduced neutral-point-potential variations

Neutral-point-clamped pulsewidth modulation rectifiers (NPCRs) are suitable for high-voltage systems because of their circuit structure. The NPCRs, however, have a problem, in that the neutral point potential (NPP) varies when the current flows into or out of the neutral point. The variations cause voltage deviations in the input waveforms, as well as unbalanced voltage stress on the devices. This paper describes a controlling method for NPCRs based on a state-space model. There are three control objectives: (1) to keep the power factor at unity; (2) to keep the DC-link voltage at a reference value; and (3) to keep the neutral point potential at 0 V. The neutral point current is treated as one of the inputs. The controller is designed based on the optimal regulator theory in order to achieve the three control objectives simultaneously. The validity of the proposed method is demonstrated by experimental results     

A Current Distortion Compensation Scheme for Four-Switch Inverters

The four-switch inverter, having a lower number of insulated gate bipolar transistors(IGBTs), has been studied for the possibility of reducing the inverter cost. But it has a limited performance in the low-frequency region, because the balance among the phase currents collapses due to the fluctuation of the center tap voltage of the DC-link capacitors. This problem could be solved if the DC-link capacitance is infinitely large, but it is a costly solution. In this paper, this problem is looked at from the perspective of source impedance and the voltage variation caused by the current flow through the capacitors. The source impedance of the center tap is large compared with other normal IGBT arms. This causes an asymmetry among the three voltage sources, resulting in phase current distortion and unbalance. Second, the capacitor voltage change caused by current flow is another source of current distortion and unbalance. The voltage errors are derived, and based on them, a compensation method is proposed. Effectiveness of the proposed method is demonstrated by the simulation and experimental results.     

A CMOS SLIC with an automatic balancing hybrid

A CMOS subscriber line interface circuit (SLIC) that has an automatic balancing hybrid facility is presented. Some of the key system aspects of line interface circuits, such as the relation between zero-loss switching and an automatic balancing hybrid circuit, power dissipation in the line circuit, and foreign voltage protection are described first. Next, details of the SLIC LSI, which comprises a dial pulse detecting circuit and and automatic balancing hybrid circuit, are described. The LSI is implemented with CMOS switched capacitor technology and is mounted on a 20-in DIL.     

High-power-factor electronic ballast with constant DC-link voltage

This paper presents a high-power-factor (HPF) electronic ballast based on a single power processing stage with constant DC-link voltage. The switching frequency is controlled to maintain the DC-link voltage and the voltage across the switches constant, independently of changes in the AC-input voltage. This control method assures zero-voltage switching (ZVS) for the specified AC-input-voltage range. Besides, with an appropriate design of the fluorescent lamps' drive circuit, the lamps' power can be kept close to the rated value. The power-factor-correction (PFC) stage is formed by a boost power converter operating in the discontinuous conduction mode, which naturally provides HPF to the utility line. The fluorescent lamps are driven by an unmodulated sine-wave current generated from an LC parallel resonant power converter which operates above the resonant frequency to perform ZVS. Theoretical analysis and experimental results are presented for two series-connected 40 W fluorescent lamps operating from 127 V -15% to +10% 60 Hz utility line. The switching frequency is changed from 25 to 45 kHz to maintain the DC-link voltage regulated at 410 V, which leads to a constant output power. The experimental results confirm the high efficiency and HPF of this electronic ballast     

Optimized Control Strategy for a Medium-Voltage DVR—Theoretical Investigations and Experimental Results

Most power quality problems in distribution systems are related to voltage sags. Therefore, different solutions have been examined to compensate these sags to avoid production losses at sensitive loads. Dynamic Voltage Restorers (DVRs) have been proposed to provide higher power quality. Currently, a system wide integration of DVRs is hampered because of their high cost, in particular, due to the expensive DC-link energy storage devices. The cost of these DC-link capacitors remains high because the DVR requires a minimum DC-link voltage to be able to operate and to compensate a sag. As a result, only a small fraction of the energy stored in the DC-link capacitor is used, which makes it impractical for DVRs to compensate relatively long voltage sags. Present control strategies are only able to minimize the distortions at the load or to allow a better utilization of the storage system by minimizing the needed voltage amplitude. To avoid this drawback, an optimized control strategy is presented in this paper, which is able to reduce the needed injection voltage of the DVR and concurrently to mitigate the transient distortions at the load side. In the following paper, a brief introduction of the basic DVR principle will be given. Next, three standard control strategies will be compared and an optimized control strategy is developed in this paper. Finally, experimental results using a medium-voltage 10-kV DVR setup will be shown to verify and prove the functionality of the presented control strategy in both symmetrical and asymmetrical voltage sag conditions.      

A comparison of high-power converter topologies for the implementation of FACTS controllers

This paper compares four power converter topologies for the implementation of flexible AC transmission system (FACTS) controllers: three multilevel topologies (multipoint clamped (MPC), chain, and nested cell) and the well-established multipulse topology. In keeping with the need to implement very-high-power inverters, switching frequency is restricted to line frequency. The study addresses device count, DC filter ratings, restrictions on voltage control, active power transfer through the DC link, and balancing of DC-link voltages. Emphasis is placed on capacitor sizing because of its impact on the cost and size of the FACTS controller. A method for the dimensioning the DC capacitor filter is presented. It is found that the chain converter is attractive for the implementation of a static compensator or a static synchronous series compensator. The MPC converter is attractive for the implementation of a unified power flow controller or an interline power flow controller, but a special arrangement is required to overcome the limitations on voltage control.     

MOPA结构准分子激光电源的高精度电压控制研究

为了减小激光器双腔放电时间的相对抖动、稳定激光器输出能量,采用闭环控制回路电压泄放方法,设计了一套主振荡功率放大结构准分子激光谐振充电高精度电压控制方案。通过对电容电压取样处理,动态监测储能电容电压,当电容电压大于目标电压时,由泄放电路泄放电压至目标值,得到高精度的充电电压,使用此电压控制方案后,充电电压的波动由1.67减小到0.83。结果表明,该方案很好地提高了谐振电源储能电容上的电压精度,减小了激光器双腔放电时间的相对抖动,并为后期的激光器能量输出稳定控制打下良好基础。     

Capacitor voltage balancing in full binary combination schema flying capacitor multilevel inverters

Recently, the full binary combination schema (FBCS) method has been introduced to control the flying capacitor multilevel inverter. This method has the primary advantage that the number of voltage levels can be increased for a given number of semiconductor devices when compared to the conventional control methods. However, due to the difficulty of balancing the capacitors, the new schema requires fixed floating sources to provide the DC voltages. This paper reveals an approach of balancing the capacitors, thus expanding the application fields of FBCS inverters to the family of the flying capacitor multilevel inverters under the condition of choosing a suitable modulation index. Simulation results demonstrate the proposed voltage balancing control.     

A new quasi-parallel resonant DC link for soft-switching PWMinverters

A new quasi-parallel resonant DC-link inverter with the more flexible pulse-width-modulation (PWM) capability and easier control is proposed in this paper. With the addition of one coupling core and one diode, the circuit can be directly applied to the single/three-phase inverter to achieve the soft-switching action. For the proposed topology, it needs neither the help of the inverter switch devices nor the requirement of voltage/current sensors. Random duration of the zero DC-link voltage can be obtained, and the voltage stresses of the inverter switches can be maintained to the minimum. The relative analysis of the presented circuit has been performed and verified by the experiment     

低压无功补偿电容投切装置的设计

在电力系统中装设静止无功补偿装置(SVC)是控制无功功率、保证电压质量的有效手段,他根据无功功率的需求,对无功器件(电容器和电抗器)进行投切或调节。晶闸管投切电容器(TSC)是静止无功补偿技术的发展方向,这种装置的关键问题是如何对作为电容器投切开关的晶闸管进行控制。针对TSC低压无功补偿装置的结构,对晶闸管的触发电路进行详细的设计和分析,仿真结果证明了设计的正确性。     

Extended operation of flying capacitor multilevel inverters

Recent research in flying capacitor multilevel inverters (FCMIs) has shown that the number of voltage levels can be extended by changing the ratio of the capacitor voltages. For the three-cell FCMI, four levels of operation are expected if the traditional ratio of the capacitor voltages is 1:2:3. However, by altering the ratio, the inverter can operate as a five-, six-, seven-, or eight-level inverter. According to previous research, the eight-level case is referred to as maximally distended (or full binary combination schema) since it utilizes all possible transistor switching states. However, this case does not have enough per-phase redundancy to ensure capacitor voltage balancing under all modes of operation. In this paper, redundancy involving all phases is used along with per-phase redundancy to improve capacitor voltage balancing. It is shown that the four- and five-level cases are suitable for motor drive operation and can maintain capacitor voltage balance under a wide range of power factors and modulation indices. The six-, seven-, and eight-level cases are suitable for reactive power transfer in applications such as static var compensation. Simulation and laboratory measurements verify the proposed joint-phase redundancy control.     

A Novel Voltage-Feedback Pixel Circuit for AMOLED Displays

This study presents a novel voltage-modulated pixel circuit for active-matrix organic light-emitting diode (AMOLED) consisting of five n-type thin-film transistors (TFTs), one additional control signal, and one storage capacitor. The proposed circuit, which can be implemented in all-n-type and all-p-type low temperature poly-silicon (LTPS) TFT technologies, successfully compensates for threshold voltage deviation of TFTs and facilitates correction of OLED degradation using a voltage feedback method. Simulation and experimental results for all-n-type TFTs indicate that the proposed pixel circuit reduced the nonuniformity brightness problem effectively by compensating for threshold voltage variation in TFTs and reduced the degradation of emission efficiency in OLEDs.