1 V All-MOS ΣΔ A/D Converters in the Log-domain

This paper presents novel low-voltage all-MOS analog circuit techniques for the synthesis of oversampling A/D converters. The new approach exploits the possibilities of Log-domain processing by using the MOSFET in subthreshold operation. Based on this strategy, a complete set of very low-voltage (down to 1 V) low-power (below 100 W) all-MOS basic building blocks is proposed. The resulting analog circuit techniques allow the integration of A/D converters for low-frequency (below 100 KHz) applications in digital CMOS technologies. Examples are given for a standard 0.35 m VLSI process.     

A 640 by 480 Pixels Readout Circuit for IR Imaging

A readout circuit for a 640 × 480 pixels FPA (focal plane array) has been successfully designed, fabricated and tested. The circuit solution is based on a per pixel source-follower direct injection (SFDI) pre-amplifier. Signal multiplexing is performed in both X and Y direction. The pixel size is 25 m × 25m. The chip is optimized for a QWIP (quantum well infrared photodetector) operating at a temperature of 70 K. The circuit has been realized in a standard 0.8 m CMOS process.     

High-Speed High-Precision CMOS Current Conveyor

In this paper a new class-AB CMOS second generation current conveyor (CCII) based on a novel high-performance voltage follower topology is proposed. Post-layout simulation results from a 0.8 m design supplied at 3.3 V show very low resistance at node X (<50 ), high frequency operation (100 MHz), high precision in the voltage and current transference and reduced offset. As application examples, a V-I converter and a current feedback operational amplifier (CFOA) have been implemented. The latter presents slew-rate levels higher than ±100 V/s.     

A New Approach to Realize Variable Gain Amplifiers

A new methodology to develop variable gain amplifiers is developed. The methodology is based on a feedback loop to generate the exponential characteristic, which is required for VGA circuits. The proposed idea is very suitable for applications that require very low power consumption, and as an application, a new current mode variable gain amplifier will be shown. The gain is adapted via a current signal ranges from –7.5 A to +6.5 A. Pspice simulations based on Mietec 0.5 m CMOS technology show that the gain can be varied over a range of 29.5 dB, with bandwidth of 3 MHz at maximum gain value. The circuit operates between ±1.5 V and consumes an average amount of power less than 495 W.     

Multi-Value Voltage-to-Voltage Converter Using a Multi-Stage Symmetrical Charge Pump for On-Chip EEPROM Programming

A fully integrated multi-stage symmetrical structure chargepump and its application to a multi-value voltage-to-voltage converterfor on-chip EEPROM programming are presented. The multi-valuevoltage-to-voltage converter is designed to offer two output voltages,power supply and triple power supply alternatively, which is neededfor a memory array. A dynamic analysis of the multi-stage symmetricalstructure charge pump and an optimization design in terms of circuitarea are also given. The circuit is implemented in a 1.2 CMOSprocess and the measurement results show that a voltage pulse as shortas 5 s with a rise time of 3 s is obtained. For a 5 V powersupply and with a resistive charge of 100 k, the programmingoutput voltage can reach as high as 11 V and output current forprogramming is over 110 A, which are high enough to program thememory cell.     

A 70-MHz Continuous-Time CMOS Band-Pass ΣΔ Modulator for GSM Receivers

A 70-MHz continuous-time CMOS band-pass modulator for GSM receivers is presented. Impulse-invariant-transformation is used to transform a discrete-time loop-filter transfer function into continuous-time. The continuous-time loop-filter is implemented using a transconductor-capacitor (G _m -C) filter. A latched-type comparator and a true-single-phase-clock (TSPC) D flip-flop are used as the quantizer of the modulator. Implemented in a MOSIS HP 0.5-m CMOS technology, the chip area is 857 m × 420 m, and the total power consumption is 39 mW. At a supply voltage of 2.5 V, the maximum SNDR is measured to be 42 dB, which corresponds to a resolution of 7 bits.     

0.35 μm CMOS T/R Switch for 2.4 GHz Short Range Wireless Applications

This paper describes the design and implementation of a transmit/receive switch for 2.4 GHz ISM band applications. The T/R switch is implemented in a 0.35 m bulk CMOS process and it occupies 150 m · 170 m of die area. A parasitic MOSFET model including bulk resistance is used to optimize the physical dimensions of the transistors with regard to insertion loss and isolation. The measured insertion loss is 1.3 dB without port matching. Simulations using measured s-parameters indicate that an insertion loss of 0.8 dB can be obtained with a conjugate match. The measured isolation is 42 dB and the maximum transmit power is 16 dBm.     

β-bit serial/parallel multipliers

A generalized -bit least-significant-digit (LSD) first, serial/parallel multiplier architecture is presented with 1n wheren is the operand size. The multiplier processes both the serial input operand and the double precision product -bits per clock cycle in an LSD first, synchronous fashion. The complete two's complement double precision product requires 2n/ clock cycles. This generalized architecture creates a continuum of multipliers between traditional bit-serial/parallel multipliers (=1) and fully-parallel multipliers (=n). -bit serial/parallel multipliers allow anoptimized integrated circuit arithmetic to be designed based on a particular application's area, power, throughput, latency, and numerical precision constraints.This project was pratically funded by the UCSD-NSF I/UCR Center on Ultra-High Speed Intergrated Circuits and Systems.     

A 1.2 V Rail-to-Rail Analog CMOS Rank-Order Filter with k-WTA Capability

In this paper, we design a rank-order filter with k-WTA capability for 1.2 V supply voltage. The circuit can find a rank order among a set of input voltages by setting different binary signals. Moreover, without modifying the circuit, the k-WTA function can be easily configured. The circuit has been designed using a 0.5 m DPDM CMOS technology. Seven input voltages are used to verify the performance of the circuit. The results of HSPICE post-layout simulation show that the response time of the circuit is 10 s for each rank-order operation, the input dynamic range is rail-to-rail, and the resolution is 10 mV for 1.2 V supply voltage. An experimental chip has been fabricated, in which accuracy of the comparator is measured as 40 mV for low-voltage operation. The dynamic power dissipation of the chip is 550 W.     

RF CMOS Cells for Wireless Applications

There is increasing interest in the use of CMOS circuits for high frequency highly integrated wireless telecommunications systems. This paper presents the results of on-going work into the development of a cell library that includes many of the circuit elements required for the high frequency sub-systems of communications integrated circuits. The cell library studied included an RF control element, single ended Class A amplifier, RF isolator, and Gilbert cell mixer circuit topologies. Circuit design criteria and measurement results are presented. All cells were fabricated using standard 2.0, 1.2, and 0.8 m CMOS integrated circuit fabrication processes with no post-processing performed. The results indicate that 2.0 m CMOS can be used successfully up to approximately 250 MHz with 0.8 m cells useful up to approximately 1000 MHz.     

Low Voltage Rail to Rail CMOS Current Feedback Operational Amplifier and its Applications for Analog VLSI

This paper presents a new CMOS current feedback operational amplifier (CFOA) with rail to rail swing capability at all terminals. The circuit operates as a class AB for lower power consumption. Besides operating at low supply voltages of ±1.5 V, the proposed CFOA has a standby current of 200 A. The proposed CFOA circuit is thus a versatile building block for low voltage low power applications. The applications of the CFOA to realize a transconductor/multiplier cell, MOS-C differential integrator, MOS-C bandpass filter and MOS-C oscillator are given. PSpice simulations based on 1.2 m level three parameters obtained from MOSIS are given.     

A CMOS Offset Phase Locked Loop for a GSM Transmitter

This paper describes a CMOS offset phase locked loop (OPLL) for a global system for mobile communications (GSM) transmitter. The OPLL is a PLL with a down-conversion mixer in the feedback path and is used in the transmit (Tx) path as a frequency converter. It has a tracking bandpass filter characteristic in such a way that the OPLL can suppress the noise in the GSM receiving band (Tx noise) without a duplexer. When the loop bandwidth of the OPLL was 1.0 MHz, the Tx noise level of –163.5 dBc/Hz, the phase error of 0.66° rms, and the settling time of 40 s were achieved. The IC was implemented by using 0.35-m CMOS process. It takes 860 m×620 m of total chip area and consumes 17.6 mA with a 3.0 V power supply.     

CMOS Analog Implementation of a Discrete-Time 9-Tap FIR Filter with Circular Buffer Architecture

This paper presents the design and simulation of a 9-Tap CMOS Analog Discrete-Time Finite Impulse Response (FIR) Filter system. This unique design features a Circular Buffer Architecture which achieves high sampling rate that can be easily expanded to improve speed and extended to higher order filters. Novel area-efficient four quadrant CMOS analog adder and multiplier circuits are employed to respond for high frequency and wide linear range inputs. The layout for all circuits has been realized using the design tool MAGIC with a 1.2 m CMOS process. The performance for each circuit and the whole system are characterized using HSPICE simulation based on the extracted MAGIC netlist. The 9-tap filter was designed to achieve 5 MHz sampling rate. The implemented design requires a total chip area of 1690.9 m by 2134.2 m and ±5 volt power supply.     

An Analog Correlator for a WCDMA Receiver

A prototype analog correlator structure suitable for a WCDMA receiver was implemented. The advantages of this correlator are low power consumption compared to a digital correlator and small chip area. The target is to use such correlator as parallel correlators (fingers) of a RAKE receiver. The analog baseband correlator utilizes passive MOS-multipliers, a first-order low-pass continuous-time oversampling sigma–delta analog-to-digital converter and a second-order sinc type of decimation filter (for both I and Q input paths). The modulator sampling rate is twice the chip rate with oversampling ratios of 8–512 depending of the PN code length. The circuit was implemented in 0.8 m CMOS-technology with a supply voltage of 2.8 V. The layout size is 345 m×686 m and the current drain is approximately 370 A.     

Design Theory and Performance of 1-GHz CMOS Downconversion and Upconversion Mixers

A CMOS mixer topology capable of both downconversion and upconversion mixing for use in integrated wireless transceivers is presented. The mixing is based on two cross-coupled differential pairs as commutators with two source-followers as current modulators. Independence of the input and output bandwidths allows this topology to be optimized separately for either downconversion or upconversion mixer. The prototypes of both upconversion and downconversion mixers, optimized for linearity and realized in 0.8 m CMOS technology, have been demonstrated to fully operate at 1 GHz with good linearity and low power consumption. In addition, another mixer, optimized for noise figure and realized in 0.5 m CMOS technology, has been designed to achieve a NF of around 12 dB.     

A 10 bit Current-Mode CMOS A/D Converter with a Current Predictor and a Modular Current Reference

This paper describes a 10 bit CMOS current-mode A/D converter with a current predictor and a modular current reference circuit. A current predictor and a modular current reference circuit are employed to reduce the number of comparator and reference current mirrors and consequently to decrease a power dissipation. The 10 bit current-mode A/D converter is fabricated by the 0.6 m n-well double poly/triple metal CMOS technology. The measurement results show the input current range of 16–528 A, DNL and INL of ±0.5 LSB and ±1.0 LSB, conversion rate of 10 M samples, and power dissipation of 94.4 mW with a power supply of 5 V. The effective chip area excluding the pads is 1.8 mm×2.4 mm.     

Design and Analysis of On-Chip ESD Protection Circuit with Very Low Input Capacitance for High-Precision Analog Applications

An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (m/m) in a 0.35-m silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only 1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.     

Compact High Gain CMOS Op Amp Design using Comparators

This paper discusses the design of high gain, general purpose op amps. The op amp is based on a novel cascaded design using comparators and with structural simplicity approaching that of digital circuits. Ideally, the design tool presented here can be used to optimize gain and CMRR independent of the other op amp performance parameters. The designed op amp has 140 dB open-loop gain and 43 MHz unity gain frequency (GBW) in Berkeley Spice3f Level-2 simulation. The circuit is implemented using a 2.0 m nwell CMOS process through MOSIS. The op amp is self-biased and requires only power supplies of ±2.5 V. It occupies an area of 113 m×474 m.     

Low-Voltage BiCMOS Four-Quadrant Multiplier and Squarer

A new low-voltage low-power BiCMOS four-quadrant multiplier using cascode NPN and NMOS pairs is presented. This circuit has been fabricated in a 1 m BiCMOS process. Experimental results show that for a power supply of ±1.5 V, the linear range is over ±0.8 V with the linearity error less than 2%. The total harmonic distortion is less than 2% with input range up to ±0.8 V. The measured –3 dB bandwidth of the proposed multiplier is about 10 MHz. Its static power dissipation is about 50 W. The squarer modified from the proposed multiplier has the input range up to ±1 V. This circuit is expected to be useful in low-voltage analog signal processing applications.