Simultaneously optimizing crosstalk and power for instruction bus coupling capacitance using wire pairing

The use of deep-submicrometer (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of a chip. In this paper, we present a technique that reduces crosstalk noise on instruction buses. While previous research focuses primarily on address buses, little work can be applied efficiently to instruction buses. This is due to the complex transition behavior of instruction streams. Based on instruction sequence profiling, we exploit an architecture that encodes pairs of bus wires and permute them in order to optimize power and noise. A close to optimal architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 50.79% and power consumption up to 55% on instruction buses.     

A coding framework for low-power address and data busses

This paper presents a source-coding framework for the design of coding schemes to reduce transition activity. These schemes are suited for high-capacitance buses where the extra power dissipation due to the encoder and decoder circuitry is offset by the power savings at the bus. In this framework, a data source (characterized in a probabilistic manner) is first passed through a decorrelating function f₁. Next, a variant of entropy coding function f₂ is employed, which reduces the transition activity. The framework is then employed to derive novel encoding schemes whereby practical forms for f₁ and f₂ are proposed. Simulation results with an encoding scheme for data buses indicate an average reduction in transition activity of 36%. This translates into a reduction in total power dissipation for bus capacitances greater than 14 pF/b in 1.2 μm CMOS technology. For a typical value for bus capacitance of 50 pF/b, there is a 36% reduction in power dissipation and eight times more power savings compared to existing schemes. Simulation results with an encoding scheme for instruction address buses indicate an average reduction in transition activity by a factor of 1.5 times over known coding schemes     

Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic

This paper presents a statistical approach to synthesize an energy conscious the optimal bus width and the number of buses. The slack is exploited to maximize bus sharing and to reduce energy consumption by simultaneously scaling the voltage during the synthesis of on-chip communication bus. An assumption for bus synthesis is that a system has been partitioned and mapped onto the appropriate modules of a system-on-chip (SoC). Because of the diversity of applications to be run on a single SoC, there exists a variability of data size to be transferred among the on-chip communicating modules. This variability of data size is modeled as a random variable with a known distribution function. The resulting synthesis problem is relaxed to a convex quadratic optimization problem and solved efficiently using a convex optimization tool. The effectiveness of our approach is demonstrated by applying optimization to an automatically generated benchmark and a real-life application. By scaling voltage of a bus, a tradeoff between communication bus cost (bus width and the number of buses) and energy reduction is explored. The experimental results show the significant reduction in communication energy with scaling voltage. However, it offers a limitation to minimize the communication bus cost, if the voltage is scaled beyond its minimum limit. Furthermore, we also estimate the distribution of voltage under a random data size using an analytical method and the Monte Carlo simulation. The results show that the analytically estimated statistical parameters of voltage are close to the simulated results.     

Adaptive low-power address encoding techniques using self-organizing lists

Off-chip bus transitions are a major source of power dissipation for embedded systems. In this paper, new adaptive encoding schemes are proposed that significantly reduce transition activity on data and multiplexed address buses. These adaptive techniques are based on self-organizing lists to achieve reduction in transition activity by exploiting the spatial and temporal locality of the addresses. Also the proposed techniques do not require any extra bit lines and have minimal delay overhead. The techniques are evaluated for efficiency using a wide variety of application programs including SPEC 95 benchmark set. Unlike previous approaches that focus on instruction address buses, experiments demonstrate significant reduction in transition activity of up to 54% in data address buses and up to 59% in multiplexed address buses. The average reductions are twice those obtained using current schemes on a data address bus and more than twice those obtained on a multiplexed address bus.     

低翻转率的SoC总线组合编码算法

为降低SoC总线功耗,避开现有总线编码技术在应用上的局限,提出了一种SoC总线编码算法。算法基于总线上IP可复用的观点,采用分组BI码和TO码各自的优点,在维持SoC总线功能基本不变的同时,减少数据线和地址线的电平翻转。最后的实验结果表明：组合编码算法可以将SoC总线的平均功耗下降7．41％,是一种有效且适用于SoC总线的低功耗算法。     

Working-zone encoding for reducing the energy in microprocessoraddress buses

The energy consumption due to input-output pins is a substantial part of the overall chip consumption. To reduce this energy, this work presents the working-zone encoding (WZE) method for encoding an external address bus, based on the conjecture that programs favor a few working zones of their address space at each instant. In such cases, the method identifies these zones and sends through the bus only the offset of this reference with respect to the previous reference to that zone, along with an identifier of the current working zone. This is combined with a one-hot encoding for the offset. Several improvements to this basic strategy are also described. The approach has been applied to several address streams, broken down into instruction-only, data-only, and instruction-data traces, to evaluate the effect on separate and shared address buses. Moreover, the effect of instruction and data caches is evaluated. For the case without caches, the proposed scheme is specially beneficial for data address and shared buses, which are the cases where other codings are less effective. On the other hand, for the case with caches the best scheme for the instruction-only and data-only traces is the WZE, whereas for the instruction-data traces it is either the WZE or the bus-invert with four groups (depending on the energy overhead of these techniques)     

Bus Energy Consumption for Multilevel Signals

A comprehensive analysis of energy consumption for voltage-mode multilevel signals on a nanometer-technology bus is presented. A transition-dependent model is used which allows simplified calculation of the energy consumption. The accuracy of the approach is demonstrated using circuit simulations of three different electrical models of the bus, namely, lumped- $C$, distributed- $RC$, and distributed- $RLC$ networks. We also verify that bus energy consumption is independent of driver resistance, as predicted by the model. Finally, we present a comparative analysis of power consumption for multilevel and binary buses.      

高效能,低功耗DDR2控制器的硬件实现

随着SoC芯片内部总线带宽的需求增加,内存控制器的吞吐性能受到诸多挑战。针对提升带宽性能的问题,可以从两个方面考虑,一个办法是将内存控制器直接跟芯片内部几个主要占用带宽的模块连接,还要能够对多个通道进行智能仲裁,让他们的沟通不必经过内部的AMBA总线,甚至设计者可以利用高效能的AXI总线来加快SoC的模块之间的数据传输。另一个办法就是分析DDR2SDRAM的特性后设计出带有命令调度能力的控制器来减少读写次数,自然就能够降低SoC芯片的功耗,为了节能的考虑还要设计自动省电机制。本文为研究DDR2SDRAM控制器性能的提升提供良好的思路。     

Bus encoding for total power reduction using a leakage-aware buffer configuration

Power consumption, particularly runtime leakage, in long on-chip buses has grown to be an unacceptable portion of the total power budget due to heavy buffer insertion used to combat RC delays. In this paper, we propose a new bus encoding algorithm and circuit scheme for on-chip buses that eliminates capacitive crosstalk while simultaneously reducing total power. We utilize a buffer design approach with a selective use of high-threshold voltage transistors and couple this buffer design with a novel bus encoding scheme. The proposed encoding scheme significantly reduces total power by 26% and runtime leakage power by 42% while also eliminating capacitive crosstalk. In addition, the proposed encoding is specifically optimized to reduce the complexity of the encoding logic, allowing for a significant reduction in overhead which has not been considered in previous bus encoding work.     

高原地区不同品牌混合动力公交车适应性分析

针对昆明示范运营的混合动力公交客车,依托昆明市新能源汽车示范运行信息化管理与监控平台,采集同一公交线路上不同品牌混合动力公交客车运行数据,并对运行车辆的油耗数据和故障进行对比分析。结果表明:三种不同品牌混合动力公交客车节油效果比纯柴油公交客车明显;高原环境的差异性和技术条件的不成熟导致混合动力公交客车故障率明显高于纯柴油公交客车;不同品牌混合动力公交客车在该公交线路上的性能存在较大差异。     

Bus-invert coding for low-power I/O

Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low-power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in low-power design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the bus-invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. This is fortunate because buses are indeed most likely to have very large capacitances associated with them and consequently dissipate a lot of power     

A partitioning scheme for optimizing interconnect power

An architecture-synthesis technique for the low-power implementation of real-time applications is presented. The technique uses algorithm partitioning to preserve locality in the assignment of operations to hardware units. This results in reduced usage of long high-capacitance buses, fewer accesses to multiplexors and buffers, and more compact layouts. Experimental results show average reductions in bus and multiplexor power of 57.8 and 56.0%, respectively, resulting in an average reduction of 25.8% in total power. In addition, we analyze the effect of varying levels of partitioning on power consumption and present models for estimating bus capacitance     

Sign Bit Reduction Encoding For Low Power Applications

In this paper, a low power technique, called SBR (Sign Bit Reduction), which reduces the energy consumption in multipliers as well as data buses is proposed. The technique reduces the number of sign bits in the data transfer as well as in the multiplication process. This feature enables us to use the encoding technique for both the transfer of the data and its multiplication at the destination without any need for an intermediate decoding step. Simple circuits are used as the SBR decoder and encoder. The efficacy of the technique is evaluated for both voice and random data. The results of applying the voice data to a 16-bit multiplier implemented with this scheme shows energy consumption up to 11.4% compared to those of a 2’s complement implementation, while the number of required clock periods for the multiplication process is reduced up to 14.5%. The results of applying the SBR technique to a 30-tap FIR filter show up to 9.6% reduction in the energy consumption and up to 13.4% reduction in the required clock cycles. Finally, for voice data and random inputs, the use of the technique for a 16-bit data bus leads to an average energy consumption of up to 14.6%.     

Low-power encodings for global communication in CMOS VLSI

Technology trends and especially portable applications are adding a third dimension (power) to the previously two-dimensional (speed, area) VLSI design space. A large portion of power dissipation in high performance CMOS VLSI is due to the inherent difficulties in global communication at high rates and we propose several approaches to address the problem. These techniques can be generalized at different levels in the design process. Global communication typically involves driving large capacitive loads which inherently require significant power. However, by carefully choosing the data representation, or encoding, of these signals, the average and peak power dissipation can be minimized. Redundancy can be added in space (number of bus lines), time (number of cycles) and voltage (number of distinct amplitude levels). The proposed codes can be used on a class of terminated off-chip board-level buses with level signaling, or on tristate on-chip buses with level or transition signaling     

MFLP: a low power encoding for on chip networks

Network on chip (NoC) has been proposed as an appropriate solution for today’s on-chip communication challenges. Power dissipation has become a key factor in the NoCs because of their shrinking sizes. In this paper, we propose a new encoding approach aimed at power reduction by decreasing the number of switching activities on the buses. This approach assigns the symbols to data word in such a way that the more frequent words are sent by less power consumption. This algorithm dedicates the symbols with less ones to high probability data and uses transition signaling to transmit data. The proposed method, unlike the existing low power encoding, does not rely on spatial redundancy and keeps the width of the bus constant. Experimental evaluations show that our approach reduces the power dissipation up to 46 % with 2.70, 0.51, and 15.43 % power, critical path and area overhead in the NoCs, respectively.     

Efficient RC low-power bus encoding methods for crosstalk reduction

In on-chip buses, the RC crosstalk effect leads to serious problems, such as wire propagation delay and dynamic power dissipation. This paper presents two efficient bus-coding methods. The proposed methods simultaneously reduce more dynamic power dissipation and wire propagation delay than existing bus encoding methods. Our methods also reduce more total power consumption than other encoding methods. Simulation results show that the proposed method I reduces coupling activity by 26.7-38.2% and switching activity by 3.7%-7% on 8-bit to 32-bit data buses, respectively. The proposed method II reduces coupling activity by 27.5-39.1% and switching activity by 5.3-9% on 8-bit to 32-bit data buses, respectively. Both the proposed methods reduce dynamic power by 23.9-35.3% on 8-bit to 32-bit data buses and total propagation delay by up to 30.7-44.6% on 32-bit data buses, and eliminate the Type-4 coupling. Our methods also reduce total power consumption by 23.6-33.9%, 23.9-34.3%, and 24.1-34.6% on 8-bit to 32-bit data buses with the 0.18, 0.13, and 0.09 μm technologies, respectively.     

CAPPS: A Framework for Power–Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis

On-chip communication architectures have a significant impact on the power consumption and performance of emerging chip multiprocessor (CMP) applications. However, customization of such architectures for an application requires the exploration of a large design space. Designers need tools to rapidly explore and evaluate relevant communication architecture configurations exhibiting diverse power and performance characteristics. In this paper, we present an automated framework for fast system-level, application-specific, power–performance tradeoffs in a bus matrix communication architecture synthesis (CAPPS). Our study makes two specific contributions. First, we develop energy models for system-level exploration of bus matrix communication architectures. Second, we incorporate these models into a bus matrix synthesis flow that enables designers to efficiently explore the power–performance design space of different bus matrix configurations. Experimental results show that our energy macromodels incur less than 5% average cycle energy error across 180–65 nm technology libraries. Our early system-level power estimation approach also shows a significant speedup ranging from 1000 to 2000 $ times$ when compared with detailed gate-level power estimation. Furthermore, on applying our synthesis framework to three industrial networking CMP applications, a tradeoff space that exhibits up to 20% variation in power and up to 40% variation in performance is generated, demonstrating the usefulness of our approach.      

Power optimization of core-based systems by address bus encoding

This paper presents a solution to the problem of reducing the power dissipated by a digital system containing an intellectual proprietary core processor which repeatedly executes a special-purpose program. The proposed method relies on a novel, application-dependent low-power address bus encoding scheme. The analysis of the execution traces of a given program allows an accurate computation of the correlations that may exist between blocks of bits in consecutive patterns; this information can be successfully exploited to determine an encoding which sensibly reduces the bus transition activity. Experimental results, obtained on a set of special-purpose applications, are very satisfactory; reductions of the bus activity up to 64.8% (41.8% on average) have been achieved over the original address streams. In addition, data concerning the quality and the performance of the automatically synthesized encoding/decoding circuits, as well as the results obtained for a realistic core-based design, indicate the practical usefulness of the proposed power optimization strategy     

Optimality of Bus-Invert Coding

Dynamic power dissipation on I/O buses is an important issue for high-speed communication between chips. One can use coding techniques to reduce the number of transitions, which will reduce the dynamic power. Bus-invert coding is one popular technique for interchip buses, where the dominant contribution is from the self-capacitance of the wires. This algorithm uses an invert line to signal whether the bus data are in its original or an inverted form. While the method appears to be a greedy algorithm, we show that it is, in fact, an optimal strategy. To do so, we first represent the bus and invert line using a trellis diagram. Then, we show that applying bus-invert coding to a sequence of words gives the same result as would be obtained by using the Viterbi algorithm, which is known to be optimal. We also show that partitioning an $M$-bit bus into $P$ subbuses and using bus-invert coding on each subbus can be described as applying the Viterbi algorithm on a $2 ^P$-state trellis.      

Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses

We propose various low-latency spatial encoder circuits based on bus-invert coding for reducing peak energy and current in on-chip buses with minimum penalty on total latency. The encoders are implemented in dual-rail domino logic with interfaces for static inputs and static buses. A spatial and temporally encoded dynamic bus technique is also proposed for higher performance targets. Comparisons to standard on-chip buses of various lengths with optimal repeater configurations at the 130-nm node show the energy-delay and peak current-delay design space in which the different encoder circuits are beneficial. A 9-mm spatially encoded static bus exhibits peak energy gains beyond that achievable through repeater optimization for a single-cycle operation at 1 GHz, with delay and energy overhead of the encoding included. For throughput-constrained buses, the spatially encoded static bus can provide up to 31% reduction in peak energy, while the spatially and temporally encoded dynamic bus yields peak current reductions of more than 50% for all bus lengths. The encoder circuits show good scaling properties since the performance penalty from encoding decreases with scaled interconnects.