700V折叠漂移区高压器件新结构

A new high-voltage LDMOS with folded drift region(FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.     

Unified Breakdown Model of SOI RESURF Device with Uniform/Step/Linear Doping Profile

A unified breakdown model of SOI RESURF device with uniform,step，or linear drift region doping profile is firstly proposed.By the model,the electric field distribution and breakdown voltage are researched in detail for the step numbers from 0 to infinity.The critic electric field as the function of the geometry parameters and doping profile is derived.For the thick film device,linear doping profile can be replaced by a single or two steps doping profile in the drift region due to a considerable uniformly lateral electric field,almost ideal breakdown voltage,and simplified design and fabrication.The availability of the proposed model is verified by the good accordance among the analytical results,numerical simulations,and reported experiments.     

Complementary charge islands structure for a high voltage device of partial-SOI

A new partial-SOI(PSOI) high voltage device structure named CNCI PSOI(complementary n~+-charge islands PSOI) is proposed.CNCI PSOI is characterized by equidistant high concentration n~+ -regions on the top and bottom interfaces of a dielectric buried layer of a PSOI device.When a high voltage is applied to the device,complementary holes and electron islands are formed on the two n~+-regions on the top and bottom interfaces,therefore effectively enhancing the electric field of the dielectric buried layer(E_I) and increasing the breakdown voltage (BV),alleviating the self-heating effect(SHE) by the silicon window under the source.An analytical model of the vertical interface electric field for the CNCI PSOI is presented and the analytical results are in good agreement with the 2D simulation results.BV and E_I,of the CNCI PSOI LDMOS increase to 591 V and 512 V/μm from 216 V and 81.4 V/μm of the conventional PSOI with a lower SHE,respectively.The influence of structure parameters on the device characteristics is analyzed for the proposed device in detail.     

A novel structure in reducing the on-resistance of a VDMOS

A novel structure of a VDMOS in reducing on-resistance is proposed.With this structure,the specific on-resistance value of the VDMOS is reduced by 22%of that of the traditional VDMOS structure as the breakdown voltage maintained the same value in theory,and there is only one additional mask in processing the new structure VDMOS,which is easily fabricated.With the TCAD tool,one 200 V N-channel VDMOS with the new structure is analyzed,and simulated results show that a specific on-resistance value will reduce by 23%,and the value by 33% will be realized when the device is fabricated in three epitaxies and four buried layers.The novel structure can be widely used in the strip-gate VDMOS area.     

Design of 700 V triple RESURF nLDMOS with low on-resistance

A 700 V triple RESURF nLDMOS with a low specific on-resistance of 100 mΩ·cm² is designed. Compared with a conventional double RESURF nLDMOS whose P-type layer is located on the surface of the drift region, the P-type layer of a triple RESURF nLDMOS is located within it. The difference between the locations of the P-type layer means that a triple RESURF nLDMOS has about a 30% lower specific on-resistance at the same given breakdown voltage of 700 V. Detailed research of the influences of various parameters on breakdown voltage, specific on-resistance, as well as process tolerance is involved. The results may provide guiding principles for the design of triple RESURF nLDMOS.     

漂移区阶梯掺杂的双栅SOI LDMOS研究

A new double gate SOI LDMOS with a step doping profile in the drift region is proposed. The structure is characterized by one surface gate and another embedded gate under the P-body region. The broadened current flow path and the majority carrier accumulation layer on the side wall of the embedded gate reduce the specific on-resistance （Ron, sp）. The electric field distribution is improved due to the embedded gate and step doping profile, resulting in a high breakdown voltage （BV） and low Ron, sp. The influences of device parameters on BV and Ron, sp are investigated by simulation. The results indicate that BV is increased by 35.2% and Ron, sp is decreased by 35.1% compared to a conventional SOI LDMOS.     

具有补偿埋层的槽型埋氧层SOI高压器件新结构

A new silicon-on-insulator(SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer(CL T-LDMOS) is proposed.The high density inverse interface charges at the top surface of the buried oxide layer(BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained,which results in the enhancement of the breakdown voltage(BV).The compensation layer can provide additional P-type charges,and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field(RESURF) condition.The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the B V of the proposed device increases by 300%in comparison to a conventional SOI LDMOS,while maintaining low on-resistance.     

A new structure and its analytical breakdown model of high voltage SOI device with Step Unmovable Surface Charges of buried oxide layer

A new SOI （Silicon On Insulator） high voltage device with Step Unmovable Surface Charges （SUSC） of buried oxide layer and its analytical breakdown model are proposed in the paper. The unmovable charges are implemented into the upper surface of buried oxide layer to increase the vertical electric field and uniform the lateral one. The 2-D Poisson＇s equation is solved to demonstrate the modulation effect of the immobile interface charges and analyze the electric field and breakdown voltage with the various geometric parameters and step numbers. A new RESURF （REduce SURface Field） condition of the SOl device considering the interface charges and buried oxide is derived to maximize breakdown voltage. The analytical results are in good agreement with the numerical analysis obtained by the 2-D semiconductor devices simulator MEDICI. As a result, an 1200V breakdown voltage is firstly obtained in 3pro-thick top Si layer, 2pro-thick buried oxide layer and 70pro-length drift region using a linear doping profile of unmovable buried oxide charges.     

浮结型碳化硅肖特基势垒功率二极管的优化设计

SiC floating junction Schottky barrier diodes were simulated with software MEDICI 4.0 and their device structures were optimized based on forward and reverse electrical characteristics. Compared with the conventional power Schottky barrier diode, the device structure is featured by a highly doped drift region and embedded floating junction region, which can ensure high breakdown voltage while keeping lower specific on-state resistance, solved the contradiction between forward voltage drop and breakdown voltage. The simulation results show that with opti- mized structure parameter, the breakdown voltage can reach 4 kV and the specific on-resistance is 8.3 mΩ·cm2.     

电力静电感应晶体管大电压特性的改善

A novel structure for designing and fabricating a power static induction transistor（SIT）with excellent high breakdown voltage performance is presented.The active region of the device is designed to be surrounded by a deep trench to cut off the various probable parasitical effects that may degrade the device performance,and to avoid the parallel-current effect in particular.Three ring-shape junctions（RSJ）are arranged around the gate junction to reduce the electric field intensity.It is important to achieve maximum gate–source breakdown voltage BVGS, gate–drain breakdown voltage BVGD and blocking voltage for high power application.A number of technological methods to increase BVGD and BVGS are presented.The BVGS of the power SIT has been increased to 110 V from a previous value of 50–60 V,and the performance of the power SIT has been greatly improved.The optimal distance between two adjacent ring-shape junctions and the trench depth for the maximum BVGS of the structure are also presented.     

表面注入D-RESURF器件耐压模型

建立表面注入双重降低表面电场(D-RESURF)结构击穿电压模型。D-RESURF器件在衬底纵向电场和Pb区附加电场的影响下,漂移区电荷共享效应增强,优化漂移区掺杂浓度增大,器件导通电阻降低。分析漂移区浓度和厚度对击穿电压的影响,获得改善击穿电压和导通电阻折中关系的途径。在满足最优表面电场和完全耗尽条件下,导出吻合较好的二维RESURF判据。在理论的指导下,成功研制出900 V的D-RESURF高压器件。     

一种新型的双槽栅结构高压MOSFET

设计了一种能减小导通电阻并提高击穿电压的功率MOSFET。分析了击穿电压与外延浓度、耗尽层宽度、电阻率之间的关系。采用计算机仿真软件TCAD,对500 V、4 A下的N沟道MOSFET进行仿真验证。结果表明,相比传统VDMOS,双槽栅新型MOSFET的导通电阻减小了15.9%,反向击穿电压提升了2.8%。在工艺流程上减少了JFET退火工艺,仅增加了一层掩膜。     

4H-SiC SJ结构反向击穿电压的解析模型

提出了4H-SiC超级结结构反向击穿电压的二维解析模型。通过求解Poisson方程,获得了反向击穿电压的解析表达式,该表达式描述了反向击穿电压与器件参数如掺杂浓度、长度、宽度和温度等的关系。通过对导通电阻的优化,获得了导通电阻与击穿电压的关系为Ron∝VB1.4。并对模型结果进行了讨论,结果与二维数值仿真吻合得很好。     

具有L型栅极场板的双槽双栅绝缘体上硅器件新结构

为了降低绝缘体上硅（SOI）功率器件的比导通电阻,同时提高击穿电压,利用场板（FP）技术,提出了一种具有L型栅极场板的双槽双栅SOI器件新结构.在双槽结构的基础上,在氧化槽中形成第二栅极,并延伸形成L型栅极场板.漂移区引入的氧化槽折叠了漂移区长度,提高了击穿电压;对称的双栅结构形成双导电沟道,加宽了电流纵向传输面积,使比导通电阻显著降低;L型场板对漂移区电场进行重塑,使漂移区浓度大幅度增加,比导通电阻进一步降低.仿真结果表明：在保证最高优值条件下,相比传统SOI结构,器件尺寸相同时,新结构的击穿电压提高了123%,比导通电阻降低了32%;击穿电压相同时,新结构的比导通电阻降低了87.5%;相比双槽SOI结构,器件尺寸相同时,新结构不仅保持了双槽结构的高压特性,而且比导通电阻降低了46%.     

Design optimization of high breakdown voltage AlGaN-GaN power HEMT on an insulating substrate for R/sub ON/A-V/sub B/ tradeoff characteristics

High breakdown voltage AlGaN-GaN power high-electron mobility transistors (HEMTs) on an insulating substrate were designed for the power electronics application. The field plate structure was employed for high breakdown voltage. The field plate length, the insulator thickness and AlGaN layer doping concentration were design parameters for the breakdown voltage. The optimization of the contact length and contact resistivity reduction were effective to reduce the specific on-resistance. The tradeoff characteristics between the on-resistance and the breakdown voltage can be improved by the optimization of the above design parameters, and the on-resistance can be estimated to be about 0.6 m/spl Omega//spl middot/cm/sup 2/ for the breakdown voltage of 600 V. This on-resistance is almost the same as that for the device on a conductive substrate.     

用于功率变换的高击穿增强型AlGaN/GaN HEMTs

首次采用CF4等离子体技术实现可用于功率变换的增强性AlGaN/GaN功率器件。实验结果表明,当AlGaN/GaN器件经功率150W和时间150s等离子体轰击后,器件阈值电压从-4V被调制约为0.5V,表现为增强型。当漂移区LGD从5μm增加到15μm,器件的击穿电压从50V迅速增大到400V,电压增幅达350V。采用长度为3μm源场板结构将器件击穿电压明显地提高,击穿电压增加约为475V,且有着比硅基器件更低的比导通电阻,约为2.9mΩ.cm2。器件模拟结果表明,因源场板在远离栅边缘的漂移区中引入另一个电场强度为1.5MV/cm的电场,从而有效地释放了存在栅边缘的电场,将高达3MV/cm的电场减小至1MV/cm。微波测试结果表明,器件的特征频率fT和最大震荡频率fMAX随Vgs改变,正常工作时两参数均在千兆量级。栅宽为1mm的增强型功率管有较好的交直流和瞬态特性,正向电流约为90mA。故增强型AlGaN/GaN器件适合高压高频大功率变换的应用。     

阶梯掺杂P柱区二维类超结LDMOS的研究

提出了一种阶梯掺杂P柱区二维类超结LDMOS结构。漂移区采用P/N柱交替掺杂的方式形成纵向类超结。漂移区的P柱采用掺杂浓度从源端到漏端逐渐变低的变掺杂结构。这种变掺杂P柱区的引入对衬底辅助耗尽效应所带来的电荷不平衡问题进行了调制,使得漂移区可以充分耗尽,提高了耐压。P区变掺杂可以提高N区浓度,降低了导通电阻。与常规二维类超结LDMOS结构相比,击穿电压提高了30%,导通电阻下降了10.5%,FOM提升了87.6%,实现了击穿电压与导通电阻的良好折中。     

Numerical analysis of SOI LDMOS using a recessed source and a trench drain

A new SOI LDMOS using a recessed source and a trench drain was proposed to improve the on-characteristics at a given breakdown voltage. On-resistance and breakdown voltages of the proposed LDMOS are investigated by the two-dimensional simulator, MEDICI. The simulation results show that the on-resistance of the proposed and the conventional LDMOS are 76.3 and 129.5 mΩ mm², respectively. The on-resistance of the proposed LDMOS decreases by 41% compared to that of the conventional LDMOS at the same breakdown voltage of 36.5 V.     

JFET区注入对大功率VDMOS击穿电压和导通电阻的影响

研究了JFET区注入对大功率VDMOS器件击穿电压和导通电阻的影响,分析讨论了JFET区注入影响击穿电压的机理,并定量给出JFET区注入对导通电阻的影响.通过器件数值模拟优化JFET区注入剂量,并根据仿真结果改进器件设计,在满足击穿电压要求的前提下导通电阻降低了8％.     

A 475-V high-voltage 6H-SiC lateral MOSFET

High-voltage lateral MOSFET's on 6H- and 4H-SiC have been fabricated with 400-475 V breakdown voltage using the RESURF principle. An MOS electron inversion layer mobility of about 50 cm²/V-s is obtained on 6H-SiC wafers. This mobility is high enough such that the specific on-resistance of the 6H-SiC MOSFET's (~0.29-0.77 Ω-cm²) is limited by the resistance of the drift layer, as desired. However, the implanted drift layer resistance is about ten times higher than expected for the implant dose used. Design and process changes are described to decrease the on-resistance and increase the breakdown voltage. For 4H-SiC, extremely low mobility was obtained, which prevents satisfactory device operation