Shallow source/drain extensions for deep submicron MOSFETs using spin-on-dopants

Spin-on-dopants and rapid thermal processing have been used to form ultra-shallow n/sup +/-p junctions with metallurgical junction depths as shallow as 12 nm as determined by secondary ion mass spectroscopy. The electrical junction depth and the total charge concentration have been measured in the vicinity of the junction using electron holography and are shown to be consistent with activation efficiencies of 80%. The ultra-shallow junctions have been used as the source and drain contacts of sub-100-nm gate length MOSFETs. From electrical measurements, the authors extract a lateral diffusion length for the source and drains that is comparable to the vertical extent of the n/sup +/-p junctions.     

Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.     

深亚微米部分耗尽SOI MOSFETs STI应力效应研究

The STI stress effect is investigated based on the 0.13 m SOI process developed by the Institute of Microelectronics of the Chinese Academy of Sciences（IMECAS）. It shows that the threshold voltage and mobility are all affected by the STI stress. The absolute value of the threshold voltage of NMOS and PMOS increased by about 10%, the saturation current of NMOS decreases by about 20%, while the saturation current of PMOS increases by about 20%. It is also found that the lower temperature enhances the STI stress and then influences the device performance further. Then a macro model for this effect is proposed and is well verified.     

Design considerations of underlapped source/drain regions with the Gaussian doping profile in nano-double-gate MOSFETs: A quantum simulation

Design considerations of underlapped source/drain regions with Gaussian doping profile in nano-double-gate Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) are presented by developing a two-dimensional full quantum simulation. The simulations have been done by the self-consistent solution of 2-D Poisson–Schrodinger equations, within the none-equilibrium Green's function formalism. The effects of varying the underlapped source/drain parameters are investigated in terms of on current, gate work function, subthreshold swing, drain induced barrier lowering and device doping profile plane view. Simulation results demonstrate that we can improve the double-gate MOSFETs performance with proper selection of the underlapped source/drain parameters.     

An analytical drain current model of short-channel MOSFETs including source/drain resistance effect

In this paper, the DC characteristics of MOSFETs are investigated by means of an analytical approach with considerations of the source/drain parasitic resistance (R _S/R _D). Experimental data of MOS devices for DRAM design and results of TCAD simulation are used to verify the accuracy of theoretical calculation. It is found that both the R _S and R _D can induce a large reduction in the drain current in the linear region, but only the source resistance can cause a large reduction in the drain current in the saturation region. Moreover, the drain current deduction due to the R _S/R _D increases with decreasing channel length and oxide thickness.     

Projecting lifetime of deep submicron MOSFETs

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-μm and a 0.1-μm technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I_b,peak is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons     

Channel noise modeling of deep submicron MOSFETs

This brief presents a new channel noise model using the channel length modulation (CLM) effect to calculate the channel noise of deep submicron MOSFETs. Based on the new channel noise model, the simulated noise spectral densities of the devices fabricated in a 0.18 /spl mu/m CMOS process as a function of channel length and bias condition are compared to the channel noise directly extracted from RF noise measurements. In addition, the hot electron effect and the noise contributed from the velocity saturation region are discussed.     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

A novel elevated MOSFET source/drain structure

A vertically layered elevated drain structure is proposed which is suitable, in terms of reliability and performance for MOSFET scaling down to the 0.25-μm level without a reduction of the supply voltage below 3.3 V. In this structure, a low-doped polysilicon or crystalline silicon spacer (layer) is used to solve the hot-carrier problem. In contrast to existing device structures, which try to minimize the impact ionization rate, this structure rests on the idea that high-impact ionization and even high hot-carrier injection (HCl) rates can be tolerated as long as they are not detrimental to the device characteristics     

Simulation of carbon nanotube FETs with linear doping profile near the source and drain contacts

We propose carbon nanotube field effect transistors (CNTFETs) in which the source and drain regions of the channel (carbon nanotube) have been doped nonuniformly. The MOSFET like CNTFETs (MOSCNTs) suffer from band to band tunneling which in turn causes the ambipolar conduction. In this paper, we propose a linear doping profile for the carbon nanotube (CNT) near the source and drain contacts. This reduces the gradient of each potential barrier at the interface between the intrinsic and doped parts of the CNT and suppresses the band to band tunneling and ambipolar conduction. The device has been simulated by solving coupled Poisson and Schrödinger equations. Non-equilibrium Green’s function (NEGF) method has been used to investigate the transport properties. The uncoupled mode space approach has been used to reduce the computational burden. The calculated energy band diagrams justified improved ambipolar behavior and lower off current.     

Demonstration of submicron depletion-mode GaAs MOSFETs withnegligible drain current drift and hysteresis

We successfully fabricated submicron depletion-mode GaAs MOSFETs with negligible hysteresis and drift in drain current using Ga₂ O₃(Gd₂O₃) as the gate oxide. The 0.8-μm gate-length device shows a maximum drain current density of 450 mA/mm and a peak extrinsic transconductance of 130 mS/mm. A short-circuit current gain cutoff frequency (f_T) of 17 GHz and a maximum oscillation frequency (f_max) of 60 GHz were obtained from the 0.8 μm×60 μm device. The absence of drain current drift and hysteresis along with excellent characteristics in the submicron devices is a significant advance toward the manufacture of commercially useful GaAs MOSFETs     

A self-consistent extraction procedure for source/drain resistance in MOSFETs

A new method to determine source/drain series resistance has been developed for MOSFETs operated in linear region. The source/drain resistance (R_SD) is gate-bias dependent. Channel length reduction (ΔL) is extracted at low gate bias and chosen to be constant. All parameters extracted in this method are assumed to be independent of mask channel length for model simplicity. The method has been applied to devices with mask channel lengths of 0.23, 0.2, and 0.185 μm. The extracted parameters are consistent with the assumptions and have been validated by measured I-V characteristics.     

50 nm MOSFETs with side-gates for induced source/drain extension

50 nm long MOSFETs with side-gates were optimised in terms of the side-gate length and successfully fabricated with conventional MOS technology. The simulated and fabricated 50 nm long MOSFET shows a reasonable subthreshold swing of 81 mV/dec and a low drain induced barrier lowering of 77 mV     

漏及衬底偏压对深亚微米工艺器件总剂量效应的影响

本文对采用0.18?m工艺制造的NMOS器件辐射总剂量效应进行了研究。对晶体管进行了不同剂量的₆₀Co辐射实验,同时测试了辐照前后晶体管电学参数随漏、衬底偏压的变化的规律。采用STI寄生晶体管模型来解释晶体管的关态漏电流及阈值电压漂移性质。3D器件仿真验证了模型的准确性。     

Novel self-aligned polysilicon-gate MOSFETs with polysilicon source and drain

A novel self-aligned technique is described for self-aligning a polysilicon gate in devices with polysilicon source and drain regions. The technique is demonstrated for two types of polysilicon source and drain devices. In one type of device, the polysilicon serves as the source of dopant for diffused source and drain junctions. In the second type, the polysilicon, together with an underlying interfacial oxide, forms a tunneling CIS (conductor-thin insulator-semiconductor) structure. The characteristics of devices of both types fabricated under almost identical conditions using the new self-alignment technique are compared.     

Analytical modeling of thermal noise in deep submicron MOSFETs

An analytical modeling of MOSFETs channel noise is proposed by considering short-channel effects of deep submicron MOSFETs, such as mobility degradation, hot carrier, bulk charge, and channel length modulation effect. The model is only dependent on bias, size, and technology of MOSFETs, and hence is suitable for low-noise RF IC design. Noise parameters of MOSFETs are achieved and good agreement between calculated and measured results is demonstrated.     

Modeling of drain current overshoot and recombination lifetimeextraction in floating-body submicron SOI MOSFETs

This work reports on a new general modeling of recombination-based mechanisms related to electrically floating-body partially-depleted (PD) SOI MOSFETs. The model describes drain current overshoots induced when turning on the transistor gate and suggests a novel extraction method for the recombination lifetime in the silicon film. We show that the recombination process associated with drain current overshoots in PD silicon-on-insulator (SOI) MOSFETs takes place mainly in the depletion region and not in the neutral region as in case of pulsed MOS capacitors. Associated with existing techniques for generation lifetime extraction, our model offers, for the first time, the possibility of complete and rapid characterization for both generation and recombination lifetime using drain current transients in floating-body SOI MOSFETs. The model is used in order to characterize submicron SOI devices, allowing a thorough investigation of technological parameters impact on floating-body-induced transient mechanisms     

The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance     

On the extraction of the source and drain series resistances of MOSFETs

This article reviews and scrutinizes various proposed methods to extract the individual values of drain and source resistances (R_D and R_S) of MOSFETs, which are important device parameters for modeling and circuit simulation. In general, these methods contain three basic steps: (1) the extraction of the total drain and source resistance (R_D+R_S); (2) the extraction of the difference between the drain and the source resistances (R_D−R_S); and (3) the calculation of R_D and R_S from the knowledge of (R_D+R_S) and (R_D−R_S). These methods are tested and compared in the environments of circuit simulator, device simulation and measurements.