多管组合曲率补偿低压带隙基准源

A new bandgap reference(BGR) curvature compensation technology is proposed,which is a kind of multiple transistor combination.On the basis of the existing first-order bandgap reference technology,a compensation current circuit consisting of a sink current branch and a source current branch is added.The BGR was designed and simulated by using Semiconductor Manufacturing International Corporation(SMIC) 0.18μm CMOS process.The simulation results showed that when the power supply voltage was 1 V,the temperature coefficient of the BGR was 2.08 ppm/℃with the temperature range from—40 to 125℃,the power supply rejection ratio (PSRR) was—64.77 dB and the linear regulation was 0.44 mV/V with the supply power changing from 0.85 to 1.8 V.     

A new curvature-corrected bandgap reference

A bandgap-voltage reference implemented with a new accurate circuit configuration for compensating the thermal nonlinearity of the base-emitter voltage is described. With this device, a temperature coefficient of 0.5 ppm//spl deg/C over the temperature range -25 to +85/spl deg/C has been achieved. The minimum required supply voltage amounts to only 5.5 V.     

A low-voltage CMOS bandgap reference

The CMOS bandgap voltage reference described here uses the bipolar substrate-transistor and the bipolar-like source-to-drain transfer characteristics of MOS transistors in weak inversion to implement a voltage source that is proportional to absolute temperature (PTAT). A first version of PTAT source is derived from a circuit described previously. A second version is based on a novel cell that can be stacked to obtain the desired voltage. Both versions operate down to 1.3 V with a current drain below 1 /spl mu/A. A stability of 3 mV over 100/spl deg/C has been obtained with a few nonadjusted samples. Experimental results suggest some possible improvements to extend this stability to every circuit.     

Low-voltage low-power superior-order curvature-corrected voltage reference

A new superior-order curvature-corrected voltage reference will be presented. In order to improve the temperature behavior of the circuit, a double differential structure will be used, implementing the linear and the superior-order curvature corrections. An original ComplemenTary with Absolute Temperature voltage generator will be proposed, using exclusively MOS transistors biased in weak inversion for a low power operation of the voltage reference, having two great advantages: an important reducing of the circuit silicon area and an improved accuracy (matched resistors being replaced by matched MOS active devices). The superior-order curvature-correction will be implemented by taking the difference between two gate-source voltages of subthreshold-operated MOS transistors, biased at drain currents having different temperature dependencies: PTAT (ProporTional with Absolute Temperature) and square PTAT. In order to obtain a low-voltage operation of the circuit, the classical MOS transistor, which implements the elementary voltage reference, could be replaced by a Dynamic Threshold MOS transistor. The SPICE simulations confirm the theoretical estimated results, showing a temperature coefficient under 6 ppm/K for an extended input range 223 K < T < 333 K and for a supply voltage of 1.8 V and a current consumption of about 1 μA.     

A precision curvature-compensated CMOS bandgap reference

A precision curvature-compensated switched-capacitor bandgap reference is described which uses a standard digital CMOS process and achieves temperature stability significantly lower than has previously been reported for CMOS circuits. The theoretically achievable temperature coefficient approaches 10 ppm//spl deg/C over the commercial temperature range and uses a straightforward room temperature trim procedure. Experimental data from monolithic prototype samples are presented which are consistent with theoretical predictions. The experimental prototype circuit occupies 3500 mil/SUP 2/ and dissipates 12 mW with /spl plusmn/5 V power supplies. The proposed reference is believed to be suited for use in monolithic data acquisition systems with resolutions of 10 to 12 bits.     

A simple three-terminal IC bandgap reference

A new configuration for realization of a stabilized bandgap voltage is described. The new two-transistor circuit uses collector current sensing to eliminate errors due to base current. Because the stabilized voltage appears at a high impedance point, the application to circuits with higher output voltage is simplified. Incorporation of the new two-transistor cell in a three-terminal 2.5-V monolithic reference is described. The complete circuit is outlined in functional detail together with analytical methods used in the design. The analytical results include sensitivity coefficients, gain and frequency response parameters, and biasing for optimum temperature performance. The performance of the monolithic circuit, which includes temperature coefficients of 5 ppm//spl deg/C over the military temperature range, is reported.     

A CMOS bandgap reference without resistors

This paper describes a bandgap reference fabricated in a 0.5-μm digital CMOS technology without resistors. The circuit uses ratioed transistors biased in strong inversion together with the inverse-function technique to produce a temperature-insensitive gain applied to the proportional to absolute temperature (PTAT) term in the reference. After trimming, the peak-to-peak output voltage change is 9.4 mV from 0°C to 70°C. It occupies 0.4 mm² and dissipates 1.4 mW from a 3.7-V supply     

一种新型高精度曲率补偿CMOS带隙基准源

本文提出了一种兼容标准CMOS工艺的高阶曲率补偿带隙基准源。通过利用电压电流转换器和基区-发射区间PN结的电压电流特性,获得正比于VTln(T)的补偿量,从而实现基准源高阶温度补偿。基于CSMC 0.5-μm CMOS工艺进行流片验证,实验结果表明该基准在3.6V电源电压下可以达到3.9 ppm/℃的温度系数,高达72 dB的电源抑制比,并且优于0.304mV/V的线性调整率。电路最大仅消耗42 μA供电电流。     

A novel precision curvature-compensated bandgap reference

A high precision high-order curvature-compensated bandgap reference compatible with the standard CMOS process, which uses a compensation proportional to V_TlnT realized by utilizing voltage to current converters and the voltage current characteristics of a base-emitter junction, is presented. Experiment results of the proposed bandgap reference implemented with the CSMC 0.5-μm CMOS process demonstrate that a temperature coefficient of 3.9 ppm/℃ is realized at 3.6 V power supply, a power supply rejection ratio of 72 dB is achieved, and the line regulation is better than 0.304 mV/V dissipating a maximum supply current of 42μA.     

一种低电压高精度带隙基准电压设计

本文对传统的带隙基准源电路进行了详细的分析,并对近些年来一些新出现的技术进行总结,采用二阶曲率补偿技术,提出了一种能在较低电压下工作的高精度电压基准源.本设计基于CSMC0.35μm工艺仿真,结果表明电源电压为1.0 V时,电路达到稳定工作状态,在-25-125℃的温度范围内,输出电压为530 mV,平均温度系数为4....     

一种高阶温度补偿带隙基准

文章基于通过控制mos管的栅极电压产生随着温度变化的补偿电流原理,采用0.5μm BCD30 V工艺,设计一款二阶温度补偿带隙基准电压源,仿真结果表明,电源电压等于7 V时,电路能够产生一个稳定的1.24 V输出电压,在﹣40~125℃内,最小温度系数为3.47×10-6/℃,最大温度系数为6.5×10-6/℃,输出电压偏差3 m V。在7 V电源电压下,100 k Hz频率下电源抑制比为65 d B。     

一种高电源抑制比的CMOS带隙基准电压源设计

介绍一种基于CSMC0.5μm工艺的低温漂高电源抑制比带隙基准电路。本文在原有Banba带隙基准电路的基础上,通过采用共源共栅电流镜结构和引入负反馈环路的方法,大大提高了整体电路的电源抑制比。Spectre仿真分析结果表明:在-40~100℃的温度范围内,输出电压摆动仅为1.7 mV,在低频时达到100 dB以上的电源抑制比(PSRR),整个电路功耗仅仅只有30μA。可以很好地应用在低功耗高电源抑制比的LDO芯片设计中。     

一种带隙基准电压源设计

基准电压源是在电路系统中为其它功能模块提供高精度的电压基准,它是模拟集成电路和混合集成电路中非常重要的模块。文中主要研究了带隙基准基本原理的基础上,设计了一款应用于折叠插值ADC中粗量化电路部分CMOS带隙基准源。最后通过Pspice仿真给出了实验仿真的结果。     

An integrated bandgap reference

Using well-known principles a configuration has been developed for an IC reference voltage source with good performance with respect to the temperature dependency and 1/f noise. A bread-board model of this configuration has been tested. In the temperature range of 0-70/spl deg/C, the output voltage variations were less than /spl plusmn/70 ppm at an output voltage of about 2.5 V and zero load current. Low-frequency noise in a bandwidth 0.003 Hz相似文献   

一种中心值精确可调的高性能带隙基准电压源

不同的集成电路制造工艺,对平衡温度时的带隙基准电压值有影响.为此,本文提出了通过改变带隙基准电压输出级电路结构的方法,实现了在基准电路内部可精确调整基准电压中心值,以满足在不同工艺条件下电路系统对基准电压中心值的精度要求.本芯片根据CSMC公司0.50μm CMOS混合信号工艺模型设计并进行流片.测试结果表明,本文提出的方法能调整基准电压中心值.利用这种方法,可以实现带隙基准电压中心值宽范围的可调,使基准电压的输出完全符合系统所需.     

一种用于LED背光驱动的带隙基准源

依据带隙基准源的基本原理设计了一种用于LED背光驱动芯片的带隙基准源,与传统带隙基准源相比,设计的带隙基准源采用了无运放电路结构。该电路在基于0.5mm BCD工艺下完成设计,通过Hspice仿真表明,当温度在–40~+125℃变化时,基准源输出电压在1.227 5~1.229 8 V之间变化,温漂系数仅为11.36×10~(–6),基准源供电电压在6~8 V之间变化时,基准源输出电压相对变化量为0.85%,满足了设计要求。     

A CMOS bandgap reference for differential signal processing

A switched-capacitor fully differential bandgap reference that uses a standard double-poly CMOS process is presented. It generates a differential reference voltage of 6.2 V with a standard deviation of about 24 mV and a typical temperature stability of 15.2 p.p.m./°C over an extended temperature range from -40 to +85°C. These performance results are obtained without using any trimming in mass production. The bandgap reference only occupies 730 mil² and dissipates 4.8 mW at±5-V power supplies. A measured power supply rejection of about 90 dB until 500 kHz is the best ever reported at high frequency     

A floating CMOS bandgap voltage reference for differentialapplications

The circuit is suitable for precision mixed-mode systems using the differential approach, especially for the case of single-supply operation. An experimental prototype, realized in a 2-μm CMOS technology, generates a continuous-time low-impedance voltage of 2.48 V±24 mV before trimming. The temperature coefficient measured on 30 samples ranges from -20 to L32 p.p.m./°C in the temperature range from 0 to 100°C. Thanks to the differential approach, a high-frequency power supply rejection of -50 dB at 100 kHz was achieved. The active area of the chip is 1800 mil² and the circuit dissipates 6 mW when operated from a single 5-V supply     

一种新颖分段曲率补偿的带隙基准设计

基于0.5 μm CMOS工艺,设计了一种采用新颖分段曲率补偿技术的低温漂带隙基准源,利用2种不同的电流补偿结构,分别在中温和高温阶段引入正温度系数补偿电流,使得基准电压的温度特性曲线在中温和高温阶段各产生2个新的极值点,与一般的分段曲率补偿带隙基准相比,提高了补偿效率。利用Cadence软件对电路进行设计与仿真,仿真结果表明,在-40~190 ℃温度范围内,输入电压为5 V时,输出基准电压为1.231 V,温漂系数为0.885 ppm/℃,低频时电源抑制比(PSRR)为-75~-109 dB。