13 bit 50 MS/s CMOS流水线ADC的设计

介绍了一种新的流水线ADC校准算法,并利用该校准算法完成了一个13 bit,50 MS/s流水线ADC的设计.该校准算法对级电路的比较器和后级电路的输出码字的出现频率进行统计,得到各个级电路输出位的真实权值,可以同时校准多种非理想因素如运放有限增益、电容失配等造成的误差.电路采用UMC 0.18μm混合工艺,1.8 V电源电压.通过SPECTRE仿真获得晶体管级级电路的输入输出关系,将其结果导入顶层行为级模型进行校准.仿真结果表明,在50 MHz采样率、5 MHz输入信号下,通过校准算法SFDR由44.1 dB提升至102.2 dB,SNDR由40.9 dB提升至79.9 dB,ENOB由6.5 bit提升至12.98 bit.     

一种SAR ADC电容失配自测量与数字校准技术

为了解决高分辨率逐次逼近模数转换器(SAR ADC)中,电容式数模转换器(DAC)的电容失配导致精度下降的问题,提出了一种电容失配自测量方法,以及一种可适用于各种差分电容DAC设计的低复杂度的前台数字校准方法。该方法利用自身电容阵列及比较器完成位电容失配测量,基于电容失配的转换曲线分析,对每一位输出的权重进行修正,得到实际DAC电容大小对应的正确权重,完成数字校准。数模混合电路仿真结果表明,引入电容失配的16位SAR ADC,经该方法校准后,有效位数由10.74 bit提高到15.38 bit。     

基于数字自校准的14位SAR ADC的设计

为了降低电容型模数转换器（ADC）中的电容失配带来的非线性影响,提出了一种基于复用低位电容自校准的逐次逼近型（SAR）ADC电路结构,利用低位电容转化高位电容失配引起的误差电压,实现高位电容失配校准。在55 nm CMOS工艺下实现了该ADC结构。该结构ADC工作过程为失调误差提取与正常转换两阶段,失调误差提取阶段中利用低位电容将高位电容失配产生的误差电压转换为误差码并存储,将误差码与正常转化数字码求和得到最终的数字输出,实现电容失配自校准。为了提高ADC采样速率,该结构通过分段结构将电容阵列分为三段降低了单位电容数量。仿真结果表明,在1.2V电源电压,80 MSPS采样速率下,引入电容失配后电路功耗为3.72 m W,有效位数为13.45 bit,信噪失真比（SNDR）为82.75 dB,相比未校准分别提高4.41 bit,26.58 dB。     

一种用于流水线模数转换器的电容失配校准方法

对于流水线模数转换器(ADC),电容失配是一种主要的非线性误差源. 为了减小电容失配误差,提出了一种电容失配校准的方法. 该方法通过一种电荷相加、电容交换和电荷反转移的电路技术,可将电容失配误差减小至其2次项. 基于所提出的方法,设计了一种0.6μm CMOS,13b, 2MS/s的流水线ADC实验芯片. 对所设计的实验芯片进行测试,得到了0.5LSB的DNL和2.5LSB的INL,并且当以614kHz的采样率对19.2kHz的输入进行转换时,得到了71.2dB的SFDR和64.1dB的SNDR,当以2MHz的采样率对125kHz的输入进行转换时,得到了70.6dB的SFDR和62.22dB的SNDR. 以上结果表明,ADC得到了超出电容匹配精度的线性度,证明了所采用的电容失配校准方法的有效性.     

一种用于流水线模数转换器的电容失配校准方法

对于流水线模数转换器(ADC),电容失配是一种主要的非线性误差源.为了减小电容失配误差,提出了一种电容失配校准的方法.该方法通过一种电荷相加、电容交换和电荷反转移的电路技术,可将电容失配误差减小至其2次项.基于所提出的方法,设计了一种0.6μm CMOS,13b,2MS/s的流水线ADC实验芯片.对所设计的实验芯片进行测试,得到了0.5LSB的DNL和2.5LSB的INL,并且当以614kHz的采样率对19.2kHz的输入进行转换时,得到了71.2dB的SFDR和64.1dB的SNDR,当以2MHz的采样率对125kHz的输入进行转换时,得到了70.6dB的SFDR和62.22dB的SNDR以上结果表明,ADC得到了超出电容匹配精度的线性度,证明了所采用的电容失配校准方法的有效性.     

基于流水线ADC的MDAC电容失配校准研究

针对MDAC中采样电容失配会降低ADC输出非线性性能的问题,提出了一种流水线ADC的前台数字校准技术。该前台数字校准技术利用ADC输出积分非线性的相对偏差提取误差,利用简单的多路选择运算单元进行误差补偿。在此基础上,采用Verilog HDL实现了RTL级描述并成功流片。仿真和测试结果表明,该校准算法能够提升ADC输出性能。     

高精度SAR ADC电容阵列设计及校准算法

在高精度逐次逼近寄存器模数转换器(SAR ADC)中,电容阵列是SAR ADC的核心之一。电容阵列中的电容失配问题是导致转换精度降低的一个重要原因。为了尽可能改善这一问题,设计了一种6+6+6分段电容阵列,并且基于这种阵列设计了权重迭代算法的前台数字校准。该方法不需要额外的电容阵列,利用自身的电容阵列与比较器量化出电容失配,计算出每一位输出码的权重校准系数,用来对正常量化出的输出码进行编码,实现校准功能。仿真结果表明,引入电容失配的18 bit SAR ADC经过该算法校准后,信噪比(SNR)从77.6 dB提升到107.6 dB,无杂散动态范围(SFDR)从89.8 dB提升到125.6 dB,有效位数(ENOB)从12.54 bit提升到17.54 bit。在SMIC 0.18μm工艺下,该校准算法对高精度SAR ADC的动态性能具有较大提升。     

一种16位电流舵DAC的高精度前台校准方法

基于28 nm CMOS工艺,采用一种高精度的前台校准技术设计了一款16 bit电流舵数模转换器（Digitalto-analog converter,DAC）电路。该前台校准算法对16 bit数据对应的所有电流源进行校准,并且使用的电流源只有两种大小,降低校准难度的同时也提升了校准的精度。该校准电路引入了两种校准补充电流,分别用于温度和输出电流变化引起电流源失配的补偿,进一步减小了DAC电流源的失配,有效提高了DAC的整体性能。采用校准后,在-40～85℃温度范围内,微分非线性≤0.8 LSB,积分非线性≤2.0 LSB,200 MHz输出信号下无杂散动态范围≥75.3 dB。该校准方法提高了DAC的温度稳定性。     

一种基于统计的流水线ADC数字后台校准方法

高精度流水线ADC的设计需要校准技术来提高其转换精度.基于统计的数字后台校准方法无需校准信号,直接通过对输出的统计得到误差值的大小,将其从数字输出中移除从而消除了ADC输出非线性.将该校准方法应用于14bit流水线ADC中,仿真结果表明校准后信噪失真比SNR为76.9dB,无杂散动态范围SFDR为73.9dB,有效精度ENOB从9bit提高到12.5bit.     

基于16位SAR模数转换器的误差校准方法

为了实现较高精度(16位及更高)的逐次逼近(SAR)ADC,提出了一种误差自动校准技术。考虑到芯片面积、功耗和精度的折中,采用了电荷再分配分段电容DAC结构,并采用准差分输入方式提高ADC的信噪比。为了消除电容失配引入的误差,提出了一种误差自动校准算法,利用误差校准DAC阵列对电容失配误差进行量化并存储在RAM中,在AD转换过程中实现误差消除。     

基于码密度统计的流水线模数转换器校准算法研究

本文提出了一种用于校准流水线模数转换器线性误差的数字后台校准算法。该算法不需要修改转换器级电路部分,只需要一部分用于统计模数转换器输出码的数字电路即可完成。通过分析流水线模数转换器输出的数字码,该算法可以计算出每一级级电路对应的权重。本文利用一个14位的流水线模数转换器来验证该算法。测试结果显示,转换器的积分非线性由90LSB下降到0.8LSB,微分非线性由2LSB下降到0.3LSB;信噪失真比从38dB提高到66.5dB,总谐波失真从-37dB下降到-80dB。转换器的线性度有很大提高。     

应用于流水线ADC的LMS自适应校准算法与FPGA实现

研究了应用于流水线模数转换器(ADC)的LMS自适应数字校准算法及其FPGA实现。该校准算法可用于校准大多数已知的误差,包括非线性运算放大器的有限增益、电容失配,以及比较器的失调等。通过Simulink软件,对一个12位160 MS/s的流水线ADC进行建模。采用LMS自适应校准算法对该流水线ADC进行校准,并将算法在Virtex-5上实现了硬件设计。实验结果表明, 输入信号频率为58.63 MHz时,流水线ADC的无杂散动态范围(SFDR)和有效位(ENOB)分别由校准前的46.31 dB和7.32位提高到校准后的82.03 dB和11.12位。     

A Split-Based Digital Background Calibration Technique in Pipelined ADCs

A digital background calibration technique is proposed to correct gain errors in pipelined analog-to-digital converters (ADCs). The calibration technique performs the error estimation and the adaptive error correction based on the concept of split ADCs. With the 1- or 1.5-bit realization in pipelined stages, capacitor-mismatch errors can be merged with gain errors, and the proposed calibration technique can be utilized. Behavioral simulations show that the signal-to-noise-and-distortion ratio of a 12-bit pipelined ADC with an 8-bit gain accuracy and the capacitor mismatch $sigma = 0.125%$ can be improved from 56.4 to 73.8 dB. The calibration process converges in approximately 200 000 cycles.      

Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching

We propose a new digital background calibration method for capacitor mismatches in pipelined analog-to-digital converters (ADCs). It combines commutated feedback capacitor switching with a background digital correlation loop to extract capacitor mismatch information, which is subsequently used to correct errors caused by the mismatch. This is an all-digital technique requiring minimal extra digital circuits, and is applicable to both single-bit and multibit-per-stage architectures. Simulations with a 15-stage, 1.5-bit-per-stage pipelined ADC with capacitor mismatch of $sigma=0.25hbox{%}$ in each stage show that the technique improves signal-to-noise-distortion ratio from 62 dB (10 bits) to 94 dB (15.4 bits).      

采用分段平移技术校正流水线A/D转换器级间增益的方法

分析了流水线A/D转换器采样电容与反馈电容之间的增益失配,探究了运放有限增益与流水线残差输出及A/D转换器输出的关系,建立了精确的系统模型。通过建立14位流水线A/D转换器Verilog-A的行为级模型,在数字域对流水线A/D转换器输出数字码进行分段平移。在第一级级间增益误差达到±0.012 5时,校正前信噪比仅为62 dB,校正后信噪比提升到85 dB。提出的校正方法可有效补偿由流水线级间增益导致的数字输出不连续和线性度下降。     

A 14-b 32 MS/s pipelined ADC with fast convergence comprehensive background calibration

This paper presents the first aggressively calibrated 14-b 32 MS/s pipelined ADC. The design uses a comprehensive digital background calibration engine that compensates for linear and nonlinear errors as well as capacitor mismatch in multi-bit DAC. Background calibration techniques that estimate the errors by correlating the output of ADC with the calibration signal have a very slow convergence rate. This paper also presents a fully digital technique to speed up the convergence in the error estimation procedure. By digitally filtering the input signal during the error estimation, the convergence rate of the calibration has been improved significantly. Implemented in TSMC 0.25 μm technology, the pipelined ADC consumes 75 mA from 2.5 V and occupies 2.8 mm² of active area. Measurement results show that calibration significantly improved dynamic (SNDR, SFDR) as well as static (DNL, INL) performance of the ADC.     

PN-assisted digital background calibration of two-step ADC to over 14-bit accuracy

A new non-binary multiplying digital-to-analog converter (MDAC) structure with signal-dependent dithering scaling technique is proposed in this paper. A full digital background calibration algorithm based on pseudo-random dithers injection is used to calibrate the nonlinear errors of MDAC. By measuring sampling capacitor mismatch and op-amp gain errors of the pipelined analog-to-digital converter (ADC) in background, the errors will be greatly reduced by the proposed calibration algorithm. At the same time, the signal-dependent dithering scaling technique provides a swing margin to the injected pseudo-random signal. By using this technique, the errors caused by the capacitor mismatch and op-amp gain errors can be calibrated at the same time. What’s more, this method greatly accelerates the convergence speed. A two-stage 14-bit pipelined ADC is used to simulate and verify the proposed algorithm. The simulation results indicate the effectiveness of the technique, in which the signal-to-noise plus distortion (SNDR) and the spurious-free dynamic range (SFDR) performance of a 14-bit two-step ADC are improved from 49.12 and 56.25 to 85.68 and 102.23 dB with the input frequency being 0.06 * f _s , respectively. The SFDR is more than 98 dB. The SNDR reaches 84 dB in the whole Nyquist bandwidth after calibration. Integral nonlinearity is improved from 80 to 1.5 least significant bits after calibration.     

A 12-bit 20-Msample/s pipelined analog-to-digital converter with nested digital background calibration

A 12-bit 20-Msample/s pipelined analog-to-digital converter (ADC) is calibrated in the background using an algorithmic ADC, which is itself calibrated in the foreground. The overall calibration architecture is nested. The calibration overcomes the circuit nonidealities caused by capacitor mismatch and finite operational amplifier (opamp) gain both in the pipelined ADC and the algorithmic ADC. With a 58-kHz sinusoidal input, test results show that the pipelined ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 70.8 dB, a peak spurious-free dynamic range (SFDR) of 93.3 dB, a total harmonic distortion (THD) of -92.9 dB, and a peak integral nonlinearity (INL) of 0.47 least significant bit (LSB). The total power dissipation is 254 mW from 3.3 V. The active area is 7.5 mm/sup 2/ in 0.35-/spl mu/m CMOS.     

一种时间交叉采样ADC失调与增益误差校准方案

针对时间交叉采样模数转换器的失调、增益误差提出了校准方案.该方案主要通过各通道模数转换器向同一通道校准的方法,首先计算出误差参数,再根据误差参数对数字量进行校准.采用该校准方案对四通道10位640 Msps模数转换器进行校准,经MATlAB仿真,结果表明输入频率为79.14 MHz时,校准后的无杂散动态范围为75.17 dB,信噪比为55.98 dB,有效精度为9.01 bit,比较准前分别提高了24.6 dB、6.47 dB、1.08 bit.