一种片内集成飞电容的自适应开关电容DC-DC

提出一种电容片内集成、高效率升压模式的DC-DC电源管理芯片,较普通结构相比,文中提出的电路结构具有6组2×,3组3×,2组4×升压模型共11种工作模式,并具有低纹波等优点。通过MIM电容与积累型NMOS电容串联的方式,提高单位面积容值,使得总电容面积大幅减小。采用SMIC 0.18μm CMOS工艺,利用Cadence工具对电路进行仿真验证,所提出自适应开关电容升压电路,在输出电压为3 V时,其效率最高可达到83.6%。在开关频率为20 MHz时,输入电压范围为1~1.8 V,所需总片内集成电容总面积为900 μm×900 μm,输出电压纹波＜40 mV     

负电容声子晶体带隙特性研究

外接负电容的声子晶体具有可调的等效弹性模量。通过改变外接负电容的电容值,可改变等效介质的弹性模量。该文理论计算了等效弹性模量,结合位移矢量分析了带隙的产生原因及其影响因素。研究表明,外接负电容声子晶体具有可调的低频带隙,带隙随着外接负电容的变化而变化。     

高稳定度和宽电源电压范围晶体振荡器芯片设计

基于0.6μm CMOS混合信号工艺设计了一款高稳定度、宽电源电压范围的晶体振荡器芯片。该芯片片内集成具有优异频率响应的振荡器电容和反馈电阻,只需外接石英晶体即可提供高稳定时钟源。测试结果表明:芯片最高工作频率可达40MHz;在振荡频率12MHz、负载电容15pF、电源电压从2.7V到5.5V变化时其频率随电源电压变化率小于1×10-6;电源电压为5V时芯片消耗总电流小于4mA。     

标准数字CMOS工艺中LC谐振回路的改进和应用

提出了一种在标准数字CMOS工艺条件下,提高片上螺旋电感性能的实用方法,以及在缺少双层多晶硅电容的情况下,可以大大节约芯片面积的一种电容实现方法.介绍了这两种方法在电路设计中的一种应用,即利用0.35μm 1P4M标准数字CMOS工艺实现的、单片集成的LC压控振荡器.     

Class-AB型低功耗轨到轨CMOS模拟缓冲器设计

设计了一种新型Class-AB轨到轨CMOS单位增益模拟缓冲器。实现电路基于并行互补差分对输入,在保持整个电路简洁的同时,可提供低功耗Class-AB输出方式,使电路实现轨到轨的电平跟踪功能。使用0.35μm工艺库仿真,结果表明,该缓冲器具备较大的电容驱动能力,可以应用在具有大电容负载的场合。使用特殊设计方式,使电路主极点移动到输出节点上,彻底解决了大负载电容下电路的稳定性问题。电路使用3.3V单极性电源,在负载电阻大于1MΩ时,可以提供完全的轨到轨输出。在20pF负载电容时,输出摆率为+7.9V/μs和-5.8V/μs,整个电路的静态功耗仅为184μW。     

标准数字CMOS工艺中LC谐振回路的改进和应用

提出了一种在标准数字CMOS工艺条件下,提高片上螺旋电感性能的实用方法,以及在缺少双层多晶硅电容的情况下,可以大大节约芯片面积的一种电容实现方法.介绍了这两种方法在电路设计中的一种应用,即利用0 .35 μm1P4 M标准数字CMOS工艺实现的、单片集成的L C压控振荡器.     

应用于TD-SCDMA/LTE/LTE-Advanced收发机的多频多模CMOS射频接收前端电路设计

设计了应用于TD-SCDMA/LTE/LTE-Advanced收发机中的多频段、多模式射频接收前端电路. 该前端电路采用直接变频结构,包含两个可调谐差分低噪声放大器、一个正交混频器和两个中频放大器。其中,两个独立的可调谐低噪声放大器覆盖了4个射频频段,在较低的功耗下实现足够的增益和噪声性能. 并且利用开关电容阵列来调节低噪声放大器的谐振频率点. 低噪声放大器通过混频器的驱动级跨导晶体管实现结合。正交混频器采用折叠式双平衡吉尔伯特结构,利用PMOS晶体管作为本振信号的开关对,从而降低1/f噪声. 前端电路具有3种增益模式以获得更大的动态范围. 模式配置和频段选择功能都由片上的SPI模块控制. 该射频前端电路采用TSMC0.18um RF CMOS工艺实现,芯片面积为1.3 mm2. 全部频段上测量的转换增益高于43dB,双边带噪声系数低于3.5dB. 整个电路在1.8V供电电压下,消耗电流约31mA。     

一种高精度可调频张弛振荡器的设计

设计了一种高精度、宽频率范围的张弛振荡器.利用两级运放组成负反馈回路,将振荡器输入端电压钳位,通过调整外接电阻调节电容充电电流;主振荡电路采用三端比较器设计,结构简单易于实现;针对电源系统多相分布应用需求,设计了模式选择电路,可实现片外时钟同步模式工作.电路采用0.25μm 60 V BCD工艺实现.仿真结果表明,振荡...     

博通BCM2070单片蓝牙方案

方案介绍 BCM2070单片蓝牙2.1 EDR解决方案,集成了可单独使用的基带处理器和高性能2.4GHz收发器.和Bluetooth 2.1与以前的所有标准兼容.采用先进的65-nm LP CMOS技术制造而成,能以最小的占位面积和最低的成本实现蓝牙系统,且能在所有操作模式下实现最低的电流消耗.     

基于MOCCCⅡ的双模式二阶通用滤波器

提出了一种基于多输出端口电流控制电流传输器(MOCCCII,multiple outputs current controlled conveyor)的双模式二阶通用滤波器,该滤波器结构简单,仅由5个有源器件、2个接地电容构成,无须外接电阻.该电路在不改变内部电路结构的情况下能实现电压模式和电流模式滤波器,且每一种工作模式都能实现高通、低通、带通等多种滤波功能,因此该电路具有通用性.面向实际电路完成了PSPICE仿真,结果表明提出的电路正确有效.     

A universal 0.03-mm2 one-pin crystal oscillator in CMOS

A one-pin crystal oscillator with an integrated load capacitance of 15 pF has been realized in a standard 0.35-μm CMOS technology. Due to the structure of the oscillator and the use of MOS gate capacitance for the load capacitors, the chip area can be very small. The total active area including load capacitors is less than 0.03 mm². The design can be operated with supply voltages in the range of 1.4-3.6 V and allows crystal frequencies in the range of 3-30 MHz. The current consumption of the oscillator core is 180 μA at 10 MHz with 3.3-V power supply. It produces a rail-to-rail output swing, regulated by an amplitude control loop, and has the same flexibility and ease of frequency tuning as a common Pierce oscillator. As no special IC process options are required, the design is very suitable for clock generation in digital very-large-scale-integration chips     

Design considerations for high-frequency crystal oscillators

The deleterious effects of crystal shunt capacitance and series resistance on the performance of series-mode oscillators are discussed. When the parasitic capacitance across the crystal significantly modifies the transconductance of the amplifying stage the circuits can become susceptible to a parasitic second mode of oscillation above the series-resonance frequency of the crystal. A simple model that can sufficiently describe such crystal oscillator circuits was developed and used to derive simple design equations that can accurately predict the behavior of these circuits. The design equations should be especially useful for a reliable design in cases when it is not practical to use an additional inductor to compensate for the parasitic shunt capacitance of the crystal. It is shown theoretically that the inclusion of this capacitance in the feedback path reduces the total effective capacitance in the tank circuit, which is tuned to the desired overtone frequency. This creates a second mode of oscillation frequency which is higher than the desired crystal resonance frequency. The ranges of loop-gain and tank resistance values that can prevent this parasitic mode of oscillations are derived. It is also shown that the useful loop gain for the desired oscillations to start is restricted to a similar region by the crystal shunt capacitance and series resistance     

基于OrCAD/PSpice的波形发生电路设计仿真

对正弦波振荡器工作原理及振荡电路的起振条件进行了分析与研究。根据LC三点式振荡电路的组成原则设计并改进了电容三点式振荡器电路,在O rCAD/PSp ice仿真软件中对电路进行了时域及频域仿真分析,给出了振荡波形,测量了振荡频率。仿真结果表明通过对电路的改进改善了波形,所设计电路波形与理论值相接近。     

基于CCII的集成混沌振荡器设计

集成化混沌振荡器是混沌在实际应用中的一种重要趋势,特别是在大规模的混沌系统的电子实现方面。为了使混沌振荡器的集成度更高,并且具有较宽的频带,本文提出了一种新型的电流模式混沌振荡器。通过对自治混沌振荡器的电路模型分析,在文氏混沌电路基础上,采用CCII电路代替电压运算放大器、跨导运算放大器等传统运算放大器,实现了正弦波振荡电路,通过采用NMOS管将两个正弦振荡电路耦合最终实现电流模式混沌振荡器,通过对该电流模式混沌振荡器建模并进行仿真分析,描述了该振荡器的混沌行为,验证了该混沌电路的有效性和可行性。再通过仿真结果对比表明该混沌振荡器相比于传统的文氏混沌振荡器功耗更小、噪声抑制能力更强,由其产生的混沌信号在频带宽度、随机程度方面都有明显提高,更适合芯片集成。     

短波段频率合成器的设计与调试

设计了基于锁相环的短波段正弦信号合成器,其工作原理为原始的正弦波输出信号由压控振荡器产生,经芯片分频输出一个低频方波信号,参考信号采用Q值较高的晶体产生,然后输出到芯片的分频,在芯片内部输出一个低频方波信号,两路低频方波信号同时由芯片内部的数字鉴相器进行比相,输出一个反映相位误差值的双路差分电压信号到有源环路低通滤波器,经它滤波形成近似直流的信号,控制压控振荡器的变容管反相偏置电压来调整振荡频率。仿真结果达到预期要求。     

Design considerations for high-frequency crystal oscillatorsdigitally trimmable to sub-ppm accuracy

The current consumption of crystal oscillators is usually determined by the steady-state amplitude requirement, rather than the minimum transconductance for oscillation to exist, In a bipolar implementation transconductance is proportional to current, so that current consumption scales with frequency and load capacitance in the same way as transconductance. In a complementary metal-oxide-semiconductor (CMOS) implementation, current scales as the square of transconductance. It is therefore important to distinguish current from transconductance in power estimation for high frequency oscillators. Analytical expressions relating current to steady-state amplitude are used in this paper to estimate the minimum power required for a crystal oscillator at a given frequency. A 78 MHz crystal oscillator is described, which forms part of a regulated system in a pager where the oscillation frequency is controlled digitally to sub-ppm accuracy. The oscillator can be pulled from ±65 ppm to the required frequency with 0.2 ppm accuracy, with a maximum current consumption of 197 μA. The circuit has been fabricated in a 1-μm CMOS technology. The measured phase noise is -113 dBc/Hz at 300 Hz offset     

基于orCAD／PSpice的晶体振荡电路设计仿真

通过对电容三点式振荡电路和石英晶体振荡器等效电路的计算分析,设计并改进了石英晶体振荡器电路。在OrCAD／PSpice环境中完成了电路的时域和频域仿真分析,对影响振荡电路起振特性的因素进行了探讨,进一步验证了PSpice电路仿真设计的合理性和可靠性。给出了发生电路的振荡、稳幅波形,测量了振荡周期和振荡频率,并与理论值做出比较。结果表明,设计的振荡电路波形好,振荡频率稳定,易于实现,可广泛应用于工程设计领域。     

A K-band monolithic oscillator integrated with a buffer amplifierusing a device-circuit interaction design concept

We report on a high power, high efficiency, and small-size monolithic coplanar waveguide oscillator incorporating a single-stage buffer amplifier on the same chip. For the oscillator design, by changing RF current level through the device, the optimum load line was chosen in order to have an oscillation frequency insensitive to the effect of the subsequently connected amplifier, based on a device-circuit interaction concept. The amplifier, on the other hand, which was driven directly by the oscillator, was designed to achieve an overall high power and high efficiency operation. At 21 GHz, the output power of the developed chip recorded 17 dBm with an overall DC-RF efficiency of 22%. By changing the length of a source feedback line, the oscillation frequency was varied from 21 GHz to 26 GHz. For all cases, the output power remained higher than 16 dBm     

PLL-based BiCMOS on-chip clock generator for very high-speedmicroprocessor

Described is a phase-locked loop (PLL)-based BiCMOS on-chip clock generator (PCG), which is used to generate an internal clock synchronized to a reference clock from outside the chip. In order to obtain a very wide operation bandwidth, it is proposed that the PCG include a compensation circuit for voltage-controlled oscillator (VCO) operation. The compensation circuit varies the oscillation bandwidth of the VCO according to the reference clock frequency, preventing the expected oscillation frequency from being outside the oscillation bandwidth. The PCG is designed and fabricated with 1.0 μm BiCMOS technology, and it achieves an operation bandwidth of 3 to 90 MHz