一种新颖的LDO线性稳压器

设计了一种新颖的LDO线性稳压器.该LDO工作于负电源,具有微功耗、自身固定-5 V输出、外接反馈电阻可实现可调输出等特点.基于0.6 μm SOI CMOS工艺进行流片.测试结果表明,该电路输入电源电压VIN为-2～-18 V,可调输出电压为-1.3 V～VIN+0.5 V@Iour=15mA.该LDO功耗低,室温下空载静态电流约4.8μA,并且几乎不随VIN变化.内部带隙电压基准采用β二阶补偿,结构简单,温度系数为1.28×10-5/℃.线性调整率为0.015％,负载调整率为0.85 Ω.     

基于概率鲁棒及密勒补偿的LDO设计

基于概率鲁棒理论及密勒补偿架构,通过对内外环路进行稳定性分析获得元件参数,设计了一种输出电压为3.3V、最大输出电流为100mA的低压差线性稳压器。利用Spectre进行了电路仿真,并基于CSMC 0.35μm标准CMOS工艺进行了电路实现。结果表明,在5V的工作电压下,当负载电流跳变时,该低压差线性稳压器的调整时间在6ms内,输出电压变化小于150mV,线性调整率和负载调整率分别为0.16%和0.32%。     

一种高精确度低功耗无片外电容LDO设计

设计了一种片上集成的高精确度、低功耗、无片外电容的低压差线性稳压器(LDO)。采用一种新型高精确度、带隙基准电压源电路降低输出电压温漂系数;采用零功耗启动电路和支路较少的摆率增强模块降低功耗,该电路采用CSMC 0.5 μm CMOS工艺。经过Cadence Spectre仿真验证,输出电压为3.3 V,在3.5~5.5 V范围内变化时,线性调整率小于0.3 mV/V,负载调整率小于0.09 mV/mA,输出电压在-40~+150 ℃范围内温漂系数达10 ppm/℃,整个LDO消耗17.7 μA的电流。     

一种采用新颖的双重自适应补偿的低静态电流LDO稳压器的设计

设计了一种采用双重自适应补偿的两级结构LDO线性稳压器,该补偿技术能够产生两个随负载变化的零点以抵消不同负载条件下的极点变化带来的影响,从而保证系统的稳定性. 与传统的设计方法相比,该补偿方法几乎不消耗电流,文中设计的LDO静态电流小于1μA,并且采用折返式电流限制,减小了芯片的功耗. 采用该双重自适应补偿的LDO已在Hynix 0.5μm CMOS工艺线投片,当负载电流为300mA时,漏失电压为150mV,线性调整率为2mV/V,负载调整率为0.75%.测试结果表明,采用该双重自适应补偿结构的LDO工作良好.     

一种瞬态增强的无片外电容LDO设计

基于SMIC 0.18 um BCD工艺,采用自适应功率管技术和直接电压尖峰检测技术,设计了一种瞬态响应增强的无片外电容低压差线性稳压器。瞬态增强电路采用对称的频率补偿网络提高功率管瞬时摆率,抑制下冲;采用PMOS管组成的电荷泄放通路减小系统瞬时输出阻抗,抑制上冲。仿真结果显示：输入电压为3.5～4.5 V、漏失电压为100 m V时,系统最大输出电流为100 m A;线性调整率为0.04 mV/V,负载调整率为7.33 mV/A。负载电流在0～100 m A@1 us跳变时,上冲、下冲电压小于130 m V,建立时间小于1 us。     

一种低功耗无片外电容LDO的设计

基于SMIC 0.18 μm CMOS工艺,设计了一款输入电压为1.8 V、输出电压为1.6 V的低功耗无片外电容低压差线性稳压器(LDO),其静态电流仅为5 μA。该电路采用一种新型摆率增强电路,通过检测输出电压的变化实现对功率管的瞬态调节。片内采用密勒补偿使主次极点分离,整个系统在负载范围内具有良好的稳定性。仿真结果显示,该LDO在负载电流以99 mA/1 μs跳变时,输出电压下冲为59 mV,上冲为60 mV,响应时间约为1.7 μs。     

一种缓冲器阻抗动态调整的LDO

提出了一种缓冲器阻抗动态调整的LDO结构。采用并联负反馈和阻抗动态调整技术,显著降低了缓冲级的输出阻抗,没有增加额外的静态电流,功率管栅极极点始终远在单位增益带宽之外,对稳定性没有影响。该缓冲级增大了功率管栅极的摆率,提高了LDO瞬态响应性能。基于TSMC 0.18 μm 3.3 V CMOS工艺进行设计,该LDO的输出电压为1.8 V,压差电压为0.2 V,最大输出电流为100 mA。仿真结果显示,LDO的静态电流只有5 μA,当负载电流在10 ns内从0 mA跳变到100 mA时,输出欠冲和过冲电压分别为88.2 mV和34.8 mV。     

一款采用超前相位补偿技术的低压差线性稳压器

设计了一种具有高稳定性、能够驱动较大负载电流的低压差线性稳压器(LDO)电路,输入电压为3.0~6.0 V,输出电压为2.8 V。采用超前相位补偿技术,产生一组零极点对,零点补偿前面环路中的极点,使得LDO电路具有稳定的环路结构,得到稳定的输出电压。基于CSMC 0.25μm EN BCDMOS工艺完成电路和版图的设计。电路仿真结果表明电路的负载调整率为0.03%/A,线性调整率为0.13%/V,最大驱动的负载电流为10 mA。在不同负载条件下,LDO环路的最差相位裕度能够达到64.1°。     

一种低功耗、高稳定性的无片外电容线性稳压器

本文研究并设计了输出电压3.3V,最大输出电流为150mA的CMOS无片外电容的低压差线性稳压器(Off-chipcapacitor-free Low-dropout Voltage Regulator,LDO).该LDO采用了NMC(Nested Miller Compensation)频率补偿技术保证了系统的稳定性.另外,采用大电容环路和SRE(Slew Rate Enhancement)电路抑制输出电压的跳变,改善了瞬态响应.电路采用了低功耗设计技术.采用CSMC 0.5μm CMOS混合信号工艺模型仿真表明:整个LDO的静态电流仅为3.8μA;最差情况下的相位裕度约为88.50;在5V工作电压下,当负载电流在1μs内从150mA下降到1mA时,输出电压变化仅为140mV;在负载电流150mA的情况下,当电源电压在5μs内从3.5V跳变至5V时,输出电压变化也仅为140mV.     

一种基于FVF结构的快瞬态响应LDO设计

提出了一种快瞬态响应、宽输入电压范围、无片外电容的低压差线性稳压器(LDO),应用于给主控(MCU)芯片中的Flash供电。该稳压器基于超级源跟随器结构,由快慢两个通路构成。采用电容耦合方式感知负载变化,进一步增强瞬态响应。电路采用UMC 55 nm工艺设计实现,使用Spectre软件进行了仿真验证。仿真结果表明,当负载电流以10 ps的跳变边沿在0~10 mA范围变化时,输出电压的最大上冲值和下冲值分别为109 mV、153 mV。在输入电压2~3.6 V范围内,线性调整率和负载调整率分别为2.6 mV·V-1和0.5 mV·mA-1。     

一种动态补偿、高稳定性的LDO设计

设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面...     

Current buffer compensation topologies for LDOs with improved transient performance

The goal of internal frequency compensation of a low dropout voltage regulator (LDO) is the selection of a small-value, ESR-independent output capacitor. Cascode compensation formed by a common-gate transistor acting as a current buffer, an optional series resistor, and a compensation capacitor creates a dominant pole and a left-half-plane (LHP) zero, allowing adequate phase margin and stable LDO design. To this end, a 1.21?V output, 100?mA, 0.1?C10???F output capacitor, ESR-independent, low voltage LDO using cascode compensation with replica bias is designed and fabricated in a 0.5???m CMOS process with an area of 0.22?mm². A line regulation of 0.05% V/V, load regulation of 0.001% V/mA and dropout voltage of 220?mV were measured. LDO-specific pole-zero analysis is detailed. In addition to this design, two improved transient response LDO architectures using cascode compensation with split-length transistors are also explored. A Power Good feature is discussed, which enables direct interface between the LDO and a micro-processor.     

一种高稳定性高精度低压差线性稳压器的分析与设计

提出了LDO,其基于缓慢滚降式频率补偿方法,通过在电路中引入三个极零对(极零对的产生没有增加静态功耗),不仅克服了常规LDO不能使用低等效串联电阻、低成本陶瓷输出电容的缺点,而且确保了系统在整个负载和输入电压变化范围内稳定工作.由于LDO通常给高性能模拟电路供电,因此其输出电压精度至关重要;而该补偿方法能满足高环路增益、高单位增益带宽的设计要求,从而大幅提高LDO的精度.该LDO基于0.5μm CMOS工艺实现.后仿结果表明,即使在低压满负载条件下,其开环DC增益仍高于70dB,满载时单位增益带宽可达3MHz,线性调整率和负载调整率分别为27μV/V和3.78μV/mA,过冲和欠冲电压均小于30mV,负载电流为150mA时的漏失电压(dropout电压)仅为120mV.     

An ultra-low power output capacitor-less low-dropout regulator with slew-rate-enhanced circuit

An ultra-low power output-capacitorless low-dropout (LDO) regulator with a slew-rate-enhanced (SRE)circuit is introduced.The increased slew rate is achieved by sensing the transient output voltage of the LDO and then charging (or discharging) the gate capacitor quickly.In addition,a buffer with ultra-low output impedance is presented to improve line and load regulations.This design is fabricated by SMIC 0.18 μm CMOS technology.Experimental results show that,the proposed LDO regulator only consumes an ultra-low quiescent current of 1.2 μA.The output current range is from 10 μA to 200 mA and the corresponding variation of output voltage is less than 40 mV.Moreover,the measured line regulation and load regulation are 15.38 mV/V and 0.4 mV/mA respectively.     

250 mV Supply Voltage Digital Low‐Dropout Regulator Using Fast Current Tracking Scheme

This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current.     

Development of Single-Transistor-Control LDO Based on Flipped Voltage Follower for SoC

The design issues of a single-transistor-control (STC) low-drop-out (LDO) based on flipped voltage follower is discussed in this paper, in particular the feedback stability at different conditions of output capacitors, equivalent series resistances (ESRs) and load current. Based on the analysis, an STC LDO was implemented in a standard 0.35-mum MOS technology. It is proven experimentally that the LDO provides stable voltage regulation at a variety of output-capacitor/ESR conditions and is also stable in no output capacitor condition. The preset output voltage, minimum unregulated input voltage, maximum output current at a dropout voltage of 200 mV, ground current and active chip area are 1 V, 1.2 V, 50 mA, 95 muA, and 140 mum times 320 mum, respectively. The full-load transient response in the no output capacitor case is faster than a micro second and is about 300 ns.     

Enhanced active feedback technique with dynamic compensation for low-dropout voltage regulator

This paper presents a novel frequency compensation technique for a low-dropout (LDO) voltage regulator. Enhanced active feedback frequency compensation is employed to improve the frequency response. The proposed LDO is capable of providing high stability for current loads up to 150 mA with or without loading capacitors. The proposed LDO voltage regulator provides a loop bandwidth of 7.8 MHz under light loads and 6.5 MHz under heavy loads. The maximum undershoot and overshoot are 59 and 90 mV, respectively, for changes in load current within a 200-ns edge time, while the compensation capacitors only require a total value of 7 pF. This enables easy integration of the compensation capacitors within the LDO chip. The proposed LDO regulator was designed using TSMC 0.35-μm CMOS technology. With an active area of 0.14 mm² (including feedback resistors), the quiescent current is only 40 μA. The input voltage ranges from 1.73 to 5 V for a loading current of 150 mA and an output voltage of 1.5 V. The main advantage of this approach is the stability of the LDO circuit when external load capacitors are connected, or even without load capacitors.     

A capacitor-free CMOS LDO regulator with AC-boosting and active-feedback frequency compensation

A capacitor-free CMOS low-dropout(LDO)regulator for system-on-chip(SoC)applications is presented.By adopting AC-boosting and active-feedback frequency compensation(ACB-AFFC),the proposed LDO enhancement circuit is adopted to increase the slew rate and decrease the output voltage dips when the load current is suddenly switched from low to high.The LDO regulator is designed and fabricated in a 0.6/am CMOS process.The active silicon area is only 770×472μm2.Experimental results show that the total error of the output voltage due to line variation is less than ±0.1 97%.The load regulation is only 0.35 mV/mA when the load current changes fromoto 100mA.     

0.13μm BiCMOS低压差线性稳压器

设计了一种0.13μm BiCMOS低压差线性稳压器(LDO),包括BiCMOS误差放大器、带软启动的BiCMOS带隙基准源、"套筒式"共源-共栅补偿电路等。为了改善线性瞬态响应性能,在BiCMOS误差放大器的前级设置了动态电流偏置电路。由于所设计的BiCMOS带隙基准源对温度的敏感性较小,故能为LDO提供高精度的基准电压。对所设计的LDO进行了工艺流片。流片测试结果表明,该LDO可提供60 mA的输出电流且最小压差只有100 mV。测试同时验证了所设计LDO的负载和瞬态响应都得到改善:负载调整率为0.054 mV/mA,线性调整率为0.014%,而芯片面积约为0.094 mm2,因此特别适用于高精度、便携式片上电源系统。