共查询到19条相似文献,搜索用时 125 毫秒
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针对嵌入式处理器中数据Cache功耗显著的特点,提出了一种基于Load重用的低功耗数据Cache设计方法.通过保存Load指令从数据Cache中取回的数据,实现了随后Load指令对该数据的重新使用,从而减少了数据Cache的访问次数,有效降低了数据Cache的功耗.在SuperV_EF01DSP上的实验结果显示,采用该方法后,在处理器性能没有损失的情况下,数据Cache功耗平均降低29.48%,面积仅增加0.64%. 相似文献
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Markus Levy Rob Cosaro 《今日电子》2007,(10):76-77
当设计工程师为低功耗应用选择微控制器时,芯片厂商的数据手册所提供的帮助是有限的.手册不能提供业界标准的功耗评价方法,也不能说明像高速缓存(Cache)和集成浮点运算单元等功能部件是怎样影响能量消耗和性能的. 相似文献
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SOC时代低功耗设计的研究与进展 总被引:11,自引:1,他引:10
在片上系统(SOC)时代,芯片内核的超高功耗密度以及移动应用市场对低功耗的无止境需求,使低功耗设计变得日益重要.文章全面系统地介绍了低功耗设计的相关内容,包括背景、原理和不同层次的功耗优化技术,着重介绍了面向SOC的系统级功耗优化技术.通过对已有研究成果按设计抽象层次和系统功能的分析,指出了其优化的全局性不够充分.提出了基于软硬件协同设计的系统功耗优化思路和设计流程,展望了SOC低功耗设计的发展方向. 相似文献
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在多媒体系统的系统集成芯片(SoC)中,从系统集成芯片工作实时性要求,应用程序和数据尽可能存放在片上存储或Cache,执行方便,处理速度快,就要使用大量的存储部件,使得存储部件的面积和功耗占到整个芯片的很大部分.为了减少片上存储部件,则部分程序和数据移到片外存储,在执行时轮流调进到芯片内,势必增加I/O的开销.因此如何使设计优化是软硬件协同设计中的一个问题.本文以MPEG2集成解码芯片中音频存储优化为例给出了系统集成芯片存储优化的一些方法.包括通过LGDFG(Large Grain Data Flow Graph)模型分析改变程序结构,共享数据空间,改变数据类型以及添加片上SRAM并减少片上Cache容量从而减少系统存储消耗等.这些方法显著地减少系统的存储消耗,降低系统芯片的面积和功耗. 相似文献
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介绍了SOC设计中的IP核可复用技术、软硬件协同设计技术、SOC验证技术、可测性设计技术以及低功耗设计技术。对SOC低功耗设计中的瞬态功耗优化、平均功耗优化以及功耗的物理来源、电容充放电功耗、短路功耗、静电漏电功耗进行了分析。并对典型SOC设计中采取降低芯片和封装电容、降低电源电压,达到降低功耗的技术进行了研究。最后对系统级功耗设计中的电源系统低功耗设计、工作系统低功耗设计进行了探讨。 相似文献
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针对超大规模集成电路低功耗设计技术市场需求的迅速增大,提出了一种新的百万门级系统芯片低功耗设计流程,重点分析了芯片系统级、电路级、逻辑级与物理级四个不同的层次的低功耗设计方法,包括系统构架、时钟与功耗管理算法等低功耗关键技术。以某新型雷达SoC低功耗设计为例,采用SMIC 0.18 μm 1P6M CMOS工艺进行设计,版图尺寸为7.825 mm×7.820 mm,规模约为200万门。实验结果表明,在100 MHz工作频率下,采用新的低功耗设计流程后,前端设计阶段功耗降低了42.79%,后端设计阶段功耗降低了12.77%,芯片总功耗仅为350 mW。样品电路通过了用户某新型相控阵雷达系统的应用验证,满足小型化和低功耗的要求。 相似文献
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高性能DSP器件对功耗指标要求越来越高,功耗主要来源于对存储空间的访问,因此提出了一种改进型Cache功耗优化策略,实现了对指令Cache的分阶段访问,同时兼顾了Cache的动态功耗和静态漏流功耗的优化,改进了传统的基于非分阶段访问的按需唤醒策略NPOWP(Non-Phased Cache with On-Demand Wakeup Prediction)显著影响处理器性能的缺点。设计应用于DSP设计的4路组相连昏睡指令Cache中,使用基于分阶段访问的按需唤醒策略POWP(Phased Cache with On-Demand Wakeup Prediction)策略平均可降低75.4%的指令Cache功耗,降低6.7%的处理器总功耗,性能损失仅为0.77%. 相似文献
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Hui Chen Yang Xiao 《Communications Magazine, IEEE》2006,44(5):113-123
In the last two decades we have witnessed the tremendous success of the Internet and its technologies. Wireless Internet access becomes important to continue this success. However, wireless Internet access suffers from limited battery power, limited bandwidth, high mobility, and an increasing degree of heterogeneity. Cache mechanisms have been proposed to improve access latency, reduce battery power consumption, and reduce bandwidth usage in the wireless Internet. In this article we discuss issues in wireless Internet caching. In particular, we classify and survey cache access mechanisms and replacement algorithms, which should be designed considering both the limitations of wireless networks/devices and heterogeneity of the future wireless Internet. 相似文献
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一种低功耗Cache设计技术的研究 总被引:2,自引:0,他引:2
低功耗、高性能的cache系统设计是嵌入式DSP芯片设计的关键。本文在多媒体处理DSP芯片MD32的设计实践中,提出一种利用读/写缓冲器作为零级cache,减少对数据、指令cache的读/写次数,由于缓冲器读取功耗远远小于片上cache,从而减小cache相关功耗的方法。通过多种多媒体处理测试程序的验证,该技术可减少对指令cache或者数据cache20%~40%的读取次数,以较小芯片面积的增加换取了较大的功耗降低。 相似文献
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Nam Sung Kim Blaauw D. Mudge T. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(10):1147-1156
On-chip L1 and L2 caches represent a sizeable fraction of the total power consumption of microprocessors. In nanometer-scale technology, the subthreshold leakage power is becoming one of the dominant total power consumption components of those caches. In this study, we present optimization techniques to reduce the subthreshold leakage power of on-chip caches assuming that there are multiple threshold voltages, V/sub T/'s, available. First, we show a cache leakage optimization technique that examines the tradeoff between access time and subthreshold leakage power by assigning distinct V/sub T/'s to each of the four main cache components-address bus drivers, data bus drivers, decoders, and static random access memory (SRAM) cell arrays with sense amplifiers. Second, we show optimization techniques to reduce the leakage power of L1 and L2 on-chip caches without affecting the average memory access time. The key results are: 1) two additional high V/sub T/'s are enough to minimize leakage in a single cache-3 V/sub T/'s if we include a nominal low V/sub T/ for microprocessor core logic; 2) if L1 size is fixed, increasing L2 size can result in much lower leakage without reducing average memory access time; 3) if L2 size is fixed, reducing L1 size may result in lower leakage without loss of the average memory access time for the SPEC2K benchmarks; and 4) smaller L1 and larger L2 caches than are typical in today's processors result in significant leakage and dynamic power reduction without affecting the average memory access time. 相似文献
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The development of proxy caching is essential in the area of video‐on‐demand (VoD) to meet users' expectations. VoD requires high bandwidth and creates high traffic due to the nature of media. Many researchers have developed proxy caching models to reduce bandwidth consumption and traffic. Proxy caching keeps part of a media object to meet the viewing expectations of users without delay and provides interactive playback. If the caching is done continuously, the entire cache space will be exhausted at one stage. Hence, the proxy server must apply cache replacement policies to replace existing objects and allocate the cache space for the incoming objects. Researchers have developed many cache replacement policies by considering several parameters, such as recency, access frequency, cost of retrieval, and size of the object. In this paper, the Weighted‐Rank Cache replacement Policy (WRCP) is proposed. This policy uses such parameters as access frequency, aging, and mean access gap ratio and such functions as size and cost of retrieval. The WRCP applies our previously developed proxy caching model, Hot‐Point Proxy, at four levels of replacement, depending on the cache requirement. Simulation results show that the WRCP outperforms our earlier model, the Dual Cache Replacement Policy. 相似文献
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Cache performance tuning tools are conducive to develop program with good locality and fully use cache to decrease the influence caused by speed gap between processor and memory. This paper introduces the design and implementation of a cache performance tuning tool named CTuning, which employs a source level instrumentation method to gather program data access information, and uses a limited reuse distance model to analyze cache behavior. Experiments on 183.equake improve average performance more than 6% an... 相似文献
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Motomura M. Inoue T. Yamada H. Konagaya A. 《Solid-State Circuits, IEEE Journal of》1995,30(4):375-382
This paper presents a new data cache design, cache-processor coupling, which tightly binds an on-chip data cache with a microprocessor. Parallel architectures and high-speed circuit techniques are developed for speeding address handling process associated with accessing the data cache. The address handling time has been reduced by 51% by these architectures and circuit techniques. On the other hand, newly proposed instructions increase data cache bandwidth by eight times. Excessive power consumption due to the wide-bandwidth data transfer is carefully avoided by newly developed circuit techniques, which reduce dissipation power per bit to 1/26. Simulation study of the proposed architecture and circuit techniques yields a 1.8 ns delay each for address handling, cache access, and register access for a 16 kilobyte direct mapped cache with a 0.4 μm CMOS design rule 相似文献