共查询到20条相似文献,搜索用时 31 毫秒
1.
《Solid-State Circuits, IEEE Journal of》1978,13(3):345-351
A new 5-transistor memory cell in double polysilicon technology with depletion-load elements and a minimum linewidth of 3 /spl mu/m is presented. The circuit configuration, based on a Schmitt trigger, leads to static memory cells having a bit density of 1100 bit/mm/SUP 2/ and an average power consumption of 5.5 /spl mu/W/cell. With the help of computer simulations the static and dynamic behavior of the basic circuit are calculated and discussed in detail as well as the two possible operation modes of the memory cell. These results compare favorably with the experimental results obtained on a realized 2/spl times/4 memory array. The performance of the proposed memory cell is the same as that of a conventional 6-transistor cell, but the area is reduced. 相似文献
2.
《Electron Devices, IEEE Transactions on》1982,29(3):368-376
A new one-transistor, one-capacitor RAM cell structure called a Quadruply Self-Aligned Stacked High Capacitance (QSA SHC) RAM is proposed as a basic cell for a future one-million-bit VLSI memory. This cell consists of a QSA MOSFET and a Ta2 O5 capacitor stacked on it. By this cell, the ultimate cell area3F times 2F can be realized with sufficient operating margin. Here,F is the minimum feature size. The basic cell was fabricated and its operation was experimentally verified. The leakage current of Ta2 O5 film was small enough for the storage capacitor dielectric. Using a3F times 4F cell and a4F pitch sense amplifier, a one-million-bit memory was designed with a 2-µm rule. A cell size of 6.5 × 8 µm2, and a chip size of 9.2 × 9.5 mm2were obtained. The access time, neglecting the RC time constant of the word line, was estimated to be about 170 ns. Based on this design, it is argued that a future one-million-bit memory can be realized by QSA SHC technology with a 2-1-µm process. The mask set of the 1-Mbit RAM was actually fabricated by an electron-beam mask maker. A photomicrograph of the 1-Mbit RAM chip patterned by the mask set is shown. This chip was patterned not to get an operating sample but to show an actual chip image of the future 1- Mbit RAM. The area of each circuit block including storage array can be seen in this chip image. 相似文献
3.
A neural-network-based approach to synthesising F0 information for Mandarin text-to-speech is discussed. The basic idea is to use neural networks to model the relationship between linguistic features. Extracted from input text and parameters representing the pitch contour of syllables. Two MLPs are used to separately synthesise the mean and shape of pitch contour, using different linguistic features. A large set of utterances is employed to train these MLPs using the well known back-propagation algorithm. Pronunciation rules for generating F0 information are automatically learned and implicitly memorised by the MLPs. In the synthesis, parameters representing the mean and shape of the pitch contour of each syllable are generated using linguistic features extracted from the given input text. Simulation results confirmed that this is a promising approach for F0 synthesis. The resulting synthesised pitch contours of syllables match well with their original counterparts. Average root mean square errors of 0.94 ms/frame and 1.00 ms/frame were achieved 相似文献
4.
《Solid-State Circuits, IEEE Journal of》1980,15(5):854-861
A 64 kbit fully static MOS RAM which contains about 402500 elements on the chip area of 5.44/spl times/5.80 mm has been designed. The memory cell is a basic cross-coupled flip-flop with four n-MOSFETs and two polysilicon load resistors. The memory cell size is decreased to 16/spl times/19 /spl mu/m (304 /spl mu/m/SUP 2/) by using advanced n-MOS technology with double-level polysilicon films and photolithography of 2 /spl mu/m dimensions. By applying n-well CMOS technology fabricated on a high-resistivity p-type silicon substrate to peripheral circuits of the RAM, high performance characteristics with high speed access times and low power dissipation are obtained. The RAM is designed for single 5 V operation. Address and chip select access times are typically 80 ns. Power dissipation in the active and standby mode is typically 300 and 75 mW, respectively. 相似文献
5.
Horiguchi M. Aoki M. Nakagome Y. Ikenaga S. Shimohigashi K. 《Solid-State Circuits, IEEE Journal of》1988,23(1):27-33
A 4-bit semiconductor file memory using 16-levels (4-bits)/cell storage is described. The device has 1-Mb single-transistor dynamic memory cells which are divided into 4-kb sequential-access blocks. It incorporates a staircase-pulse generator for multilevel storage operations, a voltage regulator to protect against power-supply voltage surge, and a soft-error-correction circuit based on a cyclic hexadecimal code. The device is fabricated using 1.3-μm CMOS technology. It operates with a 5-V single power supply. Random block selection time is 147 μs, while the sequential data rate is 210 ns. A single-incident alpha particle destroys 4-bit data in two or more adjacent cells. The error correction circuit completely corrects these errors. The soft-error rate under actual operating conditions with error correction is expected to be under 100 FIT (10-7 h-1) 相似文献
6.
基于0.18-μm 1.8 V CMOS标准工艺,设计了一个高精度开关电流存储单元.通过设置存储晶体管工作于线性区,并结合虚拟开关等技术,降低了由阈值电压失配和时钟馈通所产生的谐波失真,有效消除了增益误差和漂移误差.利用Spectre仿真器,对版图进行后仿真验证.当输入信号频率为200 kHz、幅度为5μA、采样频率为5 MHz时,误差仅为0.5%,输入信号幅度低至1μA时,误差依然低于1%.仿真结果表明,电路具有高精度,可作为滤波器、∑-△调制器等系统的基本模块. 相似文献
7.
We discuss circuit parameters that limit the precision of basic dynamic current-memory cells. In addition to analyzing current-copying errors caused by the finite output conductances of the current sources and by the clock-feedthrough (CFT) of the feedback switches, we analyze the noise performance of the basic memory cell. To reduce CFT and noise, we propose a novel circuit based on Miller capacitance-enhancement. Measurement results of memory cells integrated in a 1-μm CMOS process confirm the theoretical findings; with our CFT and noise reduction technique based on Miller enhanced capacitance and dummy switches, we achieve a dynamic range of 11 b at clock frequencies greater than 100 kHz 相似文献
8.
《Electron Devices, IEEE Transactions on》1987,34(6):1368-1372
A new VLSI memory cell is proposed that offers high immunity to alpha-particle-induced soft errors and a cell area comparable to a one-transistor memory cell. This memory cell consists of a pair of complementary MOSFET's and one capacitor. The PMOSFET is formed in an SOI film over the NMOSFET. Since both storage capacitor nodes are kept electrically floating in retention periods and one storage capacitor node is formed in a thin SOI film, an alpha-particle hit does not destroy the stored charge of this memory cell. It is sufficient for an SOI-PMOSFET to provide only three orders of magnitude ON/OFF current ratio. Experimental memory cells were fabricated using polysilicon film as an SOI film. Measuring them confirmed the main effectiveness of this memory cell. 相似文献
9.
Improving the Reliability of MLC NAND Flash Memories Through Adaptive Data Refresh and Error Control Coding 总被引:1,自引:0,他引:1
Chengen Yang Hsing-Min Chen Trevor N. Mudge Chaitali Chakrabarti 《Journal of Signal Processing Systems》2014,76(3):225-234
NAND Flash memory has become the most widely used non-volatile memory technology. We focus on multi-level cell (MLC) NAND Flash memories because they have high storage density. Unfortunately MLC NAND Flash memory also has reliability problems due to narrower threshold voltage gap between logical states. Errors in these memories can be classified into data retention (DR) errors and program interference (PI) errors. DR errors are dominant if the data storage time is longer than 1 day and these errors can be reduced by refreshing the data. PI errors are dominant if the data storage time is less than 1 day and these errors can be handled by error control coding (ECC). In this paper we propose a combination of data refresh policies and low cost ECC schemes that are cognizant of application characteristics to address the errors in MLC NAND Flash memories. First, we use Gray code based encoding to reduce the error rates in the four subpages (MSB-even, LSB-even, MSB-odd, LSB-odd) of a 2-bit MLC NAND Flash memory. Next, we apply data refresh techniques where the refresh interval is a function of the program/erase (P/E) frequency of the application. We show that an appropriate choice of refresh interval and BCH based ECC scheme can minimize memory energy while satisfying the reliability constraint. 相似文献
10.
de la Rosa J.M. Perez-Verdu B. del Rio R. Rodriguez-Vazquez A. 《Solid-State Circuits, IEEE Journal of》2000,35(8):1220-1226
This paper presents a CMOS 0.8-μm switched-current (SI) fourth-order bandpass ΣΔ modulator (BP-ΣΔM) IC capable of handling signals up to 1.63 MHz with 105-bit resolution and 60-mW power consumption from a 5-V supply voltage. This modulator Is intended for direct A/D conversion of narrow-band signals within the commercial AM band, from 530 kHz to 1.6 MHz. Its architecture is obtained by applying a low-pass-to-bandpass transformation (z-1 →-z-2) to a 1-bit second-order low-pass ΣΔ modulator (LP-ΣΔM). The design of basic building blocks is based upon a detailed analysis of the influence of SI errors on the modulator performance, followed by design optimization. Memory-cell errors have been identified as the dominant ones. In order to attenuate these errors, fully differential regulated-folded cascode memory cells are employed. Measurements show a best SNR peak of 65 dB for signals of 10-kHz bandwidth and an intermediate frequency (IF) of 1.63 MHz. A correct noise-shaping filtering is achieved with a sampling frequency of up to 16 MHz 相似文献
11.
《IEEE transactions on information theory / Professional Technical Group on Information Theory》2009,55(6):2659-2673
12.
Nozoe A. Kotani H. Tsujikawa T. Yoshida K. Furusawa K. Kato M. Nishimoto T. Kume H. Kurata H. Miyamoto N. Kubono S. Kanamitsu M. Koda K. Nakayama T. Kouro Y. Hosogane A. Ajika N. Koyashi K. 《Solid-State Circuits, IEEE Journal of》1999,34(11):1544-1550
A 256-Mb flash memory is fabricated with a 0.25-μm AND-type memory cell and 2-bit/cell multilevel technique on a 138.6-mm2 die. Parallel decoding of four memory threshold voltage levels to 2-bit logical values prevents throughput degradation due to multilevel operation. This parallel decoding has been achieved by sense latches and data latches connected to each bitline. Tight distribution of memory cell threshold voltage is essential to reliable multilevel operation. This chip has several measures to deal with the factors that widen the memory cell Vth. The effect of adjacent memory cell's Vth is eliminated by using an AND-type flash memory cell. An initial distribution width of 0.1 V is achieved. The wordline voltage, which has negative temperature dependency, compensates the positive dependency of memory cell Vth. In the -5-75°C range, memory threshold Vth deviation is reduced from the conventional 0.19-0.07 V. Conventionally, the number of programs without erase operation per one sector is limited by the limitations from program disturb. This chip introduced a new rewrite scheme, and this limit is increased from the conventional 10-2048+64 times/sector 相似文献
13.
Some unsafe languages, like C and C+ + , let programmers maximize performance but are vulnerable to memory errors which can lead to program crashes and unpredictable behavior. Aiming to solve the problem, traditional memory allocating strategy is improved and a new probabilistic memory allocation technology is presented. By combining random memory allocating algorithm and virtual memory, memory errors are avoided in all probability during software executing. By replacing default memory allocator to manage allocation of heap memory, buffer overflows and dangling pointers are prevented. Experiments show it is better than Die-hard of the following aspects: memory errors prevention, performance in memory allocation set and ability of controlling working set. So probabilistic memory allocation is a valid memory errors prevention technology and it can tolerate memory errors and provide probabilistic memory safety effectively. 相似文献
14.
《Microwave and Wireless Components Letters, IEEE》2009,19(12):801-803
15.
Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed 总被引:1,自引:0,他引:1
16.
《Solid-State Circuits, IEEE Journal of》1976,11(5):591-596
This paper describes a new random-access memory which achieves a bit density comparable to CCD memories. This memory uses as storage elements single-transistor memory cells which are connected to a common bit line. The bit line is implemented with an MOS transmission line, which makes possible an almost lossless charge transport from the single-transistor memory cell to the read/write amplifier. Due to the almost lossless charge transport, the storage capacitance can be reduced and the bit density increased. The expected performance of a 32-kbit memory has been derived. 相似文献
17.
18.
《Solid-State Circuits, IEEE Journal of》1980,15(2):201-205
A 2K/spl times/8-bit static MOS RAM with a new memory cell structure has been developed. The memory cell consists of six devices including four MOSFETs and two memory load resistors. Two load resistors are fabricated in the second-level polysilicon films over the polysilicon gate MOSFET used as the driver. Thus the memory cell area is determined only by the area of four MOSFETs. By applying the new cell structure and photolithography technology of 3 /spl mu/m dimensions, the cell area of 23/spl times/27 /spl mu/m and the chip area of 3.75/spl times/4.19 mm have been realized. The RAM is nonclocked and single 5 V operation. Access time of about 150 ns is obtained at a supply current of 120 mA. 相似文献
19.
《Solid-State Circuits, IEEE Journal of》1973,8(5):319-323
For a comparison of different single-transistor cell designs and sense/refresh amplifier designs figures of merit are derived from the quasi-static behavior of the memory circuit during sensing. The principles of the different cell designs are discussed. A cell with the most favorable design has been realized with a standard n silicon-gate process sequence and contact photolithography. It uses aluminum word lines of 5 /spl mu/m width and separation, a contact hole with a size of 4 /spl mu/m to 6 /spl mu/m, and diffused bit lines with a width of 4 /spl mu/m. For the 1-mil/SUP 2/ memory cell a sense/refresh amplifier based on the gated flip-flop principle has been realized. The sensitivity of this amplifier, which is determined by the integrated circuit element tolerances is estimated and measured. 相似文献
20.
A new dynamic RAM (DRAM) signal sensing principle, a divided/shared bit-line (DSB) sensing scheme, is proposed. This sensing scheme provides folded bit-line sensing operation in a crosspoint-type memory cell array. The DSB scheme offers a high-density DRAM memory core with the common-mode array noise eliminated. A bit-line architecture based on this new sensing principle and its operation are demonstrated. A divided/pausing bit-line sensing (DIPS) scheme, which is an application of this DSB principle to the conventional folded bit-line type of memory cell arrangement, is also proposed. The DIPS architecture achieves complete pausing states for alternate bit lines throughout the active period. These alternate pausing bit lines shield the inter-bit-line coupling noise between active bit lines. Here the inter-bit-line coupling noise is eliminated by a slight architectural change to the conventional folded bit-line memory cell array. These new memory core design alternatives provide high-density DRAM memory cores suitable for the 64-Mb level and beyond. with the memory array noise reduced significantly 相似文献