Digital implementation of the Q-C method for MOS measurements

Computer controlled hardware and software needed for digital implementation of the Q-C method are described. Incorporation of a program that generates ideal data permits debugging and complete verification of the analysis routines. An error sensitivity check shows the parameters that must be measured most carefully are the device area, oxide capacitance, and the voltage independent capacitance in series with the MOS capacitor. The digital technique was found to provide advantages in convenience, speed, accuracy and versatility when implementing the Q-C method.     

Design and implementation of a new four-quadrant MOS analog multiplier

A four-quadrant MOS analog multiplier is proposed using the quarter-square technique, which is based on the quadratic characteristics of an MOS transistor operating in the saturation region and the difference operation of four identical sourced-coupled differential amplifiers. The multiplier has a simple configuration and a large dynamic range over a wide frequency range, since each input signal passes only one transistor to reach the output. The operation of the multiplier was analyzed in detail, and the second-order effects were also analyzed. The proposed circuit was fabricated in 12-V p-well CMOS process with a 5-m minimum feature. The measured results show that linearity error is less than 1% for 5-V_p-p input at ±5 V supply voltage, and the-3 db bandwidth is 30 MHz.     

Improved MOS capacitor measurements using the Q-C method

We describe a method for determining band bending vs gate bias, doping profile and oxide charge density by simultaneous measurement of charge and high frequency MOS capacitance as a function of applied voltage. This charge-capacitance or Q-C method is compared with the usual MOS measurements for the same properties. We find the Q-C method is more accurate and more routine than methods presently in use.In addition, accurate and systematic procedures are introduced for (1) finding the additive constant in the band bending vs gate bias relation, (2) eliminating interface trap error in the doping profile, (3) extrapolation of the doping profile to the interface in the region inaccessible to measurement, (4) correction of oxide charge and work-function determination for interface trap errors and effects of nonuniform doping profiles.     

Low-voltage MOS linear transconductor/squarer and four-quadrant multiplier for analog VLSI

Analog computations such as four-quadrant multiplication, linear voltage-to-current conversion and sum-square or difference-square are fundamental for many analog signal processing systems. All these functions can be realized based on the principle of the linearized differential pair using floating-voltage sources. This paper describes an improved practical realization of this principle, which is particularly suited to analog VLSI computational systems. The proposed class-AB analog cells are very compact, exhibit low total harmonic distortion and low nonlinearity, have a wide bandwidth, and are compatible with low-power and low-voltage operation. A mathematical discussion on stability and harmonic distortion of the proposed realization is presented. Both simulated results and measurements from fabricated cell samples in a 0.8-/spl mu/m CMOS process are given. The described circuits operate from a single 2-V power supply.     

Features and Prototypes of HTS High Q Resonant Circuit

High Tc superconductor (HTS) technology has been used to develop a unique high Q resonant circuit. Such circuit or device has some special characteristics such as very high voltage generation. Theoretical study and experimental approaches have proceeded for the concept verification. This paper presents the theory about this high Q resonant circuit. The operation principle of the circuit is described. A practical prototype for HTS high voltage generation is also demonstrated. The experiment result shows that very high voltages can be achieved by the developed method using HTS technology.     

Potential of MOS technologies for analog integrated circuits

Reviews the rapid progress in MOS analog circuit techniques over the past three years, and attempts to estimate the near-term attainable characteristics of MOS LSI circuits which incorporate both analog and digital functions.     

Nonlinear HEMT model formulated from the second-order derivative of the I-V and Q-V characteristics

In this paper, an empirical nonlinear model of high electron mobility transistors (HEMTs) suitable for a wide bias range is presented. Unlike the conventional large-signal models whose fitting parameters are coupled to the measured drain current and gate capacitance characteristics, the derived modeling equations are direct formulated from the second-order derivative of drain current (I-V) and gate charge (Q-V) with respect to gate voltage. As a consequence, the proposed nonlinear model is kept continuously differentiable and accurate enough to the higher-order I-V and Q-V derivatives. Besides, the thermal and trapping effects have been implemented in the large-signal model along with its dependence on temperature and quiescent-bias state. The composite nonlinear model is shown to accurately predict the S-parameters, large-signal power performances as well as the two-tone intermodulation distortion products for various types of GaAs and GaN HEMTs.     

A novel two-dimensional MOS transistor for analog applications

In analog MOS integrated circuits, matching between transistors is a critical requirement because the circuit performance is determined by the device matching available. A new type of matched configuration is presented in this paper which utilizes the inherent 2-D geometry of an MOS transistor which was hitherto unexplored. This has been achieved by adding two more diffusion regions along the length of a normal MOS transistor. The characteristics of the device thus formed have been modeled in the linear region for different configurations, by solving the 2-D current continuity equation. For the saturation region, an empirical relation has been given. Theoretical and experimental results for a test chip have been presented. A few potential applications are mentioned.     

Statistical modeling of device mismatch for analog MOS integratedcircuits

A generalized parameter-level statistical model, called statistical MOS (SMOS), capable of generating statistically significant model decks from intra- and inter-die parameter statistics is described. Calculated model decks preserve the inherent correlations between model parameters while accounting for the dependence of parameter variance on device separation distance and device area. Using a Monte Carlo approach to parameter sampling, circuit output means and standard deviations can be simulated. Incorporated in a CAD environment, these modeling algorithms will provide the analog circuit designer with a method to determine the effect of both circuit layout and device sizing on circuit output variance. Test chips have been fabricated from two different fabrication processes to extract statistical information required by the model. Experimental and simulation results for two analog subcircuits are compared to verify the statistical modeling algorithms     

Comparing the ocean color measurements between MOS and SeaWiFS: avicarious intercalibration approach for MOS

The Modular Optoelectronic Scanner (MOS) was launched in the spring of 1996 on the Indian IRS-P3 satellite. With the successful launch of NASA's Sea-viewing Wide Field of-view Sensor (SeaWiFS) in the summer of 1997, there are now two ocean color missions in concurrent operation, and there is interest to compare data from these two sensors. In this paper, we describe our efforts to retrieve ocean-optical properties from both SeaWiFS and MOS using consistent methods. We first briefly review the atmospheric correction, which removes more than 90% of the observed radiances in the visible, and then we describe how the atmospheric-correction algorithm used for the SeaWiFS data can be modified for application to other ocean color sensors. Next, since the retrieved water-leaving radiances in the visible between MOS and SeaWiFS are significantly different, we developed a vicarious intercalibration method to recalibrate the MOS spectral bands based on the optical properties of the ocean and atmosphere derived from the coincident SeaWiFS measurements. Furthermore, because of the strange calibration behavior of the MOS 750 nm band, we modified the atmospheric correction such that the MOS 685 and 868 nm bands can also be used. We present and discuss the MOS-retrieved, ocean-optical properties before and after the vicarious calibration using both the MOS 685 and 750 nm coupled with 868 nm bands in comparison with results from SeaWiFS and demonstrate the efficacy of this approach. We show that it is possible and efficient to vicariously intercalibrate sensors between one and another     

An MOS digitally controlled analog attenuator for voiceband signals

Describes the design of an analog attenuator integrated circuit having loss settings that can be determined by remote digital control. The circuit uses a weighted MOS capacitor array to effect losses of 0-16.5 dB in steps of 0.1 dB. Each loss setting is accurate to /spl plusmn/0.02 dB. Two approaches to the circuit realization are described: a CMOS version that includes a digital memory to permit retention of loss settings for a few hours, thereby bridging brief power failures, and a more compact NMOS version that contains all the analog components on a single chip.     

Subthreshold analysis of an MOS analog switch

Charge injection error in the presence of subthreshold effects has been analyzed. It is confirmed that the subthreshold effect is significant at low voltage falling rates. A simplified model is derived using an appropriate approximation. Predictions are compared to the results of a SPICE simulation, a nonquasi-static (NQS) model simulation and experimental results. Excellent agreement between the modified and NQS model and recently published experimental results was obtained. This analytical model is computationally efficient compared to the SPICE and NQS models and provides physical insight into the switching errors     

Characterisation and modeling of mismatch in MOS transistors for precision analog design

A characterization methodology is presented that accurately predicts the mismatch in drain current over a wide operating range using a minimum set of measured data. The physical causes of mismatch are discussed in detail for both p- and n-channel devices. Statistical methods are used to develop analytical models that relate the mismatch to the device dimensions. It is shown that these models are valid for small-geometry devices only. Extensive experimental data from a 3-/spl mu/m CMOS process are used to verify the models. The application of the transistor matching studies to the design of a high-performance digital-to-analog converter (DAC) is discussed. A circuit design methodology is presented that highlights the close interaction between the circuit yield and the matching accuracy of devices. It has been possible to achieve a circuit yield of greater than 97% as a result of the knowledge generated regarding the matching behavior of transistors and due to the systematic design approach.     

Observation and characterization of near-interface oxide traps in 3C-SiC MOS structures by quasi-static I-V method

The electrical properties of oxides grown on 3C-SiC by rapid thermal processing in various oxidizing and annealing atmospheres are investigated using a quasi-static method. According to the anomalous capacitance hump, the existence of two types of traps, interface and near interface oxide traps, is observed in quasi-static. By monitoring the sweep-rate measurement of the quasi-static current related to electron tunneling from interface traps to near-interface oxide traps, a profile of the traps in response time can be obtained. Based on the extracted parameters of the carrier traps, we demonstrate that the near SiO₂/3C-SiC interface is significantly improved when using 100% N₂O compared to 100% O₂ or even N₂-O₂ dilution as oxidizing gas. Also, we show that incorporating N₂ during the oxidation in O₂ is not favourable for the reduction of the near-interface oxide traps.     

The MOS implementation of low-speed modems

This paper identifies the improvements due to large-scale integration [LSI] in the areas of cost, performance, size, reliability, and testing of data communication equipments. An example using Motorola's MC6860 Digital Modem is given. Techniques for implementing linear functions using digital designs and processing methods are discussed along with future technology trends and projections.     

A quick method for the determination of bulk generation lifetime in semiconductors from pulsed MOS capacitance measurements

The high frequency capacitance transient that is observed when an MOS (Metal-Oxide-Semiconductor) capacitor is pulsed from accumulation to deep depletion condition is usually analysed graphically to determine the values of bulk generation rates or of minority carrier lifetimes in the semiconductor concerned. However, this analytical process is a long and laborious one and in this paper a quicker method for the determination of lifetime is suggested. The extracted lifetime value is typically within 10% of the true value and is sufficient for applications such as on-line process control.     

Current-mode subthreshold MOS implementation of the Herault-Juttenautoadaptive network

The authors explore translinear circuits in subthreshold MOS technology and current-mode design techniques for the implementation of neuromorphic analog network processing. The architecture, also known as the Herault-Jutten network, performs an independent component analysis and is essentially a continuous-time recursive linear adaptive filter. Analog I/O interface, weight coefficients, and adaptation blocks are all integrated on the chip. A small network with six neurons and 30 synapses was fabricated in a 2-μm double-polysilicon, double-metal n-well CMOS process. Circuit designs at the transistor level yield area-efficient implementations for neurons, synapses, and the adaptation blocks. The authors discuss the design methodology and constraints as well as test results from the fabricated chips     

Correlation-based associative memory and its MOS implementation

We propose an associative memory based on minimization of a free-energy function determined by the library vectors to be stored. When the library vectors are bipolar, the energy function contains minima at the library vector location. The minima can be sought by search techniques such as gradient descent. Significantly, if the correlation nonlinearity is chosen to be sufficiently strong, then convergence occurs in a single step. We demonstrate how the algorithm can be implemented using MOS circuitry.     

Measurement and analysis of charge injection in MOS analog switches

The analysis has been extended to the general case including signal-source resistance and capacitance. Universal plots of percentage channel charge injected are presented. Normalized variables are used to facilitate usage of the plots. The effects of gate voltage falling rate, signal-source level, substrate doping, substrate bias, switch dimensions, as well as the source and holding capacitances are included in the plots. A small-geometry switch, slow switching rate, and small source resistance can reduce the charge injection effect. On-chip test circuitry with a unity-gain operational amplifier, which reduces the disturbance imposed by measurement equipment to a minimum, is found to be an excellent monitor of the switch charge injection. The theoretical results agree with the experimental data.     

Model for 1/f; noise in MOS transistors biased in the linear region

1/f; Noise calculations and experiments are presented for conductance fluctuations in inversion layers. The layers are biased in the ohmic region at very low drain-source voltages. The model makes use of an experimental fact that competing scattering mechanisms other than lattice scattering lead to a reduction of 1/f; noise, but does not consider trapping of charge carriers in surface states as the source of 1/f; noise. The free charge carrier distribution and a mobility profile play an important part in the model. The model describes the measured results well. A reduction of the effective mobility with increasing gate voltage is accompanied by a strong reduction of the noise.