Silicon p−n insulator-metal (p-n-I-M) devices

Silicon p-n-I-M devices with thin insulating layers ($\text{thicknesses}\text{? 30}\text{A}\text{?}$), named MTIS devices, have been developed. The two terminal device shows an S-shaped negative resistance characteristics similar to a Schockley diode (or p-n-p-n diode). Typically the threshold and sustaining voltages are 10 ～ 15 and 1.3 ～ 2 volts, respectively. The former however can be controlled by optical illumination. Turn-on time including delay is less than 2 nsec and turn-off time ? 1 nsec or less. A thyristor-like device with its third terminal connected to the n-layer shows switching operation controllable by this terminal. A monolithic linear array of p-n-I-M diodes with 30 μm spacing operates as a shift register through coupling of adjacent diodes. Life of the two terminal devices recorded at present is over 1.5 × 10⁴ hr. These devices can be applied to low power and high-speed electrical switching and also to optical switching and integrated logic circuits.     

A dynamic model of the p-n-n+ step recovery diodes for the numerical analysis of pulse circuits

A new p-n-n⁺ diode model for circuit transient analysis is developed. In contrast to existing circuit models, this model reflects all step-recovery diode (SRD) effects during switching on and off, including “ramp” of slow recovery phase. It is accomplished by taking into account the dynamic physical phenomena in the p-n-n⁺ diodes when switched. A non-linear dynamic diffusion capacitance of the diode model is determined by the dependence of the instantaneous base charge on the instantaneous diode voltage.The accuracy of the presented model is verified by comparison of the calculated and measured wave forms of some pulse circuits.The present model has been proved to be more accurate than SRD models previously published.     

Potential and limitations of Schottky-barrier barritt devices

Computer simulation of various Schottky-barrier structures is carried out to investigate the large-signal properties of these devices. Comparison between Schottky-barrier devices and their p-n junction counterparts are also made to evaluate the potential and limitations of these devices and to explain the difference in performance between them. It is shown that among various Schottky-barrier structures, the M-n-i-p⁺ structure is the most powerful one and the M-n-p-p⁺ device is the most efficient one. Furthermore, Schottky-barrier devices with low barrier heights for minority carriers (less than 0.2 eV) are capable of producing power levels close to the generated power of p-n junction devices. Investigation of the temperature dependence of the large-signal performance of these devices shows that Schottky barriers are more sensitive and exhibit their optimum performance close to room temperature value. At low temperature, the output power is limited by the low minority carrier injection, whereas at high temperature the limitation is due to the velocity-modulation losses in the injection and low-field regions of the device.     

Depletion layer formation,space-charge injection and current-voltage characteristics for the silicon p-n-p (n-p-n) structure

Depletion layer formation and current-voltage characteristics are described for the general semiconductor p-n-p (n-p-n) structure in which the impurity or defect centre is able to communicate with both sets of transport levels. All possibilities for current lie within the region bounded on one side by the essentially vertical Shockley-Prim punch-through characteristic and on the other side by the square-law Mott-Gurney space-charge-limited characteristic. If the impurity levels lie near the mid-gap position a variety of characteristics within this region can be expected. Representative current-voltage characteristics have been computed and are described for a typical silicon structure.     

Degradation mechanism for silicon p+-n junctions under forward bias

Leakage current degradation has been observed during forward bias stressing of silicon integrated p⁺-n junctions. Detailed characterization results of the anomalous leakage behavior are discussed in this paper. From these results an electric field-enhanced impurity diffusion mechanism has been proposed to explain both the strong temperature and forward bias dependencies on leakage current time-to-saturation. An activation energy has been determined for this mechanism (0.48±0.04 eV) and is in good agreement with that previously determined for diffusion of interstitial copper in p-type silicon. Subsequent Secondary Ion Mass Spectrometer elemental analysis has confirmed the presence of copper near the surface of the epitaxial layer containing the p⁺-n device.     

Spectral response of an injection-mode infrared detector

Large injection pulses are observed in simple circuits containing forward-biased silicon p-i-n (p⁺-n-n⁺) structures at liquid helium temperatures. The pulse rate is dependent on the intensity of infrared radiation incident on the device. The substantial voltage, current, and power output eliminates the need for on-chip or off-chip amplifiers. The first observation of the spectral response of such a detector as measured from 22 to 32 μm with a liquid-helium-cooled monochromator is reported. The response is similar to other extrinsic detectors and modulated by a multiple internal reflection interference pattern. The interference pattern and the origin of optical absorption are analyzed.     

A computer-aided analysis of one-dimensional thermal transients in n-p-n power transistors

An algorithm is presented which permits the one-dimensional simulation of thermal transients in n-p-n transistors. Band distortion effects, temperature dependent mobilities and thermal conductivity are incorporated into the model. Accurate expressions are derived for the heat generated at any point within the semiconductor and the finite difference forms of the current continuity equations. Results showing the internal device behaviour under various bias conditions are presented.     

A computer-aided simulation model for the I–V characteristic of M-n-p silicon Schottky-barrier diodes produced by use of low-energy arsenic-ion implantation

Current-transport properties of Al-n-p silicon Schottky-barrier diodes have been studied both experimentally and theoretically. An analytical model for the I-V characteristic of a metal-n-p Schottky barrier diode has been developed by using an interfacial layer-thermionic-diffusion model. Assuming a Gaussian distribution for the implanted profile, the barrier-height enhancement and ideality factor have been derived analytically. Using low energy (25 KeV) arsenic implantation with the dose ranged form 8 × 10¹⁰/cm² to 10¹²/cm², Al-n-p silicon Schottky barrier diodes have been fabricated and characterized. Comparisons between the experimental measurements and the results of computer simulations have been performed and satisfactory agreements between these comparisons have been obtained. The reverse I–V characteristics of the fabricated Al-n-p silicon Schottky barrier diodes can also be well simulated by the developed model.     

An analytic procedure for extraction of metallic collector-up InP/InGaAsP/InGaAs HBT small signal equivalent circuit parameters

A parameter extraction procedure for determining an improved T-topology small signal equivalent circuit of a metallic collector-up HBT with composite base is presented. The proposed T-small signal equivalent circuit includes base and collector impedances modelled by parallel RC circuits. The new technique employs analytically derived expressions for direct calculation of HBT T-Model equivalent circuit element values in terms of the measured S-parameters. This approach avoids errors due to uncertainty in fitting to large, over determined equivalent circuits and does not require the use of test structures and extra measurement steps to evaluate parasitics. Physically realistic results are demonstrated under various biasing conditions for the n–p–n InP/InGaAsP/InGaAs composed base HBT with metallic collector-up structure (C-up MHBT). The agreement between the measured and model-produced data is excellent over the large frequency range and for several polarizations conditions for devices.     

Hot photo-carrier and hot electron effects in p-n junctions

When a p-n junction of semiconductor (with bandgap energy E_g) is illuminated by light beam (with photon energy hv) in the condition of E_g>hv, such as in Ge p-n junction illuminated by CO₂ laser beam, an electromotive force (emf) was induced between the terminals of the p-n junction, which indicated the opposite polarity to the ordinary photovoltaic effect like a solar cell. Such an anomalous photovoltaic phenomenon was explained by an optically excited hot carrier effect, through the following experiment with electrical excitation. Using a rod of n- or p-type Ge with a p-n junction at the surface of its center and an ohmic contact at each terminal of the rod, the same kind of phenomena was observed when electric field is applied along the length of the rod. The perpendicularly induced voltage or current had the same polarity instead of the reverse change of the applied electric field, and increases with increasing the applied field strength. The perpendicularly induced emf was caused by warm or hot carriers crossing the potential barrier of the p-n junction, which is very sensitive to the departure from thermally equilibrium velocity distribution of carriers.     

Current-voltage characteristics of GaAs p-i-n and n-i-n diodes

Using the same basic equations as Kazarinov et al.[2], but assuming that the product of the electron drift velocity and of the electron lifetime remains constant, we have derived a new formula for the forward d.c. current—voltage characteristic distinguished by the saturated voltage. We have shown that this formula can describe the measured characteristics of some GaAs p-i-n and n-i-n diodes.     

Theory of switching in p-n-insulator (tunnel)-metal devices—II: Avalanche mode

The four layer structure M-I (leaky)-n-p semiconductor displays a current-controlled negative-resistance in its I-V characteristic. The device is named “MISS” which is an acronym for Metal-Insulator-Silicon-Switch. The punch-through mode of operation of the device was treated in an earlier paper (part I). The avalanche-mode of the operation of the device is now considered.In addition to the basic positive feedback action associated with the punch-through MISS, a second positive feedback action is found to exist in the avalanche-mode MISS, which parallels that responsible for switching in an avalanche transistor. The coexistence of these two regenerative feedback actions can, under favourable conditions, result in three stable states in the I-V characteristic of the MISS. A device incorporating this behaviour can be of importance in multi-level logic circuits.     

On the small-signal equivalent circuit of p-n junctions in the condition of finite carriers multiplication

A new version of the equivalent circuit of the space-charge region of the reverse biased p-n junction is evaluated and the expressions for the circuit parameters are given. The basic idea is to separate the equivalent circuit in to the “conductive” and “displacement” branches and in this way the equivalent circuit parameters have physical meaning. The results are applicable to conditions of the finite multiplication factors and unequal ionization coefficients in a wide range of frequency and in the presence of the generation of carriers (thermal or outside induced) in the space-charge region. The numerical results for two complementary abrupt silicon p-n junctions and for low-frequency are given. The equivalent circuit of the multiplication noise source of the p-n junction is discussed.     

A calculation of the capacitance-voltage characteristics of p+-InP/n-InP/n-InGaAsP photodiodes

An analytic solution for the capacitance-voltage characteristics of p⁺?InP/n?InP/n?InGaAsP diodes has been obtained. The solution, which closely approximates that obtained using numerical methods, indicates that the dip followed by a peak generally observed in the effective carrier concentration profile as derived from experimental capacitance measurements is likely due to the properties of the n-n heterojunction rather than actual variations in the doping concentration. The availability of the analytic solution greatly facilitates the study of the effects of various parameters on these characteristics. The influence of grading and the collection of holes in the notch formed by the valence band discontinuity is also briefly considered.     

A structure-oriented model for determining the substrate spreading resistance in bulk CMOS latch-up paths and its application in holding current prediction

A structure-oriented model has been developed to simulate the actual distribution of majority-carrier current flow paths in the substrate when the parasitic p-n-p-n structure with long-stripe geometry in a CMOS (complementary metal—oxide-semiconductor) circuit is at the latch-up state. Based on this structure-oriented model, the voltage drop across the latch-up path in the substrate can be calculated directly from the structure data. Therefore, the equivalent emitter-base shunting resistance in the substrate can be easily obtained and used to accurately predict the holding current. The two-dimensional numerical simulations have been carried out, based on this structure-oriented model, to obtain the emitter-base shunting resistance associated with the parasitic lateral bipolar transistor in the substrate. The computed substrate shunting resistance and the well emitter-base shunting resistance have been used to calculate the holding current with the help of the measured peak parasitic transistor gains. The predicted holding currents have been found to be in good agreement with the experimental data measured from several p-n-p-n structures, including normal and reversed layouts which are all designed by using the long-stripe geometries. Furthermore, the numerical simulations have been extended to predict the effects of the layout changes of the p-n-p-n structures on the latch-up susceptibility.     

The effect of photogenerated carriers on the mean time delay for avalanche breakdown in p-n junctions

Avalanche breakdown in p-n junctions is preceded by a delay time between application of an overvoltage and the actual initiation of an avalanche discharge. The mean of this delay time has been studied as a function of photogeneration in p-n junction devices. Results agree well with McIntyre's theory of breakdown probability. The data further indicate that the probability of any given carrier initiating breakdown is independent of carrier concentration over the three orders of magnitude investigated.     

Evaluation of magnesium and manganese as the P-type dopant for InP/InGaAs heterojunction transistors

Among Zn, Cd, Mg, Mn, and Be as the p-type dopant in InGaAs, Mg and Mn were taken as candidates for the dopant in the base region of InP/InGaAs heterojunction transistors. Properties of the two dopants were investigated in terms of doping reproducibility, diffusion in solid phase, and attainable optical gain in the InP/InGaAs heterojunction phototransistors. Mn was found to be suitable for the p-type dopant in the InGaAs base region of InP/InGaAs n-p⁺-n transistors.     

Drift of the breakdown voltage in p-n junctions in silicon (walk-out)

A quantitative model for the time behaviour of the walk-out phenomenon in planar p-n junctions is given. The injection of hot carriers into SiO₂ and subsequent trapping of part of them is assumed to be the origin of the walk-out. The model is found to be in reasonable agreement with the experimental results on both p⁺?n and n⁺?p junctions. The parameters in the model are discussed in relation with the experiments.     

A thyristor protected against di/dt failure at breakover turn-on

The principle and the operation of a thyristor that can be turned on by exceeding its breakover voltage are described. The principle uses the concept of an auxiliary thyristor amplifying the small breakover current to a large gate current for the main thyristor. In this arrangement the breakover turn-on has to occur first in the auxiliary thyristor. This is ensured by a doping of the n-base of the auxiliary thyristor which is higher than that of the n-base of the main thyristor. Time resolved infrared photographs of the breakover turn-on are presented. Also, infrared photographs of the breakdown radiation from p-n-p structures are used to give a survey on the starting silicon which already contains the inhomogeneous doping.     

Instrumentation and analog implementation of the Q-C method for MOS measurements

The instrumentation required to implement the Q-C (charge-capacitance) method and the effects of parasitics are described. Accurate results with the Q-C method critically depend on controlling and properly accounting for these parasitics. Also described are analog computer circuits for calculating band bending vs gate voltage, and doping profile from the measured quantities.