On the tunneling component of charge pumping current in ultrathingate oxide MOSFETs

A simple method is described for separating the charge pumping current from the parasitic tunneling component in a charge pumping measurement performed on MOS transistors with ultrathin (<2 nm) gate oxide thickness. The method is presented here for a two-level charge pumping signal and can be used to significantly increase the accuracy of the technique to extract interface trap parameters in tunnel MOS devices     

Tunneling component suppression in charge pumping measurement and reliability study for high-k gated MOSFETs

Although charge pumping (CP) is a powerful technique to measure the energy and spatial distributions of interface trap and oxide trap in MOS devices, the parasitic gate leakage current in it is the bottleneck. A CP method was modified and applied to high-k gate dielectric in this work to separate the CP current from the parasitic tunneling component in MOS devices. The stress-induced variations of electrical parameters in high-k gated MOS devices were investigated and the physical mechanism was studied by the modified CP technique. The stress-induced trap generation for devices with HfO₂-dominated high-k gate dielectrics is like mobile defect; while that with SiO₂-dominated ones is similar to the near-interface/border trap.     

Electrical and physical characteristics of HfLaON-gated metal-oxide-semiconductor capacitors with various nitrogen concentration profiles

The comparative studies of electrical and physical characteristics of HfLaON-gated metal-oxide-semiconductor (MOS) capacitors with various nitrogen concentration profiles (NCPs) were investigated. Various NCPs in HfLaON gate dielectrics were adjusted by Hf₂La₂O₇ target sputtered in an ambient of modulated nitrogen flow. The related degradation mechanisms of various NCPs in HfLaON dielectrics have been investigated under various post-deposition annealing (PDA). The results indicate that by developing full nitrogen profile (FNP) incorporated into HfLaON dielectric enhances electrical characteristics, including oxide trap charge, interface trap density, and trap energy level. Detailed understand of current mechanisms of various NCPs incorporated into HfLaON dielectrics using current-voltage characteristics under various temperature measurements were investigated. Energy band diagram of MOS capacitor with Ta/HfLaON/SiO₂/P-Si(1 0 0) structure was demonstrated by the measurement of Schottky barrier height and the optical band gaps.     

Effects of electrical stressing in power VDMOSFETs

The effects of gate bias stressing on threshold voltage and mobility in power VDMOSFETs and underlying changes in gate oxide-trapped charge and interface trap densities are presented and analysed in terms of the mechanisms responsible. It is shown that gate bias stressing causes significant threshold voltage shift and mobility degradation in power VDMOSFETs; the negative bias stressing causes more rapid initial changes of both threshold voltage and mobility, but the final threshold voltage shift and mobility reduction are significantly larger in devices stressed by positive gate bias. In the case of positive bias stressing, electron tunnelling from neutral oxide traps associated with trivalent silicon defects into the oxide conduction band is proposed as the main mechanism responsible for positive oxide-trapped charge buildup, while subsequent hole tunnelling from the charged oxide traps to interface-trap precursors Si_s–H is shown to be the dominant mechanism responsible for the interface trap buildup. In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Si_s–H with the charged oxide traps and H⁺ ions are proposed to be responsible for interface trap buildup.     

MOS栅氧的界面特性和辐照特性研究

通过交流电导法,对经过不同时间N₂O快速热处理(RTP)的MOS电容进行界面特性和辐照特性研究。通过电导电压曲线,分析N₂O RTP对Si-SiO₂界面陷阱电荷和氧化物陷阱电荷造成的影响。结论表明,MOS电容的Si-SiO₂界面陷阱密度随N₂O快速热处理时间先增加再降低;零偏压总剂量辐照使氧化层陷阱电荷显著增加,而Si-SiO₂界面陷阱电荷轻微减少。     

Modeling MOS capacitors to extract Si—SiO2interface trap densities in the presence of arbitrary doping profiles

A conventional Poisson solver has been used to calculate the quasi-static capacitance of an MOS capacitor. The effects of an energy dependent Si-SiO2interface trap density and of an arbitrary silicon substrate doping profile have been included. This model has been used to calculate the quasi-staticC-Vcharacteristics and to compare them with those measured using Kuhn's technique for as-received and for gamma-irradiated p-type and n-type silicon MOS capacitors. The substrate doping profiles were obtained from high-frequencyC-Vcurves. Experimental and theoreticalC-Vcurves were made to agree by varying the voltage offset due to fixed oxide charge and both the magnitude and the energy distribution of interface trapped charge. The distributions of interface traps that gave the best fits between experiment and theory are donor-like with a peak 0.1 eV below midgap for the p-type and 0.1 eV above midgap for the n-type silicon MOS capacitors. The predictedC-Vcurves are insensitive to increases in the density of interface traps near the band edge.     

A New Method for Extracting Interface Trap Density in Short-Channel MOSFETs from Substrate-Bias-Dependent Subthreshold Slopes

Interface trap densities at gate oxide/silicon substrate (SiO₂/Si) interfaces of metal oxide semiconductor field-effect transistors (MOSFETs) were determined from the substrate bias dependence of the subthreshold slope measurement. This method enables the characterization of interface traps residing in the energy level between the midgap and that corresponding to the strong inversion of small size MOSFET. In consequence of the high accuracy of this method, the energy dependence of the interface trap density can be accurately determined. The application of this technique to a MOSFET showed good agreement with the result obtained through the high-frequency/quasi-static capacitance-voltage (C-V) technique for a MOS capacitor. Furthermore, the effective substrate dopant concentration obtained through this technique also showed good agreement with the result obtained through the body effect measurement.     

Theory and experiments on surface 1/f noise

A theoretical low-frequency noise model for the epitaxial-channel surface field-effect structure is presented where random modulation of the channel conductance arises from fluctuation of charges trapped at the oxide trap states near the Si-SiO2interface. In this model, charge fluctuation in the oxide traps arises from carrier tunneling between the fast interface surface states and the oxide trap states. A second fluctuation, at higher frequencies, arises from the random thermal emission and capture of electrons and holes at the fast interface states through the thermal or Shockley-Read-Hall process. Different oxide trap densities were introduced into the interface region of the metal-oxide-silicon field-effect structures using a carefully controlled and reproducible oxygen heat treatment technique. Energy distributions of the oxide trap densities are obtained from capacitance measurements. Humps are observed between the flat band and the onset of strong surface inversion (lower half of the bandgap) in both the noise power and the oxide trap density versus gate voltage (or surface band bending) plots. Theoretical noise power calculations using the experimental oxide trap density profile from the capacitance-voltage data agree very well with the experimental noise humps in both magnitudes and fine structures. It is shown that the frequency spectra of noise depend strongly on the oxide trap density profile in the oxide. It is suggested that the oxide traps are due to the excess oxygen at the SiO2-Si interface.     

Correlation between most 1/f noise and CCD transfer inefficiency

The 1/f noise in MOS transistors has been investigated and is shown to correlate with charge transfer inefficiency experiments on surface-channel CCDs. Both independent phenomena can be quantitatively explained by the same interface state model. The oxide trap density turns out to vary by more than a factor 10. The 1/f noise is compared with McWhorter's number fluctuation model and with the mobility fluctuation model. The oxide trap density is calculated from the charge transfer inefficiency in surface CCDs. Both the quantitative agreement between oxide trap density and 1/f noise and the observed dependence of 1/f noise on gate voltage here give strong arguments in favour of the McWhorter model. The investigated MOS transistors fall into a category that cannot be explained by the present mobility fluctuation model.     

Study of the electronic trap distribution at the SiO2-Siinterface utilizing the low-frequency noise measurement

A correlation of the trap distribution at the silicon-oxide interface with the low-frequency noise measurement in MOS devices at temperatures ranging from 77 to 300 K is presented. Several devices with differently prepared gate oxides were used to study the process-induced trap distribution. Several peaks varying from sample to sample are found in a frequency index of noise spectrum versus temperature plot and are correlated with the discrete trap distribution across the bandgap of silicon. This method provides more information on traps as it circumvents the complexity of superimposing different traps which was encountered in the capacitance-voltage (C-V) method. Results, either compatible with others' work or consistent with data based on other measurements, show that the electronic trapping behavior in MOS structures is governed by two intrinsic traps located at 0.12 and 0.3 eV (both measured from the conduction band) for all kinds of oxides. In addition, dry oxidation was found to introduce an additional trap at an energy level of 0.23 eV, and annealing the gate oxide in ammonia at a high temperature (>1000°C) results in an enhancement of the trap density of 0.43 eV below the conduction band edge of silicon, which was also observed in a quasi-static C-V measurement     

Instrumentation and analog implementation of the Q-C method for MOS measurements

The instrumentation required to implement the Q-C (charge-capacitance) method and the effects of parasitics are described. Accurate results with the Q-C method critically depend on controlling and properly accounting for these parasitics. Also described are analog computer circuits for calculating band bending vs gate voltage, and doping profile from the measured quantities.     

In-depth exploration of Si-SiO2 interface traps in MOStransistors using the charge pumping technique

It is shown that the charge pumping (CP) technique can be used for extraction of the depth concentration profile of traps situated in the oxide of metal-oxide-semiconductor (MOS) transistors, near and at the Si-SiO₂ interface. The trap density is obtained from the variation of the charge pumping current as a function of frequency, the other measurement parameters being kept constant. The concentration profiles are measured on n and p-channel transistors from several technologies, and on virgin and stressed devices. The results show that the trap concentration decreases rapidly from the Si-SiO₂ interface in the direction of the oxide depth and suggest that it becomes constant at a fraction of a nanometer from the silicon interface. The method easily demonstrates the trap creation due to Fowler-Nordheim stress. The profiles compare favorably with those measured using a new drain-current transient technique. In all cases, the integration of the depth concentration profiles leads to the interface trap densities measured using the conventional charge pumping method     

Effect of strain-temperature stress on MOS structure with ultra-thin gate oxide

A method called strain-temperature stress was adopted in this work to improve the quality of ultra-thin oxide on both MOS(p) and MOS(n) capacitors. MOS structures were baked at 100 °C under externally applied mechanical stress. Reduced gate leakage current, reduced interface trap density (D_it), and improved time-dependent-dielectric-breakdown (TDDB) characteristics were observed after tensile-temperature stress treatment without increasing the oxide thickness. On the contrary, compressive-temperature stress resulted in a degraded performance of MOS capacitors. Consequently, the tensile-temperature stress method is suggested as a possible technique to enhance the ultra-thin oxide quality of MOS structure.     

A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET's

A new method is described for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements. The admittance of the conduction channel of the MOSFET is derived from a transmission line model. The peaks of theG/omegaversus ω curves are used to deduce gate-channel capacitance and mobility. The mobile carrier density and mobility in very thin-oxide MOSFET's can be measured more accurately using this ac method, since a zero lateral field and a uniform mobile charge distribution along the channel is maintained with zero drain-source voltage and interface trap effects are reduced by using high test frequencies. Measured data on the electron mobility versus gate voltage are presented for 90-A gate dielectric MOS transistors.     

Interface trap passivation effect in NBTI measurement for p-MOSFET with SiON gate dielectric

New findings of interface trap passivation effect in negative bias temperature instability (NBTI) measurement for p-MOSFETs with SiON gate dielectric are reported. We show evidence to clarify the recent debate: the recovery of V/sub th/ shift in the passivation phase of the dynamic NBTI is mainly due to passivation of interface traps (N/sub it/), not due to hole de-trapping in dielectric hole traps (N/sub ot/). The conventional interface trap measurement methods, dc capacitance-voltage and charge pumping, seriously underestimate the trap density N/sub it/. This underestimation is gate bias dependent during measurement, because of the accelerated interface trap passivation under positive gate bias. Due to this new finding, many of previous reliability studies of p-MOSFETs should be re-investigated.     

Radiation damage of thermally oxidized MOS capacitors

The influence of preparation parameters and the effect of X-rays (150 keV, 10⁴rad (Si)) on oxide charge Qoxand interface state density Nssin thermally oxidized MOS varactors under different biasing conditions during irradiation has been investigated. The interface state density was determined by the ac conductance method before and after irradiation. The oxide charge has been evaluated with regard to the charge Qssof the interface states. Qsshas beeu discussed with the aid of simple models concerning the energetic distribution and recharge character of the interface states. The results indicate a similar dependence between flatband voltage, interface state density, and normalized oxide charge density as a function of gate bias during irradiation. Furthermore, the so-called "oxidation triangle" of oxide charge before irradiation exists for interface states as well. Calculations on the basis of the Schottky barrier model of the irradiated MOS structure show that the radiation-induced charge exists at both interfaces in the oxide layer. Radiation tolerance of the MOS capacitors as a function of technological parameters is discussed.     

Rapid interface parameterization using a single MOS conductance curve

Figures are presented for finding interface trap density D_it capture probability c_p, and interfacial broadening σ_s, from a single curve of small-signal MOS interface trap conductance G_it/ω vs either band bending ν_s, or frequency f[ω = 2πf]. Almost no computation is necessary. An additional figure allows the depletion layer capacitance to be determined if the oxide capacitance and the measured capacitance at the maximum value of G_it/ω are known.The extension to G_it/ω vs ν_s, curves is a convenience. Parameters throughout the bandgap can be obtained from measurements at fewer frequencies than are needed for construction of accurate G_it/ω vs f curves. Economy also results because data usually are obtained by sweeping gate bias at selected frequencies. Construction of G_it/ω vs ν_s curves from the data is simpler than G_it/ω vs f, particularly if ν_s is measured directly.The information needed from the G_it/ω curve is the maximum value of G_it/ω and the width of the peak at an arbitrary fraction of its maximum value, fw. In addition, for capture probability only, the frequency and band bending at the peak maximum are needed, as well as the bulk doping.The method assumes validity of the Gaussian approximation to broadening of the conductance peak. Comparison of the parameters obtained for several choices of fw allows a check of this assumption, which usually is valid for MOS devices.     

Procedure for determination of a linear approximation doping profile in a MOS structure

A method for determination of a linear approximation doping profile in a semiconductor is presented. The procedure is based on measurement of the high frequency C-V characteristic of a MOS capacitor. The proposed approximation of doping profile is sufficiently accurate in practical cases and the method is fast. Hence it can be applied in MOS device modelling or routine MOS technology diagnostics.     

Characterization of various stress-induced oxide traps in MOSFET'sby using a subthreshold transient current technique

An oxide trap characterization technique by measuring a subthreshold current transient is developed. This technique consists of two alternating phases, an oxide charge detrapping phase and a subthreshold current measurement phase. An analytical model relating a subthreshold current transient to oxide charge tunnel detrapping is derived. By taking advantage of a large difference between interface trap and oxide trap time-constants, this transient technique allows the characterization of oxide traps separately in the presence of interface traps. Oxide traps created by three different stress methods, channel Fowler-Nordheim (F-N) stress, hot electron stress and hot hole stress, are characterized. By varying the gate bias in the detrapping phase and the drain bias in the measurement phase, the field dependence of oxide charge detrapping and the spatial distribution of oxide traps in the channel direction can be obtained. Our results show that 1) the subthreshold current transient follows a power-law time-dependence at a small charge detrapping field, 2) while the hot hole stress generated oxide traps have a largest density, their spatial distribution in the channel is narrowest as compared to the other two stresses, and 3) the hot hole stress created oxide charges exhibit a shortest effective detrapping time-constant     

Silicon-gate CMOS devices with 300 Å gate oxides

Polycrystalline silicon gate (phosphorus doped) complementary MOS structures were fabricated with gate oxide thicknesses down to 300 Å. Measurements of the oxide fixed charge, Q_ss, and of the back-gate bias dependence of the threshold voltage indicate an absence of phosphorus diffusion through the gate oxide during conventional processing.