Potential and limitations of Schottky-barrier barritt devices

Computer simulation of various Schottky-barrier structures is carried out to investigate the large-signal properties of these devices. Comparison between Schottky-barrier devices and their p-n junction counterparts are also made to evaluate the potential and limitations of these devices and to explain the difference in performance between them. It is shown that among various Schottky-barrier structures, the M-n-i-p⁺ structure is the most powerful one and the M-n-p-p⁺ device is the most efficient one. Furthermore, Schottky-barrier devices with low barrier heights for minority carriers (less than 0.2 eV) are capable of producing power levels close to the generated power of p-n junction devices. Investigation of the temperature dependence of the large-signal performance of these devices shows that Schottky barriers are more sensitive and exhibit their optimum performance close to room temperature value. At low temperature, the output power is limited by the low minority carrier injection, whereas at high temperature the limitation is due to the velocity-modulation losses in the injection and low-field regions of the device.     

Silicon p−n insulator-metal (p-n-I-M) devices

Silicon p-n-I-M devices with thin insulating layers ($\text{thicknesses}\text{? 30}\text{A}\text{?}$), named MTIS devices, have been developed. The two terminal device shows an S-shaped negative resistance characteristics similar to a Schockley diode (or p-n-p-n diode). Typically the threshold and sustaining voltages are 10 ～ 15 and 1.3 ～ 2 volts, respectively. The former however can be controlled by optical illumination. Turn-on time including delay is less than 2 nsec and turn-off time ? 1 nsec or less. A thyristor-like device with its third terminal connected to the n-layer shows switching operation controllable by this terminal. A monolithic linear array of p-n-I-M diodes with 30 μm spacing operates as a shift register through coupling of adjacent diodes. Life of the two terminal devices recorded at present is over 1.5 × 10⁴ hr. These devices can be applied to low power and high-speed electrical switching and also to optical switching and integrated logic circuits.     

Theoretical calculations of Debye length,built-in potential and depletion layer width versus dopant density in a heavily doped p-n junction diode

Theoretical calculations of Debye length, built-in potential, depletion layer width and capacitance as a function of dopant density in a heavily doped p-n junction diode are described in this paper. The heavy doping effects such as carrier degeneracy, dopant density-dependent dielectric constant and bandgap narrowing are accounted for by using the empirical approximation for the reduced Fermi-energy given by[1] and the dopant density dependent dielectric constant given by[2], as well as the bandgap narrowing model proposed by[3]. The results show that: (1) bandgap narrowing and carrier degeneracy have important effects on the junction built-in potential; (2) carrier degeneracy and dopant density-dependent dielectric constant are important to Debye length for the abrupt junction case, and (3) the dopant density-dependent dielectric constant is a key parameter which strongly affects the values of depletion layer width and depletion capacitance. These findings are important for modeling of heavily doped p-n junction devices in the VLSI applications.     

Effect of irradiation with fast neutrons on electrical characteristics of devices based on CVD 4<Emphasis Type="Italic">H</Emphasis>-SiC epitaxial layers

The effect of irradiation with 1-MeV neutrons on electrical properties of Al-based Schottky barriers and p⁺-n-n⁺ diodes doped by ion-implantation with Al was studied; the devices were formed on the basis of high-resistivity, pure 4H-SiC epitaxial layers possessing n-type conductivity and grown by vapor-transport epitaxy. The use of such structures made it possible to study the radiation defects in the epitaxial layer at temperatures as high as 700 K. Rectifying properties of the diode structures were no longer observed after irradiation of the samples with neutrons with a dose of 6×10¹⁴ cm^?2; this effect is caused by high (up to 50 GΩ) resistance of the layer damaged by neutron radiation. However, the diode characteristics of irradiated p⁺-n-n⁺ structures were partially recovered after an annealing at 650 K.     

Theory for voltage dependent series resistance in silicon solar cells

A distributed parameter model has been proposed for p-n junction solar cells to account for the variation of series resistance due to the forward biasing of the p-n junction under external injection condition. The theoretical expression developed using this model predicts a coupling between base and emitter via depletion layer. This coupling becomes stronger with increasing bias and is found to be responsible for the observed decrease of series resistance with rising injection level. Numerical results of our theory are found to agree well with those obtained from experiments.     

A structure-oriented model for determining the substrate spreading resistance in bulk CMOS latch-up paths and its application in holding current prediction

A structure-oriented model has been developed to simulate the actual distribution of majority-carrier current flow paths in the substrate when the parasitic p-n-p-n structure with long-stripe geometry in a CMOS (complementary metal—oxide-semiconductor) circuit is at the latch-up state. Based on this structure-oriented model, the voltage drop across the latch-up path in the substrate can be calculated directly from the structure data. Therefore, the equivalent emitter-base shunting resistance in the substrate can be easily obtained and used to accurately predict the holding current. The two-dimensional numerical simulations have been carried out, based on this structure-oriented model, to obtain the emitter-base shunting resistance associated with the parasitic lateral bipolar transistor in the substrate. The computed substrate shunting resistance and the well emitter-base shunting resistance have been used to calculate the holding current with the help of the measured peak parasitic transistor gains. The predicted holding currents have been found to be in good agreement with the experimental data measured from several p-n-p-n structures, including normal and reversed layouts which are all designed by using the long-stripe geometries. Furthermore, the numerical simulations have been extended to predict the effects of the layout changes of the p-n-p-n structures on the latch-up susceptibility.     

Depletion layer formation,space-charge injection and current-voltage characteristics for the silicon p-n-p (n-p-n) structure

Depletion layer formation and current-voltage characteristics are described for the general semiconductor p-n-p (n-p-n) structure in which the impurity or defect centre is able to communicate with both sets of transport levels. All possibilities for current lie within the region bounded on one side by the essentially vertical Shockley-Prim punch-through characteristic and on the other side by the square-law Mott-Gurney space-charge-limited characteristic. If the impurity levels lie near the mid-gap position a variety of characteristics within this region can be expected. Representative current-voltage characteristics have been computed and are described for a typical silicon structure.     

Equivalent circuits for transients in p-n junctions and solar cells with their application to methods for minority carrier life-time measurements

Equivalent circuits corresponding to series solutions obtainable under various operating conditions of p-n junctions and solar cells are given. These circuits are directly applicable to the small signal impedance measurements. The transient behaviour of the p-n junction devices during minority carrier lifetime determination experiments has also been explained successfully with the help of these circuits. This provides a better insight towards the physical processes involved in these methods and interpretation of the various experimental results becomes easier.     

The effect of photogenerated carriers on the mean time delay for avalanche breakdown in p-n junctions

Avalanche breakdown in p-n junctions is preceded by a delay time between application of an overvoltage and the actual initiation of an avalanche discharge. The mean of this delay time has been studied as a function of photogeneration in p-n junction devices. Results agree well with McIntyre's theory of breakdown probability. The data further indicate that the probability of any given carrier initiating breakdown is independent of carrier concentration over the three orders of magnitude investigated.     

High-voltage planar junction with a field-limiting ring

A twodimensional Poisson equation is solved as part of a program to improve breakdown characteristics of a planar p-n junction by using a field limiting ring. The influences of n^? concentration and n^? layer width of p⁺-n^?-n⁺ diode are investigated. Higher n^? concentration and smaller n^? width make optimum distance between anode and field limiting ring smaller. Breakdown voltages predicted by optimising method reported agree well with the experimental results.     

Profiling the boron distribution in asymmetric n +-p silicon photodiodes and a new concept for creating selectively sensitive photocells for megapixel color-image receivers

The spectral photosensitivity of n ⁺-p silicon photodiodes with a p ⁺ layer implanted in the substrate is studied experimentally. It is demonstrated that such p ⁺ doping effectively shifts the long-wavelength edge of the photosensitivity in the optical spectral range and the shift depends on the depth of the p ⁺ layer. A new concept for creating selectively sensitive photocells for megapixel color-image receivers is proposed. The receivers are based on n ⁺-p photodiode structures containing a few layers that are implanted at different depths and form desired color-separating potential barriers and lateral diffusion channels for collection of the minority carriers generated by photons of different colors.     

A dynamic model of the p-n-n+ step recovery diodes for the numerical analysis of pulse circuits

A new p-n-n⁺ diode model for circuit transient analysis is developed. In contrast to existing circuit models, this model reflects all step-recovery diode (SRD) effects during switching on and off, including “ramp” of slow recovery phase. It is accomplished by taking into account the dynamic physical phenomena in the p-n-n⁺ diodes when switched. A non-linear dynamic diffusion capacitance of the diode model is determined by the dependence of the instantaneous base charge on the instantaneous diode voltage.The accuracy of the presented model is verified by comparison of the calculated and measured wave forms of some pulse circuits.The present model has been proved to be more accurate than SRD models previously published.     

A finite-element model and characterization of the p-i-n magnetodiode at microwave frequencies

A finite element, resistive network analog model is presented and applied to p-i-n magnetodiodes at a microwave frequencies. The network analog model is outlined and verified with microwave measurements on a mesa-style p-i-n diode. The microwave measurements, coupled with data obtained by the model, are shown to provide a measure of the ambipolar mobility in the i-region of the semiconductor device. The magnetosensitivity of the magnetodiode as a function of geometry is also discussed.     

A simplified model for graded-gap heterojunctions

A simplified method for calculating the energy band profiles of graded-gap heterojunctions, based on the generalized model of Oldham and Milnes, is presented. The profiles are derived by superposing an energy band grading function and the electrostatic potential in the heterojunction. The latter is obtained by using the depletion layer approximation as for conventional p-n homojunctions. The energy band profiles of hypothetical p(GaAs)-n(Al_0·4Ga_0·6As) heterojunctions are calculated using the simplified method. For small grading layer widths, the results are in good agreement with the generalized model. The barrier lowering factor η as a function of the graded layer width l is calculated for such heterojunctions. It is found, for acceptor and donor densities of 10¹⁸ and 10¹⁶ cm^?3 respectively, that the barrier height is reduced from 0·47 eV to zero as l increases from zero (abrupt case) to ≈300 Å. The applications of these analyses to practical heterojunctions are discussed.     

Solution of the problem of charge-carrier injection into an insulating layer under self-consistent boundary conditions at contacts

The problem of charge carrier injection into a finite-length insulating layer is analytically solved in the drift-diffusion approximation, taking into account self-consistent boundary conditions. The main assumption is the neglect of intrinsic doping of the i-type layer. The solution allows calculation of the potential, electric field, and current-voltage characteristics of various structures, i.e., metal-i-n ⁺ (or p ⁺)-semiconductor, metal-i-layer-metal, and n ⁺(p ⁺)-i-n ⁺(p ⁺) structures. The solution allows generalization for structures having heterobarriers at semiconductor layer interfaces. The proposed approach considers contact phenomena and volume effects associated with the space-charge-limited current in the i-type layer. The solution is valid in both extreme cases and intermediate conditions.     

A discrete element small-signal equivalent circuit for forward-biased p+n diodes containing deep levels

A discrete element small-signal equivalent circuit model for p-n diodes containing deep defect levels is developed, by extending an existing model for undamaged devices. With the aid of a simple analytical expression which accurately describes the forward bias d.c. current, the enhanced small-signal conductance due to carrier recombination in the depletion region is included in the model. The influence of trapped charge on the space charge capacitance is incorporated using a simplified version of the analysis of Beguwala and Crowell. The predictions of the model are verified by experimental data from silicon p⁺n diodes, in which deep levels have been induced by electron irradiation. It is shown that the deep level activation energies may be estimated from the forward bias capacitance-voltage characteristics, yielding values which agree well with those obtained by established techniques.     

A review of ohmic and rectifying contacts on cadmium telluride

The state-of-the-art of contact formation on n and p-type cadmium telluride is discussed in this paper. We summarize the main surface properties, which influence the contact behavior, and the various technologies, which have been used to fabricate ohmic and rectifying contacts on CdTe. In this way MS and MIS structures, p-n junctions, and heterojunctions have been considered. In all cases we indicate the advantages and disadvantages of the electrical behavior of the devices.     

Theory of switching in p-n-insulator (tunnel)-metal devices: Part I: Punchthrough mode

The four-layered structure (M-I(leaky)-n-p⁺) is found to exhibit a current-controlled negative resistance region in its I-V characteristics. In this paper, a quantitative physical model of the device in the punch-through mode is presented. The negative resistance behaviour is due to a positive feedback mechanism between the tunnel MIS and the n-p⁺ junction parts of the device. The effect of the device parameters on its I-V characteristics is studied.     

Degradation mechanism for silicon p+-n junctions under forward bias

Leakage current degradation has been observed during forward bias stressing of silicon integrated p⁺-n junctions. Detailed characterization results of the anomalous leakage behavior are discussed in this paper. From these results an electric field-enhanced impurity diffusion mechanism has been proposed to explain both the strong temperature and forward bias dependencies on leakage current time-to-saturation. An activation energy has been determined for this mechanism (0.48±0.04 eV) and is in good agreement with that previously determined for diffusion of interstitial copper in p-type silicon. Subsequent Secondary Ion Mass Spectrometer elemental analysis has confirmed the presence of copper near the surface of the epitaxial layer containing the p⁺-n device.