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对基于模代数的三值触发器的研究 总被引:9,自引:0,他引:9
本文用模代数讨论三值触发器。提出了基于模代数的三值 JK 触发器。与基于 Post代数的三值 JK 触发器相比,它的逻辑功能是均衡的,它能像二值 JK 触发器一样方便地构成另外二种常用的触发器:三值 D 型触发器与三值 T 型触发器。此外,由时序电路的设计实例,也证实了因它的功能较强而能导致较简单的激励函数与组合电路。 相似文献
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双端置数技术与高值CMOS触发器设计 总被引:5,自引:1,他引:4
在分析以往高值触发器困难的基础上本文提出了双端予置的逻辑设计方案。应用传输函数理论对四值CMOS触发器进行了电路设计。结果表明,与存贮相同信息量的二个二值触发器相比,它有较简单的结构与较快的工作速度。 相似文献
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电流型CMOS脉冲D触发器设计 总被引:1,自引:0,他引:1
该文根据脉冲触发器的设计要求,结合阈算术代数系统,提出一种电流型CMOS脉冲D触发器的通用结构,用于二值及多值电流型CMOS脉冲触发器的设计,并可方便地应用于单边沿和双边沿触发。在此结构的基础上设计了电流型CMOS二值、三值以及四值脉冲D触发器。采用TSMC 180 nm CMOS工艺参数对所设计的电路进行HSPICE模拟后表明所设计的电路具有正确的逻辑功能和良好的瞬态特性,且较以往文献提出的电流型D触发器,优化了触发器的建立时间和保持时间,二值和四值触发器最差最小D-Q延时比相关文献的主从触发器降低了59.67%和54.99%,比相关文献的边沿触发器降低了4.62%以上,所用晶体管数也相对减少,具有更简单的结构以及更高的电路性能。 相似文献
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基于集成门电路的三值单稳态触发器研究 总被引:1,自引:0,他引:1
通过对二值单稳态触发器设计原理的重新归纳,本文从三值三稳态触发器的正确设计出发,提出了二种三值单稳态触发器的设计方案。以RC微分电路为定时电路的设计已用PSPICE程序进行计算机验证。 相似文献
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多值时钟与并列式多拍多值触发器 总被引:8,自引:2,他引:6
通过对现有多值主从触发器-串列式二拍多值主从触发器的分析,本文指出了这些触发器并不符合使用信号增加信息携带量的要求,从而提出了采用多值时钟的并列式多拍多值触发器,并设计了四值D触发器,这种发器具有存贮能力强,逻辑结构丰富的特点。 相似文献
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任意值数的时序逻辑电路设计 总被引:2,自引:0,他引:2
本文提出了一种值数可任意扩展的多值逻辑存贮单元——DYL多值D触发器。文中将二值时序电路设计方法推广到多值逻辑系统中,运用DYL电路的线性与或门和阈门以及多值D触发器,实现了任意值数的时序逻辑电路设计。 相似文献
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根据在保持电路原有性能的前提下可通过降低时钟频率来降低系统功耗的原理和双边沿触发器的设计思想,本文将多值信号信息量大的优点应用于时钟网络上设计了基于三值时钟的四边沿触发器,消除了三值时钟的冗余跳变,从而通过降低时钟频率的方式达到降低功耗的目的。本文设计的四边沿触发器电路结构简单,既可以用于二值时序电路中也可以用于多值时序电路中。模拟结果表明,本文设计的四边沿触发器具有正确的逻辑功能且能有效地降低系统功耗。 相似文献
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By analysing the difficulty of previous flip-flops with a high radix, this paper proposes a logic design scheme with two presetting inputs. The circuit of a quaternary CMOS flip-flop is designed by using the transmission function theory. The result shows that its structure is simpler and its processing speed is higher than that of two binary flip-flops which store the equal information. 相似文献
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为了探索多输入时序逻辑电路的简便实现方法,介绍了基于数据选择器和D触发器的多输入时序逻辑电路设计技术。即将D触发器和数据选择器进行组合,用触发器的现态作为数据选择器选择输入变量、数据选择器的输出函数作为触发器的D输入信号,构成既有存储功能又有数据选择功能的多输入端时序网络。由触发器的现态选择输入变量、所选择的输入变量决定触发器的次态转换方向。该方法适合实现互斥多变量时序逻辑电路,且在设计过程中不需要进行函数化简。 相似文献
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本文应用限幅电压开关理论设计了两种主从型nMOS四值触发器。这砦触发器具有双端预置能力和双轨互补输出。通过采用JKLM型触发器对十六进制加法计数器和十进制加法计数器的设计实例证明了这些触发器能有效地用于四值时序电路的设计。 相似文献
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Hossain R. Wronski L.D. Albicki A. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》1994,2(2):261-265
In this paper we study the power savings possible using double edge triggered (DET), instead of, conventional single edge triggered (SET) flip-flops. We begin the paper by introducing a set of novel D-type double edge triggered flip-flops which can be implemented with fewer transistors than any previous design. The power dissipation in these flip-flops and single edge triggered flip-flops is compared via architectural level studies, analytical considerations and simulations. The analysis includes an implementation independent study on the effect of input sequences in the energy dissipation of single and double edge triggered flip-flops. The system level energy savings possible by using registers consisting of double edge triggered flip-flops, instead of single edge triggered flip-flops, is subsequently explored. The results are extremely encouraging, indicating that double edge triggered flip-flops are capable of significant energy savings, for only a small overhead in complexity 相似文献
17.
《Solid-State Circuits, IEEE Journal of》1984,19(2):254-259
The circuit is constructed with two cross-coupled DC flip-flops, resulting in a square-wave output signal without an external special clock signal. The circuit has been fabricated and its operating margin has been examined. An improved circuit for a wider operating margin is proposed and discussed. 相似文献
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DESIGN OF nMOS QUATERNARY FLIP-FLOPS AND THEIR APPLICATIONS 总被引:2,自引:0,他引:2
By using the theory of clipping voltage-switches, two kinds of master/slave nMOS quaternary flip-flops are designed. These
flip-flops have the capability of two-input presetting and double-rail complementary outputs. It is shown that these flip-flops
are effectively suitable to design nMOS quaternary sequential circuits by designing two examples of hexadecimal up-counter
and decimal up-counter.
Supported by Youth Science & Technology Foundation of Ningbo Science & Technology Commission and by Natural Science Foundation
of Zhejiang Province, China 相似文献
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Integration of partial scan and built-in self-test 总被引:2,自引:0,他引:2
Partial-Scan based Built-In Self-Test (PSBIST) is a versatile Design for Testability (DFT) scheme, which employs pseudo-random BIST at all levels of test to achieve fault coverages greater than 98% on average, and supports deterministic partial scan at the IC level to achieve nearly 100% fault coverage. PSBIST builds its BIST capability on top a partial scan structure by adding a test pattern generator, an output data compactor, and a PSBIST controller in a way similar to that of deriving a full scan BIST from a full scan structure. However, to make the scheme effective, there is a minimum requirement regarding which flip-flops in the circuit should be replaced by scan flip-flops and/or initialization flip-flops. In addition, test arents are usually added to boost the fault coverage to the range of 95 to 100 percent. These test points are selected based on a novel probabilistic testability measure, which can be computed extremely fast for a special class of circuits. This ciass of circuits is precisely the type of circuits that we obtain after replacing some of the flip-flops.withscan and/or initilization flip-flops. The testability measure is also used for a very useful quick estimation of the fault coverage right after the selection of sean flip-flops, even before the circuit is modified to incorporate PSBIST capability. While PSBIST provides all the benefits of BIST, it incurs lower area overhead and performance degradation than full scan. The area overhead is further reduced when the boundary scan cells are reconfigured for BIST usage. 相似文献
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《Solid-State Circuits, IEEE Journal of》1984,19(4):480-484
The circuit is constructed with two cross-coupled DC flip-flops, resulting in a square wave output signal without any external special clock signal. The circuit configuration and operating principle are described. The circuit has been experimentally fabricated and its operating margin has been examined. The analysis successfully explains the experimental results. 相似文献