软判决Fano译码算法的FPGA实现

Fano译码算法一般采用软件实现,受制于计算机的结构,译码速度较慢。为大幅度提高译码速度,研究软判决Fano译码算法的全硬件实现方案,即采用AHDL（Ahera硬件描述语言）设计软判决Fano译码译码器,使用FPGA（现场可编程门阵列）予以实现。介绍了总体结构,重点描述构建Fano软判决译码器关键部件——状态机的设计。实测数据表明,在相同时钟频率条件下,软判决Fano译码算法的全硬件实现比软件方案至少快20倍。     

LDPC编译码算法分析

低密度奇偶校验(LDPC)码是一种线性分组码,其纠错能力可以接近香农极限。针对LDPC码的编译码问题,分析了校验矩阵的构造方法。给出了LDPC码的编码算法以及算法的实现结构。分析了基于软判决的置信传播(BP)译码算法,并给出了可以进一步降低计算复杂度的简化译码方法。通过仿真对比了不同的译码算法在高斯信道下的译码性能。     

MIMO系统中STTC译码的一种改进型算法

本文对MIMO系统中用于STTC编码器的VA译码算法进行了改进,建立了节点度量的递推方程,并给出了分枝转移的度量方法。改进后的VA算法适用于已经估计出MIMO系统中信道转移阵的条件下。相比于标准的STTC译码算法,改进后的算法可以在一根接收天线上独立进行,并且节点度量可以通过递推方程进行累积。当多根天线独立译码后,可以进一步进行后续比较以再次降低误码率。仿真结果显示：改进VA在比特误码性能上与标准VA算法接近,但是在分段度量计算时收敛速度要远快于标准VA。     

MIM0系统中STTC译码的一种改进型算法

本文对MIMO系统中用于STTC编码器的VA译码算法进行了改进,建立了节点度量的递推方程,并给出了分枝转移的度量方法.改进后的VA算法适用于已经估计出MIMO系统中信道转移阵的条件下.相比于标准的STTC译码算法,改进后的算法可以在一根接收天线上独立进行,并且节点度量可以通过递推方程进行累积.当多根天线独立译码后,可以进一步进行后续比较以再次降低误码率.仿真结果显示:改进VA在比特误码性能上与标准VA算法接近,但是在分段度量计算时收敛速度要远快于标准VA.     

带禁止符号的算术码序列译码算法

如何有效检测错误以及如何构造编码树型结构是算术码抗误码性能研究的两个关键性问题。文章利用多禁止符号实现快速、高效检错,并结合删减编码树型结构分支点的序列译码算法,在降低序列译码复杂度的同时提高了算术码的抗误码性能。仿真结果表明,在同样误包率的条件下,多禁止符号的抗误码性能优于单禁止符号0．5dB。而且在数据包长固定的条件下,禁止符号冗余度的选择和序列译码堆栈空间大小密切相关,联合优化后可以达到性能最优。     

基于矩阵分块的LDPC码快速编码结构研究

低密度奇偶校验(LDPC)码由于具有接近香农限的性能和高速并行的译码结构而成为研究热点。然而,当码长很长时,编译码器的硬件实现变得很困难。文章从编译码实际实现的角度出发,提出一种基于分块的LDPC码下三角形校验矩阵结构,降低了编译码复杂度,不仅可以实现线性时间编码,同时还可以实现部分并行译码。仿真结果表明,具有这种结构的LDPC码和随机构造的LDPC码相比具有同样好的纠错性能。     

一种适用于BICM-ID系统的迭代载波同步算法

在比特交织编码调制迭代译码(BICM-ID)系统中,针对低信噪比条件下传统的同步算法对频偏和相差估计精度较低的问题,提出了一种码辅助的迭代载波同步算法。该算法基于最大期望(EM)算法,并在此基础上加以改进,利用译码器输出的软信息,迭代的在载波同步和译码之间相互交换信息,实现同步和译码的联合处理。仿真结果表明,在译码器收敛的允许范围之内,提出的算法能够大幅提高同步参数的估计精度,在迭代次数达到8次时,BICM-ID系统的误比特率性能基本接近理想同步条件下的译码性能。     

Turbo高速编译码技术研究

本文提出了一种高速Turbo编译码方法。从算法改进和结构改进技术两方面进行研究,以期解决现有译码算法难以实现高速这一问题。在结构改进技术方面,采用分块思想,将分量编码器分成两块并行处理,速度提高一倍;在算法改进技术方面,一方面针对目前存在的复杂度较低、性能次优的Radix-4 Max-Log-MAP译码算法,通过尺度因子的补偿,得到了译码性能较好的SF-Max-Log-MAP算法。另一方面采用了HDA停止迭代准则,有效地减少了译码时延。     

一种性能优越的Turbo码SOVA译码算法

MAP译码算法性能上是最优的,但是其复杂度也是十分高的,影响了硬件的实现,介绍了一种性能上接近于MAP译码算法,复杂度上有明显减少的译码算法,并且对其进行了完善,仿真结果表明对于二进制Turbo码,改进后的译码算法与MAP算法的译码性能更为接近。     

基于GPU的RS码并行译码算法研究

针对RS码硬件译码器中常用的BMA译码算法并行性较差,导致译码延迟较大和译码速率较低的问题,研究了RS码的高速并行译码算法及其软件实现方式,设计和实现了一种基于GPU的RS码并行译码算法cu PGZ。实验结果表明,对CCSDS建议的RS(255,223)码,在128 bits错误的情况下,cu PGZ可以达到590 Mbps的最大译码速率以及0.5 ms的最小译码延迟,与BMA算法的GPU实现相比,译码速率提高1倍,译码延迟降低为1/60。实际工程应用表明,cu PGZ能够满足实际测控数传的信道译码要求。     

新的降低复杂度的Turbo均衡

Turbo均衡是一种通过反复均衡和信道译码来提高接收性能的迭代接收机算法。通常的Turbo均衡算法采用均衡与软输出译码的迭代运算，由于均衡和译码的重复计算，使得复杂度大大提高。文中提出了2种降低复杂度的Turbo均衡器：第一种采用软判决维特比译码，第二种采用软输入硬输出的维特比译码。通过仿真表明，这2种算法在几乎没有损失接收性能的情况下，大大降低了计算复杂度，并且第二种的性能要好于第一种。     

Systematic analysis of the decoding delay in multiview video

We present a framework for the analysis of the decoding delay in multiview video coding (MVC). We show that in real-time applications, an accurate estimation of the decoding delay is essential to achieve a minimum communication latency. As opposed to single-view codecs, the complexity of the multiview prediction structure and the parallel decoding of several views requires a systematic analysis of this decoding delay, which we solve using graph theory and a model of the decoder hardware architecture. Our framework assumes a decoder implementation in general purpose multi-core processors with multi-threading capabilities. For this hardware model, we show that frame processing times depend on the computational load of the decoder and we provide an iterative algorithm to compute jointly frame processing times and decoding delay. Finally, we show that decoding delay analysis can be applied to design decoders with the objective of minimizing the communication latency of the MVC system.     

System Architecture and Implementation of MIMO Sphere Decoders on FPGA

Multiple-input-multiple-output (MIMO) systems use multiple antennas in both transmitter and receiver ends for higher spectrum efficiency. The hardware implementation of MIMO detection becomes a challenging task as the computational complexity increases. This paper presents the architectures and implementations of two typical sphere decoding algorithms, including the Viterbo-Boutros (VB) algorithm and the Schnorr-Euchner (SE) algorithm. Hardware/software codesign technique is applied to partition the decoding algorithm on a single field-programmable gate array (FPGA) device. Three levels of parallelism are explored to improve the decoding rate: the concurrent execution of the channel matrix preprocessing on an embedded processor and the decoding functions on customized hardware modules, the parallel decoding of real/imaginary parts for complex constellation, and the concurrent execution of multiple steps during the closest lattice point search. The decoders for a 4times4 MIMO system with 16-QAM modulation are prototyped on a Xilinx XC2VP30 FPGA device with a MicroBlaze soft core processor. The hardware prototypes of the SE and VB algorithms show that they support up to 81.5 and 36.1 Mb/s data rates at 20 dB signal-to-noise ratio, which are about 22 and 97 times faster than their respective implementations in a digital signal processor.     

H.264和AVS多模视频解码器中运动矢量预测的硬件实现

文章比较了H.264和AVS两个标准在运动补偿中运动矢量预测算法的差别,提出了一种实现H.264中主档次（main profile）下的第4级别（level 4）和AVS中的基准档次面向高清应用时运动矢量预测复用的硬件结构.提出了一种新颖的缓存管理更新机制,极限情况下用于运动矢量的片上缓存大小减少了75%.用FPGA验证结果表明资源占用情况是单独实现AVS的2.3倍,是单独同时实现两个标准的70%.能实现对1080i 30Hz高清图像实时解码.     

An efficient VLSI architecture for CBAC of AVS HDTV decoder

Context-based Binary Arithmetic Coding (CBAC) is a normative part of the newest X Profile of Advanced Audio Video coding Standard (AVS). This paper presents an efficient VLSI architecture for CBAC decoding in AVS. Compared with CBAC in H.264/AVC, the simpler binarization methods and context selection schemes are adopted in AVS. In order to avoid the slow multiplications, the traditional arithmetic calculation is transformed to the logarithm domain. Although these features can obtain better balance between the compression gain and implementation cost, it still brings huge challenge for high-throughput implementation. The fact that current bin decoding depends on previous bin results in long latency and limits overall system performance. In this paper, we present a software–hardware co-design by using bin distribution feature. A novel pipeline-based architecture is proposed where the arithmetic decoding engine works in parallel with the context maintainer. A finite state machine (FSM) is used to control the decoding procedure flexibly and the context scheduling is organized carefully to minimize the access times of context RAMs. In addition, the critical path is optimized for the timing. The proposed implementation can work at 150 MHz and achieve the real-time AVS CBAC decoding for 1080i HDTV video.     

Flexible and Expandable Speech Recognition Hardware with Weighted Finite State Transducers

Hardware implementation of speech recognition can not only accelerate decoding speed for real-time processing but also reduce the power consumption. Recently the weighted finite state transducer (WFST) has emerged as a major recognition network representation because it reduces the algorithmic complexity of decoding procedures by applying many optimizations on the network in offline. However, hardware implementation of continuous speech recognition (CSR) with the WFST network is challenging, mainly because Viterbi search should traverse a large sized network with limited hardware resources. This paper presents two hardware speech recognition systems with the WFST network. The first one, which is called the SRAM-oriented system, utilizes the internal SRAM as a hash table to efficiently manage active working set. This system is flexible because it can easily accommodate different speech recognition tasks as long as the SRAM space is allowed. For easy expansion, we also propose the DRAM-oriented system where the active working set is stored in the external DRAM. To hide long latency of DRAM access, a split DRAM hash table is employed, which stores active working set in the opened rows of DRAM to reduce the number of row misses. Experimental results show that the SRAM-oriented system decodes the 5k-word CSR task 4.93 times faster than real-time, while the DRAM-oriented system runs 4.48 times faster than real-time with only about a half SRAM capacity.     

一种基于分层译码和Min-max的多进制LDPC码译码算法

该文在现有译码算法的基础上提出一种高效的非二进制低密度奇偶校验码(NB-LDPC)译码方法,充分利用了分层译码算法与Min-max算法的优点,不但译码复杂度低、需要的存储空间小,而且可将译码速度提高一倍。应用该算法,对一种定义在GF(25)上的(620,509)码进行了仿真。该码的仿真结果表明：在相同误码率下,该文译码算法所需最大迭代次数仅为Zhang的算法(2011)的45%。     

数字广播接收终端TPEG解码功能的软件实现

本文研究在数字广播接收终端上利用MCU实现TPEG的软件解码,包括TPEG帧数据的解码实现和TPEG内容的解码实现,完成了TPEG信息的实时接收和正确解码。     

Scarce-state-transition syndrome-former error-trellis decoding of(n,n-1) convolutional codes

A novel scarce-state-transition (SST) type trellis decoding system for (n,n-1) convolutional codes with coherent BPSK signals is proposed. The new system retains the same number of binary comparisons as the syndrome-former trellis decoding technique. Like the original SST-type encoder trellis technique, the proposed system is also suitable for CMOS VLSI implementation. A combination of the two techniques results in a less complex and low power consumption decoding system