1/f noise in HEMT-type GaAs FETs at low drain bias

The 1/f noise in HEMT-type GaAs FETs is calculated for low drain bias. It comes from 1/f type fluctuations in the series resistances R_S and R_D on the source and drain side of the channel, respectively, and 1/f type fluctuations in the device resistance R_A. It is assumed that the latter is due to mobility fluctuation noise and that the former may either be due to number fluctuations or mobility fluctuations. It is demonstrated how one can experimentally discriminate between the two noise sources.     

A physics-based MOSFET noise model for circuit simulators

Discussed is a physics-based MOSFET noise model that can accurately predict the noise characteristics over the linear, saturation, and subthreshold operating regions but which is simple enough to be implemented in any general-purpose circuit simulator. Expressions for the flicker noise power are derived on the basis of a theory that incorporates both the oxide-trap-induced carrier number and correlated surface mobility fluctuation mechanisms. The model is applicable to long-channel, as well as submicron n- and p-channel MOSFETs fabricated by different technologies, and all the model parameters can be easily extracted from routine I-V and noise measurements     

A model for low frequency excess noise in Si-JFETs at low bias

Spectral analyses of the fluctuating drain-source voltages in n- and p-channel Si-JFETs at low bias conditions revealed generation-recombination (G-R) noise over a temperature range of 150–300 K in both types of devices. The corner frequencies f_C and the low frequency plateau values of the Lorentzian spectra were used to study the nature of the noise. In the n-channel device, f_C was strongly temperature dependent; an activation energy, E_C − E_T, of approximately 0.36 eV was obtained from the Arrhenius plot. For the p-channel device, a much higher corner frequency of 20–30 kHz was measured. Based on the experimental results we are led to consider a model for low frequency noise in JFETs that accounts for fluctuations in the channel thickness, and the correlated fluctuations in the number and the mobility of carriers. The relative significance of the three noise mechanisms was found to depend strongly on temperature, doping concentrations, device dimensions, and the energy level of the recombination centers.     

A broadband PHEMT MMIC distributed doubler using high-pass drain line topology

A broadband frequency doubler, based on distributed amplifier techniques, has been designed to operate from 11 to 21 GHz. In order to reject the fundamental signal over a broadband frequency range, the conventional low-pass drain line structure was replaced with the high-pass structure. This topology can suppress fundamental signals over broadband without any balanced structure so that the chip size can be more compact. Measured conversion losses of better than 10 dB from 11 to 21 GHz input frequencies are achieved with fundamental signal rejection better than 12 dB. To the best of our knowledge, this is the first demonstration of distributed doubler using the high-pass drain line topology.     

A functional GaAs FET noise model

It is the purpose of this paper to develop a theory upon which the design of low noise FET amplifiers can be based. This is not a fundamenta model of the noise mechanisms in GaAs FET's, but rather, an endeavor to relate physically measurable device capacitances and resistances to the device noise figure and optimum noise source impedance. I will be shown that the noise performance of an FET can be adequately described by two uncorrelated noise sources. One, at the input of the FET, is the thermal noise generated in the various resis, tances in the gate-source loop. This noise source is frequency dependent and it can be calculated from the equivalent circuit of the FET. The second noise source, in the Output of the FET, is frequency independent, and not recognizably related to any measured parameters. This output nise is a function of drain current and voltage. The decomposition of the FET noise into two uncorrelated sources simplifies the design of broad-band low noise amplifiers. Once the equivalent circuit of a device and its noise figure at one frequency are known, the optimum noise source impedance and noise figure over a broad range of frequencies may be calculated. For the device designer this model also may be helpful in balancing input-output noise tradeoffs.     

A submicron PHEMT nonlinear model suitable for RFID low current amplifier design

A new nonlinear submicron double heterostructure PHEMT model is presented that is suitable for low current application. It is found that this model accurately predicts the bias-dependent S-parameters for PHEMT up to 40?GHz, and good agreement is obtained between simulated and measured results for 2.45?GHz and 5.8?GHz amplifiers.     

1/f noise in MODFETs at low drain bias

The 1/f noise in normally-on MODFETs biased at low drain voltages is investigated. The experimentally observed relative noise in the drain current S_I/I² versus the effective gate voltage V_G=V_GS-V_off shows three regions which are explained. The observed dependencies are S_I/I²∝V_G ^m with the exponents m=-1, -3, 0 with increasing values of V_G. The model explains m =-1 as the region where the resistance and the 1/f noise stem from the 2-D electron gas under the gate electrode; the region with m=0 at large V_G or V_GS≅0 is due to the dominant contribution of the series resistance. In the region at intermediate V_G , m=-3, the 1/f noise stems from the channel under the gate electrode, and the drain-source resistance is already dominated by the series resistance     

High drain current-voltage product of submicrometer-gateion-implanted GaAs MESFET's for millimeter-wave operation

Ion-implanted GaAs MESFETs with gate lengths of 0.3 and 0.5 μm have been fabricated using optical lithography. The devices with 0.3- and 0.5-μm gate lengths exhibit extrinsic transconductances, at zero gate bias, of 200 and 180 mS/mm at drain currents of 400 and 420 mA/mm, respectively. The gate-to-drain diode characteristics of these two different gate-length devices show similar breakdown voltages of 13-15 V. From S-parameter measurements, current-gain cutoff frequencies, f _ts, of 56 and 30 GHz are obtained for 0.3- and 0.5-μm gate-length devices, respectively. The high drain current-voltage product and the microwave performance indicate that ion-implanted technology has the potential to be used to manufacture power devices for millimeter-wave applications     

DC-40 GHz光通信系统用GaAs PHEMT驱动放大器。

利用0.2μmGaAsPHEMT工艺研制了40Gb/s光通信系统中的光调制器驱动放大器。该放大器芯片采用有源偏置的七级分布放大器结构,工作带宽达到40GHz,输入输出反射损耗约-10dB,功率增益14dB,功耗700mW,最大电压输出幅度达到7V。两级芯片级连后,功率增益约27dB,在40Gbit/s速率下得到清晰的眼图。     

Analytical bias dependent noise model for InP HEMT's

A practical device model for both high frequency small signal and noise behavior of InP-HEMT's depending on both gate and drain voltage has been developed. The model is based on the two-piece linear approximation using charge control and saturation velocity models. Combining large signal model and analytical expressions for the noise source parameter P, R, and C, an analytical bias-dependent noise model can be obtained. For implementation into high frequency simulation software, the exact calculated bias dependence was mathematically fitted by elementary functions. It could be shown that lowest noise is observed when the drain current for maximum gain is reduced to a third while the drain voltage is reduced to the start of the saturation region V_ds =0.6 V. Modeling scaling effects of the noise behavior shows that lowest noise is observed for a gate width of 1×40 μm. Multi-finger layouts are preferable for gate widths above 70 μm. Furthermore it is shown, that the optimum width of each finger decreases with the number of fingers     

A physics-based three-dimensional model for distributed feedbacklaser diodes

A comprehensive physics-based three-dimensional (3-D) model for distributed feedback (DFB) lasers is developed and presented. The model considers self-consistently optical confinement, carrier transport and heat transfer over the two-dimensional (2-D) cross section. It also accounts for the longitudinal spatial hole-burning effect along the laser cavity. A rigorous optical gain model is incorporated into the 3-D model. A number of novel techniques are used in implementation of the model for efficient simulation of de and ac performance. The simulator runs efficiently on a personal computer and can be incorporated as part of the computer-aided engineering tools for the design and analysis of DFB lasers     

A fully on-chip ESD protection UWB-band low noise amplifier using GaAs enhancement-mode dual-gate pHEMT technology

This paper presents the development of a novel ESD protected wideband low noise amplifier (LNA) using enhancement-mode (E-mode) pHEMT dual-gate clamps. The proposed novel clamp possesses a low on-state resistance, uniform parasitic capacitance, and flexibility to adjust the trigger voltage for different ESD applications. Implementation of the LNA demonstrates that RF performance can be maintained after human body mode (HBM) ESD test while at the same time endure more than +2.5 kV and −2 kV HBM ESD stress voltage. In addition, the incorporated clamps use a fewer number of diodes than the conventional diode stacks, thereby making it size efficient and low effort impedance matching co-design which allow this approach to be an attractive solution for ESD protection.     

A new physics-based model for time-dependent Dielectric breakdown

A physics-based model for time dependent dielectric breakdown has been developed, and is presented along with test data obtained by NIST on oxides provided by National Semiconductor. Testing included fields from 5.4 MV/cm to 12.7 MV/cm, and temperatures ranging from 60 °C to 400 °C. The physics, mathematical model, and test data, all confirm a linear, rather than an inverse field dependence. The primary influence on oxide breakdown was determined to be due to the dipole interaction energy of the field with the orientation of the molecular dipoles in the dielectric. The resultant failure mechanism is shown to be the formation and coalescence of vacancy defects, similar to that proposed by Dumin et al.     

A 68% PAE, GaAs power MESFET operating at 2.3 V drain bias for lowdistortion power applications

A high-efficient GaAs power metal semiconductor field effect transistor operating at a drain voltage of 2.3 V has been developed for low distortion power applications. The device has been fabricated on an epitaxial layer with a high-low doped structure grown by molecular beam epitaxy. The MESFET with a gate length of 0.8 μm and a total gate width of 21.16 mm showed a maximum drain current of 5.9 A at V_gs =0.5 V, a knee voltage of 1.0 V and a gate-to-drain breakdown voltage of 28 V. The MESFET tested at a 2.3 V drain bias and a 900 MHz operation frequency displayed the best power-added efficiency of 68% with an output power of 31.3 dBm. The associate power gain at 20 dBm input power and the linear gain were 11.3 dB and 16.0 dB, respectively. The power characteristics of the device operating under a bias of 2 V exhibit power-added efficiency of 67% and output power of 30.1 dBm at an input power of 20 dBm. Two tone test measured at 900.00 MHz and 900.03 MHz shows that 3rd-order intermodulation and power-added efficiency at an output power of 27 dBm were -30.6 dBc and 36%, respectively, which are good for CDMA digital applications. A third-order intercept point and a linearity figure-of-merit were measured to be 49.5 dBm and 53.8, respectively     

Supression of drain conductance transients, drain current oscillations, and low-frequency generation—Recombination noise in GaAs FET's using buried channels

The drain conductance transients of buried-channel MESFET's fabricated on GaAs are compared with conductance transients of regular MESFET's. The buried-channel MESFET's are shown to be essentially free of drain transients in comparison to the regularly fabricated MESFET's. In addition, the buried-channel FET's are shown to be free of oscillations in the drain current, which have been found in FET's manufactured by common techniques.     

Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.     

A new and improved physics-based model for MOS transistors

An improved MOS device model is derived based upon a first-order model for the dependency of MOS surface mobility on surface field and lateral drain field. A comparison with experimental data shows that a consistent set of physical parameters can be used to describe both long-channel nMOS devices and short-channel devices. The model can form the basis for improved compact MOS models for circuit analysis.     

A new meshing criterion for the equivalent thermal analysis of GaAs PHEMT MMICs

In this paper, a new meshing criterion for the equivalent thermal analysis of GaAs PHEMT MMICs (Monolithic microwave integrated circuit) is proposed. Based on the meshing criterion, an equivalent thermal model of GaAs PHEMTs with remarkably reduced mesh complexity is established, and the simplification of both layout pattern and vias of MMICs are performed. Theoretical analysis is applied for the calibration of the equivalent thermal model. Assisted by the meshing criterion, chip-level simulators are capable to obtain the peak temperature of MMICs without using averaging approximations, and achieve considerably high simulation accuracy. As examples, two MMIC power amplifiers are designed and implemented using GaAs PHEMT process. Thermal simulation and measurement results obtained with ANSYS ICEPAK and infrared thermography, respectively, show high consistency. The proposed meshing criterion can be applied to improve the accuracy of thermal analysis of MMICs, and the obtained precise peak temperature can be used to effectively assess the power threshold of the designed amplifiers in reliability tests.     

A joint physics-based statistical deformable model for multimodalbrain image analysis

A probabilistic deformable model for the representation of multiple brain structures is described. The statistically learned deformable model represents the relative location of different anatomical surfaces in brain magnetic resonance images (MRIs) and accommodates their significant variability across different individuals. The surfaces of each anatomical structure are parameterized by the amplitudes of the vibration modes of a deformable spherical mesh. For a given MRI in the training set, a vector containing the largest vibration modes describing the different deformable surfaces is created. This random vector is statistically constrained by retaining the most significant variation modes of its Karhunen-Loève expansion on the training population. By these means, the conjunction of surfaces are deformed according to the anatomical variability observed in the training set. Two applications of the joint probabilistic deformable model are presented: isolation of the brain from MRI using the probabilistic constraints embedded in the model and deformable model-based registration of three-dimensional multimodal (magnetic resonance/single photon emission computed tomography) brain images without removing nonbrain structures. The multi-object deformable model may be considered as a first step toward the development of a general purpose probabilistic anatomical atlas of the brain.