105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105 nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart Cut^TM process to fabricate 200 mm GeOI wafers with Ge thickness down to 60–80 nm. A full Si MOS compatible pMOSFET process was implemented with HfO₂/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (I_ON, I_OFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μ_h ～ 250 cm²/V/s, I_ON = 436 μA/μm for L_G = 105 nm), and OFF current densities comparable or better than those reported in the literature.     

Activation level in boron-doped thin germanium-on-insulator (GeOI): Extraction method and impact of mobility

We hereby present a non-destructive method for extracting the activation level on boron-doped germanium-on-insulator (GeOI) wafers, with a discussion on the impact of the hole mobility model. This method combines Monte Carlo boron profile simulations with optical Ge layer thickness T_Ge and electrical sheet resistance R_sh measurements. As B atoms are known not to diffuse in Ge for the usual activation temperatures (<800 °C), we can assume that the as-implanted dopant profile remains unchanged after annealing (no modelling of boron diffusion required). We highlight that the knowledge of the hole mobility dependence on activated impurities concentration in Ge is of paramount importance. Several experimental and theoretical models are available in the literature. After relative validity assessments, all of them have been implemented for extraction and unfortunately yield different values scattered over nearly one decade. Still, the lower-bound concentration 2.7×10¹⁹ cm⁻³ is in the range of the state-of-the-art values for B-implanted crystalline Ge and has proven suitable for functional GeOI pMOSFET demonstration.     

A threshold-voltage model of SiGe-channel pMOSFET without Si cap layer

An analytical model on the threshold voltage of SiGe-channel pMOSFET with high-κ gate dielectric is developed by solving the Poisson’s equation. Energy-band offset induced by SiGe strained layer, short-channel effect and drain-induced barrier lowering effect are taken into account in the model. To evaluate the validity of the model, simulated results are compared with experimental data, and good agreements are obtained. This model can be used for the design of SiGe-channel pMOSFET, thus determining its optimal parameters.     

Integration of Germanium-on-Insulator and Silicon MOSFETs on a Silicon Substrate

The monolithic integration of germanium-on-insulator (GeOI) p-MOSFETs with silicon n-MOSFETs on a silicon substrate is demonstrated. The GeOI p-MOSFETs are fabricated on the oxide for silicon device isolation based on the newly developed rapid-melt-growth method. CMOS inverters consisting of the silicon n-MOSFET and GeOI p-MOSFET were obtained, and the measured results show that the processing of high-performance GeOI devices is compatible with bulk-silicon technology     

Impact of single pMOSFET dielectric degradation on NAND circuit performance

Degradation of CMOS NAND logic circuits resulting from dielectric degradation of a single pMOSFET using constant voltage stress has been examined by means of a switch matrix technique. As a result, the NAND gate rise time increases by greater than 65%, which may lead to timing errors in high frequency digital circuits. In addition, the NAND gate DC switching point voltage shifts by nearly 11% which may be of consequence for analog or mixed signal applications. Experimental results for the degraded pMOSFET reveal a decrease in drive current by approximately 43%. There is also an increase in threshold voltage by 23%, a decrease in source-to-drain conductance of 30%, and an increase in channel resistance of about 44%. A linear relationship between the degradation of the pMOSFET channel resistance and the increase in NAND gate rise time is demonstrated, thereby providing experimental evidence of the impact of a single degraded pMOSFET on NAND circuit performance.     

A comparative 1/f noise study of GeOI wafers obtained by the Ge enrichment technique and the Smart Cut technology

This paper presents an experimental investigation of Low-frequency Noise (LFN) measurements on Germanium-On-Insulator (GeOI) PMOS transistors processed on different wafers. The wafers are obtained by Ge enrichment technique and by Smart Cut™ technology. The slow oxide trap densities of back interface are used as a figure of merit to evaluate the process. The Smart Cut™ process is evaluated by studying GeOI pMOSFETs, and the enrichment process by studying Si_1−xGe_x (x = 25% and 35%) pMOSFETs. The buried oxide is used as a back gate for experimental purposes. The extracted values are of the same order of magnitude for both processes and are close to those of state of art buried oxide SiO₂/Si interfaces, demonstrating that both the Smart Cut™ and enrichment techniques produce equally good quality interfaces.     

Fabrication of Thick Germanium-on-Insulator (GeOI) Substrates

Fabrication of germanium-on-insulator (GeOI) substrates with a 160-nm-thick Ge layer is reported. Such thick GeOI substrates were fabricated by thermal intermixing and subsequent condensation of epitaxially grown high-Ge- content SiGe on Si-on-insulator (SOI) substrates. Transmission electron microscopy revealed that the GeOI layer was single crystalline. The high-resolution rocking curve and reciprocal lattice map obtained from X-ray diffraction measurements showed a relaxed GeOI. This was further confirmed by micro-Raman measurements, where the Ge-Ge optical phonon peak shift represented a nearly strain-free Ge layer. Using this methodology, GeOI substrates with Ge layers 120–160 nm thick have been fabricated with thickness variations of less than 4 nm across 200 mm wafers.     

A New Method to Extract Bulk Carrier Mobility in Germanium-on-Insulator

A new method is presented to extract bulk carrier mobility of germanium-on-insulator (GeOI) films based on the data from the depletion mode of four-point probe pseudo-MOSFET measurement. Analytical models of the conductance in depletion region and related parameter extraction procedures are presented. This method is validated with both GeOI and silicon-on-insulator substrates prepared by layer transfer.     

Polarity dependent gate tunneling currents in dual-gate CMOSFETs

Polarity dependence of the gate tunneling current in dual-gate CMOSFETs is studied over a gate oxide range of 2-6 nm. It is shown that, when measured in accumulation, the I_g versus V_g characteristics for the p⁺/pMOSFET are essentially identical to those for the n⁺/nMOSFET; however, when measured in inversion, the p⁺/pMOSFET exhibits much lower gate current for the same |V_g|. This polarity dependence is explained by the difference in the supply of the tunneling electrons. The carrier transport processes in p⁺/pMOSFET biased in inversion are discussed in detail. Three tunneling processes are considered: (1) valence band hole tunneling from the Si substrate; (2) valence band electron tunneling from the p⁺-polysilicon gate; and (3) conduction band electron tunneling from the p⁺-polysilicon gate. The results indicate that all three contribute to the gate tunneling current in an inverted p⁺/pMOSFET, with one of them dominating in a certain voltage range     

The Ge condensation technique: A solution for planar SOI/GeOI co-integration for advanced CMOS technologies?

This paper presents a general study on the germanium (Ge) condensation technique to assess its potential, issues and applications for advanced metal oxide semiconductor field effect transistor (MOSFET) technologies. The interest in such process for fabrication of ultrathin germanium on insulator (GeOI) layers for fully depleted GeOI MOSFETs application is first described. We highlight the impact of initial silicon on insulator (SOI) substrates uniformity on the process, determined as the key parameter to be improved. Next, a global procedure is described for MOSFETs integration on Ge layers grown on 75% Ge-enriched silicon germanium on insulator (SGOI) substrates obtained by the Ge condensation technique. A third section reviews the different local Ge condensation techniques for fabrication of SOI–GeOI hybrid substrates. Interests of such substrates for SOI–GeOI planar co-integration either at the microprocessor, at the cell or at the transistor level will be discussed. Finally, the fabrication of a first 50-nm-thick SOI–GeOI hybrid substrate is described.     

Dynamic NBTI lifetime model for inverter-like waveform

In this paper, a simple yet accurate NBTI lifetime model has been formulated for a pMOSFET working in dynamic AC condition. The model is based on detailed dynamic NBTI (DNBTI) characterization for inverter-like waveform stress. The fitting parameters of the model can be readily obtained from the calibration of one-time DNBTI lifetime measurement for a small set of frequency/duty cycle matrix. After that, it can be employed to estimate the NBTI lifetime for a pMOSFET under any AC operating condition with reasonably good agreement. Additionally, it is shown that the lifetime enhancement by a shorter duty cycle is even more significant than that by a higher frequency. The application of the model to the lifetime estimation of circuits with multiple operation modes is also discussed.     

Characterization of impact of process options in Germanium-On-Insulator (GeOI) high-k & metal gate pMOSFETs by low-frequency noise

The impact of technological processes on Germanium-On-Insulator (GeOI) noise performance is studied. We present an experimental investigation of low-frequency noise (LFN) measurements carried out on (GeOI) PMOS transistors with different process splits. The front gate is composed of a SiO₂/HfO₂ stack with a TiN metal gate electrode. The result is an aggressively reduced equivalent oxide thickness (EOT) of 1.8 nm. The buried oxide is used as a back gate for experimental purposes. Front and back gate interfaces are characterized and the slow oxide trap densities are extracted. The obtained values are comprised between 5 × 10¹⁷ and 8 × 10¹⁸ cm⁻³eV⁻¹. No correlation between front interface trap density and front interface mobility is observed. We underline a strong correlation between rear interface trap density and rear interface mobility degradation. The impact of Ge film thickness is equally studied. For thin films, the measured drain-current noise spectral density shows that LFN can be described by the carrier fluctuation model from weak to strong inversion. For thicker film devices, in weak inversion the LFN can be described by the mobility fluctuation model and in strong inversion the LFN is described by the carrier fluctuation model. The α_H parameter for these devices is 1.2 × 10⁻³. These results are significant for the future development of GeOI technologies.     

Circuit level prediction of device performance degradation due to negative bias temperature stress

A circuit level methodology for predicting performance degradations due to negative bias temperature stress is developed in this paper. Degradation mechanism is discussed based on experimental observations. Then, models that consist of a threshold voltage shift and a drain current reduction are developed based on the degradation mechanism. The developed models are implemented into a compact MOSFET model so that we can directly link the local degradation of pMOSFETs’ electrical characteristics to the total circuit performances. The validity of the developed models is confirmed by the good agreement in simulated and measured results of I–V characteristics of pMOSFET in all the transistor working region before and after negative bias temperature stress. Then, circuit performance prediction is carried out for the stressed 199-stage ring oscillator on its waveform and oscillation frequency. Excellent agreements between the experimental results and predicted results are obtained.     

Effects of high field injection on the hot carrier induceddegradation of submicrometer pMOSFET's

The interaction between the hot carrier (HC) induced pMOSFET's degradation and the Fowler-Nordheim (FN) injection is investigated. It has been found that the FN injection is an efficient method to recover pMOSFET's from the HC induced degradation. This is achieved by removing some of the trapped electrons from the oxide and forming positive charges along the channel. The relative importance of these two factors is determined. The contribution of the interface states created by FN injection is negligible, since they are acceptor-like and not charged during pMOSFET's operation. The positive charges increase the lifetime of a recovered pMOSFET by requiring more electron trapping to compensate their effects on the threshold voltage. They also enhance the magnitude of punchthrough voltage. The effects of FN injection on the HC trapping kinetics are discussed. Under our experimental conditions, the new trapping sites created by FN injection are negligible, compared with the as-grown traps. When a recovered pMOSFET is stressed again, its degradation rate is not higher than that of a fresh pMOSFET. This allows FN injection to be used repeatedly and we can therefore control the pMOSFET's degradation within a given range     

Modeling of Gate Tunneling Current for Nanoscale MOSFETs with High-k Gate Stacks

介绍了一种纳米MOSFET(场效应管)栅电流的统一模型,该模型基于Schrodinger-Poisson方程自洽全量子数值解,特别适用于高k栅介质和多层高k栅介质纳米MOSFET.运用该方法计算了各种结构和材料高k介质的MOSFET栅极电流,并对pMOSFET和nMOSFET高k栅结构进行了分析比较.模拟得出栅极电流与实验结果符合,而得出的优化氮含量有待实验证实.     

高k栅介质纳米MOSFET栅电流模型

介绍了一种纳米MOSFET(场效应管)栅电流的统一模型,该模型基于Schrodinger-Poisson方程自洽全量子数值解,特别适用于高k栅介质和多层高k栅介质纳米MOSFET.运用该方法计算了各种结构和材料高k介质的MOSFET栅极电流,并对pMOSFET和nMOSFET高k栅结构进行了分析比较.模拟得出栅极电流与实验结果符合,而得出的优化氮含量有待实验证实.     

HfO_2/TaON叠层栅介质Ge pMOSFET制备及迁移率退化研究

为提高high-k/Ge界面质量,在high-k介质和Ge表面引入薄的TaON界面层。相对于没有界面层的样品,HfO2/TaON叠层栅介质Ge pMOSFET样品的空穴迁移率有显著提高,但仍小于理论预测值。利用high-k栅介质MOSFET中各种新的附加散射机制,分析了迁移率退化的原因,模型计算结果与实验结果一致。     

Polarity-dependent tunneling current and oxide breakdown indual-gate CMOSFETs

The gate tunneling leakage current in dual-gate CMOSFETs exhibits strong polarity dependence when measured in inversion, although it exhibits practically no polarity dependence when measured in accumulation. Specifically, p⁺-gate pMOSFET shows substantially lower tunneling current than n⁺-gate nMOSFET when measured in inversion. This polarity dependence arises from the difference in the supply of tunneling electrons. The polarity dependent tunneling current has a significant impact on oxide reliability measurements. For example, it gives rise to a higher T_bd value for p⁺/pMOSFET as compared to that for n⁺/nMOSFET when both are biased to inversion. Rationaless are given as to why T_bd is a better gauge than Q_bd for reliability assessment, and why nMOSFET is more prone to oxide breakdown than pMOSFET under normal operating conditions     

Fully depleted 20-nm SOI CMOSFETs with W-clad gate/source/drainlayers

Fully-depleted 20-nm SOI complementary metal-oxide-semiconductor field effect transistors (CMOSFETs) were successfully fabricated without a raised source/drain (S/D) structure, instead using low-temperature selective tungsten CVD (SWCVD) technology that can reduce the S/D series resistance. The thickness of the residual SOI layer under the W-clad layer in the S/D region was 6 nm for an nMOSFET and 9 nm for a pMOSFET. For 0.15-μm-gate CMOSFETs, the subthreshold swings were 70 and 75 mV/dec for the nMOSFET and pMOSFET, respectively. The effectiveness of SWCVD technology when applied to ultrathin SOI devices was confirmed by small Si consumption and good continuity between the W and SOI layers. We expect that the S/D series resistance can be reduced to less than 1 kΩ-μm by optimizing the S/D implantation conditions