A design methodology for high-order class-D audio amplifiers

This paper presents a design methodology for high-order class-D amplifiers, based on their similarity with sigma–delta ( $\Upsigma\Updelta$ ) modulators, for which established theory and toolboxes are available. The proposed methodology, which covers the entire design flow, from specifications to component sizing, is validated with three design examples, namely a second-order, a third-order, and a fourth-order class-D amplifier. Moreover, the third-order class-D amplifier has been integrated on silicon and characterized, further confirming the validity of the whole design flow. The achieved results demonstrate that high-order class-D amplifiers can achieve total-harmonic-distortion (THD) performance compatible with the specifications of high-end audio applications (THD  ≈ 90 dB), which would be unfeasible with conventional first-order class-D amplifiers.     

便携式音频功率放大器综述

便携式电子产品的发展推动了各种元器件的不断改进。本文以便携式音频功率放大器这一类器件的发展概况作一些介绍。     

一种高效率 PWM CMOS D类音频功率放大器

基于反馈系统的闭环结构,采用全差分前置放大和全差分反馈结构,提出了一种高效率PWM CMOS D类音频功率放大器,并采用一种具有滞回结构Rail-to-Rail比较器作为PWM比较器,以保证良好的噪声性能。整个电路基于CSMC 0.5μm CMOS工艺进行实现,最大转换效率达到90％,电源电压范围为2.5-5.5V,1kHz下的THD+N小于0.20％,电源抑制比为-75dB,空载消耗电流为2.8mA,待机电流为0.5μA,有效芯片面积为1.47mm*1.52mm,最大功率可以达到2.5W,能应用于各种高效率中小功率音频放大系统。     

A high efficiency PWM CMOS class-D audio power amplifier

Based on the difference close-loop feedback technique and the difference pre-amp, a high efficiency PWM CMOS class-D audio power amplifier is proposed. A rail-to-rail PWM comparator with window function has been embedded in the class-D audio power amplifier. Design results based on the CSMC 0.5 μm CMOS process show that the max efficiency is 90%, the PSRR is -75 dB, the power supply voltage range is 2.5-5.5 V, the THD+N in 1 kHz input frequency is less than 0.20%, the quiescent current in no load is 2.8 mA, and the shutdown current is 0.5 μA. The active area of the class-D audio power amplifier is about 1.47 × 1.52 mm2. With the good performance, the class-D audio power amplifier can be applied to several audio power systems.     

一种应用于PWM D类音频功率放大器的CMOS Rail-to-Rail比较器

提出了一种应用于CMOS D类音频功率放大器的Rail-to-Rail PWM比较器,其输入级为Rail-to-Rail结构,输出级为AB类输出。基于CSMC 0.5μm CMOS工艺的BSIM3V3 Spice模型,采用Hspice对PWM比较器的特性进行了仿真,典型模型下的直流开环增益为50dB,电源抑制比为52dB,ICMR为0.04V~4.98V,传输时延为24.5ns,版图有效面积为210×75μm2。由于PWM比较器的良好性能参数,所以其不仅适用于D类音频功率放大器,也能应用于各类低频数据转换电路。     

Notes on class-D transistor amplifiers

Class-D operation of RF amplifiers is characterized by sinusoidal current and pulse-type voltage waveforms at the output of the active circuit element. It is suggested that this is a more accurate model for high-frequency large-signal transistor amplifiers than the conventional Class-C model.     

用于射频D类放大器的多模高精度数字脉冲宽度调制器

介绍了一个用于D类放大器的多模高精度数字脉冲宽度调制器。这个调制器基于一个新型混合结构,不但能产生可编程的占空比,而且能通过相位离散调整实现相位调制。基于近场通信中13.56MHz的开关频率,能够取得570ps的脉冲精度。整个芯片由0.18μm EEPROM CMOS工艺实现,整个调制器面积只有130um 180um。测试结果验证了该调制器的多模功能和高精度的脉冲宽度。     

Multimode high-resolution DPWM for RF class-D amplifiers

This paper describes a multimode high-resolution digital pulse width modulator.This modulator,based on a novel hybrid structure,not only has a programmable duty cycle but also realizes phase modulation.A 576 ps pulse resolution is achieved based on a 13.56 MHz switching frequency for near field communication.Fabricated in a SMIC 0.18-μm EEPROM CMOS process,the total area of modulator is only 130×180μm~2.Measurement results validate the multi-mode modulation function and high pulse resolution.     

用于数字D类放大器的双边PWM调制模块

文中介绍了一种双边PWM调制的数字D类放大器调制模块,使用伪自然采样法消除谐波失真。该伪采样算法是将牛顿-拉夫森迭代法和多项式逼近法相结合而形成的。近年来,虽有较多关于前沿PWM调制（LEPWM）和后沿PWM调制（TEPWM）的数字D类放大器的文献,但基于双边PWM（DEPWM）调制的数字 D类放大器方面的文献较少。因此本文利用现有的噪声整形技术,基于牛顿-拉夫森迭代法的伪采样算法等实现了一种用于数字D类放大器的双边PWM调制模块,并使用FPGA搭建了一个24位立体声数字音频D类放大器调制系统。经测试,该调制系统THD＋N@6 kHz性能达到-80.5 dB。     

Hi-Fi音频功率放大器新技术

1引言现在,电子技术的发展早已进入了数码时代。而功率放大器仍沿袭着传统的模拟设计方式,其技术已相当成熟,几乎到了模拟技术的极限,似乎有落后于数码时代的趋势。但在数字功放方面进行的大量的理论研究仍未摆脱传统的模拟方式。可见传统的模拟功率放大器仍然会在较长的一段时间内,以其相当成熟的技术而大放异彩。2Hi-Fi功放的电压放大功率放大器的目的是将来自声源的信号(约1V),经电压放大和电流放大,产生足够大的输出功率推动扬声器发声。功率放大器的电压放大一般由1～3级电压放大器构成,其线性度、动态特性等直接影响功率放大器的技…     

Sliding mode audio class-D amplifier for portable devices

Audio class-D amplifiers are widely used in industrial and consumer portable electronic devices, such as mobile phones, thanks to their high efficiency. However, these amplifiers have a limited linearity due to their switching behavior and also a limited control bandwidth. To overcome these major drawbacks, this paper introduces a self-oscillating control technique based on the sliding mode theory which combines a large control bandwidth and a spread spectrum technique. A high power supply rejection, which is a crucial parameter in modules directly connected to a noisy battery, has also been achieved by introducing a variable hysteresis window. Theoretical analysis, behavioral and electrical simulations are discussed in detail in this paper. An integrated circuit using 0.13 μm CMOS process has been realized focused on mobile phone applications (0.8 W, 3.6 V and 8 Ω). The audio amplifier achieves 97 dB(A) signal-to-noise ratio, 0.02 % harmonic distortion and up to 80 dB of power supply rejection. The die area is smaller than 0.4 mm² while keeping more than 90 % efficiency at 1 W.     

A simple and versatile overcurrent protection circuit for power MOSFETs

This paper proposes an overcurrent protection (OCP) circuit for power MOSFETs employed in low voltage power converters. The proposed configuration requires only discrete components with a gate driver IC and uses the voltage drop across the device for overcurrent detection. It can operate independently in cycle-by-cycle shutdown and multiple cycle shutdown modes. In coordination with a micro-controller based driver IC input signal generator and controller, the proposed OCP circuit can also operate in a single cycle latch-up and hiccup OCP modes. The performance of the proposed scheme is evaluated experimentally at both, hard and soft fault conditions. By experimentation, it is shown that the proposed circuit can operate in various protection modes and capable of protecting a MOSFET in both, hard and soft fault conditions.     

An integrated 200-W class-D audio amplifier

An integrated stereo class-D audio power amplifier realized in a silicon-on-insulator (SOI)-based BCD technology is presented. The amplifier is capable of delivering 2/spl times/100 W in two 4-/spl Omega/ loads at a supply voltage of 60 V. A second-order feedback loop is used to suppress supply ripple and pulse-shape errors in the switching power stage. The limiting factor in the performance of any class-D amplifiers is the quality of the switching power stage. A high-speed low-current levelshifter and a robust deadtime control arrangement are proposed that enable the realization of a robust high-quality switching power stage. Some practical issues with respect to robustness and electromagnetic compatibility are discussed.     

Design of high-efficiency current-mode class-D amplifiers for wireless handsets

Design considerations are discussed for current-mode class-D (CMCD) microwave power amplifiers. Factors affecting amplifier efficiency are described analytically and via simulation. Amplifiers are reported that incorporate parallel LC resonators alongside the switching transistors. To reduce parasitic resistance, bond-wires were utilized to implement a high Q inductor in the LC resonator. An experimental CMCD amplifier based on GaAs HBTs is reported, with collector efficiency of 78.5% at an output power of 29.5 dBm (0.89 W) at 700 MHz.     

多通道音频功放监控与保护系统的设计

为了在扬声器功率测试过程中对音频功放的各个通道和运行环境进行实时监控与保护,设计了一种智能监控与保护系统。采用ARM7作为系统的主控制器,以USB通讯实现上位机终端与下位机的数据交换,通过真有效值转换和AD采集监控每个通道的运行状态,利用温度传感器实时获取系统温度,由继电器负责切断出现故障的通道,同时通过LED灯指出故障所在位置。经过实验测试表明,系统性能稳定,实时性良好,可以达到监控与保护的目的,并有效地降低了音频功放故障维护的难度,提高了测试效率和安全性。     

开关电源过流保护电路设计研究

本文研究了电源过流电路设计方案和特点以及一些常见的开关电源过流保护方式,寻找到良好的保护电路设计。     

数字音频D类功放电源误差校正方法研究

为了实时校正供电电源噪声引起的数字音频D类功放输出误差,提出一种基于FPGA的电源误差校正方法。使用高精度ADC芯片将电源纹波信号转化为数字量后送入FPGA,校正模块根据电源纹波的大小对数字音频D类功放Sigma-Delta调制器输入值进行预校正处理,从而实现在功放输出端有效的抑制电源噪声。经过实际电路测试,该方法可以有效的抑制电源噪声对数字音频D类功放的影响,电源抑制比达到36.78 dB。     

A power supply error correction method for single-ended digital audio class D amplifiers

In single-ended digital audio class D amplifiers (CDAs), the errors caused by power supply noise in the power stages degrade the output performance seriously. In this article, a novel power supply error correction method is proposed. This method introduces the power supply noise of the power stage into the digital signal processing block and builds a power supply error corrector between the interpolation filter and the uniform-sampling pulse width modulation (UPWM) lineariser to pre-correct the power supply error in the single-ended digital audio CDA. The theoretical analysis and implementation of the method are also presented. To verify the effectiveness of the method, a two-channel single-ended digital audio CDA with different power supply error correction methods is designed, simulated, implemented and tested. The simulation and test results obtained show that the method can greatly reduce the error caused by the power supply noise with low hardware cost, and that the CDA with the proposed method can achieve a total harmonic distortion + noise (THD + N) of 0.058% for a –3 dBFS, 1 kHz input when a 55 V linear unregulated direct current (DC) power supply (with the –51 dBFS, 100 Hz power supply noise) is used in the power stages.     

A digital input class-D audio amplifier with sixth-order PWM

A digital input class-D audio amplifier with a sixth-order pulse-width modulation(PWM)modulator is presented.This modulator moves the PWM generator into the closed sigma–delta modulator loop.The noise and distortions generated at the PWM generator module are suppressed by the high gain of the forward loop of the sigma–delta modulator.Therefore,at the output of the modulator,a very clean PWM signal is acquired for driving the power stage of the class-D amplifier.A sixth-order modulator is designed to balance the performance and the system clock speed.Fabricated in standard 0.18 m CMOS technology,this class-D amplifier achieves 110 dB dynamic range,100 dB signal-to-noise rate,and 0.0056%total harmonic distortion plus noise.     

电磁随钻测量系统D类功率放大电路设计

针对煤矿井下电磁随钻测量系统传统功放电路功耗大、效率低、体积大、难以适应井下供电有限的特殊环境及工作空间狭小、负载不稳定等问题,设计并实现了一种高效D类功率放大电路。该电路以TDA7492MV功放芯片为核心,采用MSP430系列超低功耗单片机对其进行过流监控保护,其具有输出阻抗低、体积小、输出电流大等优点。现场试验表明,该电路能够很好地实现功率放大级的低功耗和高效率。