A BIST Circuit for DLL Fault Detection

A built-in-self-test (BIST) circuit for the test of a delay-locked loop circuit (DLL) is proposed. This circuit is based on a simple xnor logic gate and uncalibrated delay lines to sample the output of the xnor gate, so very little area overhead is introduced. In addition, no external stimulus is required for this BIST circuit, besides the “start test” signal. Fault simulation results show high fault coverage of structural faults, combined with some coverage of parametric variations.      

Design and Analysis of Isolated Noise-Tolerant (INT) Technique in Dynamic CMOS Circuits

Along with the progress of advanced VLSI technology, noise issues in dynamic circuits have become an imperative design challenge. The twin-transistor design is the current state-of-the-art design to enhance the noise immunity in dynamic CMOS circuits. To achieve the high noise-tolerant capability, in this paper, we propose a new isolated noise-tolerant (INT) technique which is a mechanism to isolate noise tolerant circuits from noise interference. Simulation results show that the proposed 8-bit INT Manchester adder can achieve 1.66$times$ average noise threshold energy (ANTE) improvement. In addition, it can save 34% power delay product (PDP) in low signal-to-noise ratio (SNR) environments as compared with the 8-bit twin-transistor Manchester adder under TSMC 0.18-$mu$ m process.      

Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits

The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of nand and nor circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of nand and nor are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function- and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale MOS field-effect-transistor circuits.      

A Change-of-Measure Approach to Per- Flow Delay Measurement Combining Passive and Active Methods: Mathematical Formulation for CoMPACT Monitor

One problem with active measurement is that, while it is suitable for measuring time-average network performance, it is difficult to measure per-flow quality of service (QoS), which is defined as the average over packets in the flow. To achieve such per-flow QoS measurement, the authors proposed a new technique, called the change- of- measure-based passive/active monitoring (CoMPACT Monitor), which is based on the change-of-measure framework in probability/measure theory and transforms actively obtained information by using passively monitored data. This technique enables us to concurrently measure one-way delay information about individual users, applications, and organizations in detail in a lightweight manner. This paper presents the mathematical formulation for the CoMPACT Monitor and verifies that it works well under some weak conditions. In addition, we investigate its characteristics regarding several implementation issues through simulation and actual network experiments. The results reveal that our technique provides highly qualified estimates involving only a limited amount of extra traffic from active probes.      

Dynamic Thermal Clock Skew Compensation Using Tunable Delay Buffers

The thermal gradients existing in high-performance circuits may significantly affect their timing behavior, in particular, by increasing the skew of the clock net and/or altering hold/setup constraints, possibly causing the circuit to operate incorrectly. The knowledge of the spatial distribution of temperature can be used to properly design a clock network that is able to compensate such thermal non-uniformities. However, redesign of the clock network is effective only if temperature distribution is stationary, i.e., does not change over time. In this paper, we specifically address the problem of dynamically modifying the clock tree in such a way that it can compensate for temporal variations of temperature. This is achieved by exploiting the buffers that are inserted during the clock network generation, by transforming them into tunable delay elements. Temperature-induced delay variations are then compensated by applying the proper tuning to the tunable buffers, which is computed offline and stored in a tuning table inserted in the design. We propose an algorithm to minimize the number of inserted tunable buffers, as well as their tunable range (which directly relates to complexity). Results show that clock skew is kept within original bounds with worst-case power and area penalty of 3.5% and 5.5%, respectively.      

Efficient BISR Techniques for Embedded Memories Considering Cluster Faults

Instead of the traditional spare row/column redundancy architectures, block-based redundancy architectures are proposed in this paper. The redundant rows/columns are divided into row/column blocks. Therefore, the repair of faulty memory cells can be performed at the row/column-block level. Moreover, the redundant row/column blocks can be used to replace faulty cells anywhere in the memory array. This global characteristic is helpful for repairing cluster faults. The proposed redundancy architecture can be easily integrated with the embedded memory cores. Based on the proposed global redundancy architecture, a heuristic modified essential spare pivoting (MESP) algorithm suitable for built-in implementation is also proposed. According to experimental results, the area overhead for implementing the MESP algorithm is very low. Due to efficient usage of redundancy, the manufacturing yield, repair rate, and reliability can be improved significantly.      

Unequal Error Protection: An Information-Theoretic Perspective

An information-theoretic framework for unequal error protection is developed in terms of the exponential error bounds. The fundamental difference between the bit-wise and message-wise unequal error protection ( UEP) is demonstrated, for fixed-length block codes on discrete memoryless channels (DMCs) without feedback. Effect of feedback is investigated via variable-length block codes. It is shown that, feedback results in a significant improvement in both bit-wise and message-wise UEPs (except the single message case for missed detection). The distinction between false-alarm and missed-detection formalizations for message-wise UEP is also considered. All results presented are at rates close to capacity.      

On Accurate and Asymmetry-Aware Measurement of Link Quality in Wireless Mesh Networks

This paper presents a highly efficient and accurate link-quality measurement framework, called Efficient and Accurate link-quality monitoR (EAR), for multihop wireless mesh networks (WMNs) that has several salient features. First, it exploits three complementary measurement schemes: passive, cooperative, and active monitoring. By adopting one of these schemes dynamically and adaptively, EAR maximizes the measurement accuracy, and its opportunistic use of the unicast application traffic present in the network minimizes the measurement overhead. Second, EAR effectively identifies the existence of wireless link asymmetry by measuring the quality of each link in both directions of the link, thus improving the utilization of network capacity by up to 114%. Finally, its cross-layer architecture across both the network layer and the IEEE 802.11-based device driver makes EAR easily deployable in existing multihop wireless mesh networks without system recompilation or MAC firmware modification. EAR has been evaluated extensively via both ns-2-based simulation and experimentation on our Linux-based implementation in a real-life testbed. Both simulation and experimentation results have shown EAR to provide highly accurate link-quality measurements with minimum overhead.      

CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-$mu$m CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.      

Noncoherent Synchronization of UWB-IR Multiple-Antenna Multipath Channels

This paper deals with the maximum-likelihood (ML) noncoherent data-aided (e.g., no blind) synchronization of multiple-antenna ultrawideband impulse-radio (UWB-IR) terminals that operate over broadband channels and are affected by multipath fading with a priori unknown number of paths and path-gain statistics. The synchronizer that we developed achieves the ML data-aided joint estimate of the number of paths and their arrival times (e.g., time delays), without requiring any a priori knowledge and/or a posteriori estimate of the amplitude (e.g., module and sign) of the channel gains. The ultimate performance of the proposed synchronizer is evaluated (in closed form) by developing the corresponding CramÉr–Rao bound (CRB), and the analytical conditions for achieving this bound are provided. The performance gain for the synchronization accuracy of multipath-affected UWB-IR signals arising from the exploitation of the multiple-antenna paradigm is (analytically) evaluated. Furthermore, a low-cost sequential implementation of the proposed synchronizer is detailed. It requires an all-analog front-end circuitry composed of a bank of sliding-window correlators, whose number is fully independent from the number of paths comprising the underlying multiple-antenna channel. Finally, the actual performance of the proposed synchronizer is numerically tested under both the signal acquisition and tracking operating conditions.      

Novel Scheme for Joint Estimation of SNR, Doppler, and Carrier Frequency Offset in Double-Selective Wireless Channels

As receiver performance will be degraded by carrier frequency offset (CFO), Doppler shift, and low signal-to-noise ratio (SNR), a novel estimator that jointly considers CFO, Doppler shift, and SNR is proposed in this paper. The proposed algorithm uses the Fourier transform (FT) to calculate the power spectral density of time-varying channels through channel estimates. Then, a new periodogram technique is utilized to estimate CFO, Doppler shift, and SNR together. Unlike conventional methods in sinusoid estimation, which rely on the peak-value search of a periodogram, this paper exploits the hypothesis test to address the random frequency modulation of time-varying channels. Furthermore, to optimize estimation performance, a theoretical analysis is also provided on the influences of some key parameters, e.g., the length of the signal processed with fast FT , the amplitude threshold value, the SNR dynamic range, and the velocity dynamic range. Correspondingly, the appropriate key parameters are chosen according to this analysis and are validated by simulations. The results are consistent with our analysis and present high accuracy over a wide range of velocities and SNRs.      

A Comprehensive Delay Model for CMOS CML Circuits

MOS-transistor-based current-mode logic (CML)-type (MCML) circuits in high-speed circuit applications often operate as low-swing analog circuits rather than fully switched digital circuits. At these high-speed operations, the effect of the finite input signal slope on the delay of MCML gates significantly increases mainly due to incomplete current steering. Hence, for such cases, the conventional RC delay model which is based on ideal step input assumption fails to track the delay of MCML circuits with errors as high as 40% when a design is optimized for high-speed. In this paper, a comprehensive delay model is proposed that accurately predicts the delay of MCML circuits for all types of operation from low-speed and fully switched to high-speed and low-swing applications by including the input slope effect (ISE) into the conventional RC delay model. Furthermore, the proposed model is extended to multilevel complex logic gates without losing the general RC delay model format. Theoretical results are compared with Spice simulations in a 0.13-$mu{hbox {m}}$ CMOS technology. Results show that the error in delay of the proposed model is less than 20% for all practical designs. The proposed model is still sufficiently tractable to be use in back-of-envelope calculations that achieve close-to-optimum solutions without running extensive parametric simulations. In addition to the achieved accuracy and preserved simplicity, the proposed model enhances the intuitive understanding of MCML gates that simple RC delay model fails to provide.      

Buffered Cross-Bar Switches, Revisited: Design Steps, Proofs and Simulations Towards Optimal Rate and Minimum Buffer Memory

Regarding the packet-switching problem, we prove that the weighed max-min fair service rates comprise the unique Nash equilibrium point of a strategic game, specifically a throughput auction based on a “least-demanding first-served” principle. We prove that a buffered crossbar switch can converge to this equilibrium with no pre-computation or internal acceleration, with either randomized or deterministic schedulers, (the latter with a minimum buffering of a single-packet per crosspoint). Finally, we present various simulation results that corroborate and extend our analysis.      

Distributed Throughput Maximization in Wireless Mesh Networks via Pre-Partitioning

This paper considers the interaction between channel assignment and distributed scheduling in multi-channel multi-radio Wireless Mesh Networks (WMNs). Recently, a number of distributed scheduling algorithms for wireless networks have emerged. Due to their distributed operation, these algorithms can achieve only a fraction of the maximum possible throughput. As an alternative to increasing the throughput fraction by designing new algorithms, we present a novel approach that takes advantage of the inherent multi-radio capability of WMNs. We show that this capability can enable partitioning of the network into subnetworks in which simple distributed scheduling algorithms can achieve 100% throughput. The partitioning is based on the notion of Local Pooling. Using this notion, we characterize topologies in which 100% throughput can be achieved distributedly. These topologies are used in order to develop a number of centralized channel assignment algorithms that are based on a matroid intersection algorithm. These algorithms pre-partition a network in a manner that not only expands the capacity regions of the subnetworks but also allows distributed algorithms to achieve these capacity regions. We evaluate the performance of the algorithms via simulation and show that they significantly increase the distributedly achievable capacity region. We note that while the identified topologies are of general interference graphs, the partitioning algorithms are designed for networks with primary interference constraints.      

Channel Estimation in OFDM Systems With Unknown Power Delay Profile Using Transdimensional MCMC

This paper considers the problem of channel estimation for orthogonal-frequency-division multiplexing (OFDM) systems, where the number of channel taps and their power delay profile are unknown. Using a Bayesian approach, we construct a model in which we estimate jointly the coefficients of the channel taps, the channel order and decay rate of the power delay profile (PDP). In order to sample from the resulting posterior distribution we develop three novel Trans-dimensional Markov chain Monte Carlo (TDMCMC) algorithms and compare their performance. The first is the basic birth and death TDMCMC algorithm. The second utilizes Stochastic Approximation to develop an adaptively learning algorithm to improve mixing rates of the Markov chain between model subspaces. The third approximates the optimal TDMCMC proposal distribution for between-model moves using conditional path sampling proposals. We assess several aspects of the model in terms of sensitivities to different prior choices. Next we perform a detailed analysis of the performance of each of the TDMCMC algorithms. This allows us to contrast the resulting computational effort required under each approach versus the estimation performance. Finally, using the TDMCMC algorithm which produces the best performance in terms of exploration of the model subspaces, we assess its performance in terms of channel estimation mean-square error (MSE) and bit error rate (BER). It is shown that the proposed algorithm can achieve results very close to the case where both the channel length and the PDP decay rate are known.      

SEChecker: A Sequential Equivalence Checking Framework Based on ${K}$th Invariants

In recent years, considerable research efforts have been devoted to utilizing circuit structural information to improve the efficiency of Boolean satisfiability (SAT) solving, resulting in several efficient circuit-based SAT solvers. In this paper, we present a sequential equivalence checking framework based on a number of circuit-based SAT solving techniques as well as a novel invariant checker. We first introduce the notion of $k$th invariants. In contrast to the traditional invariants that hold for all cycles, $k$ th invariants are guaranteed to hold only after the $k$th cycle from the initial state. We then present a bounded model checker (BMChecker) and an invariant checker (IChecker), both of which are based on circuit SAT techniques. Jointly, BMChecker and IChecker are used to compute the $k$th invariants, and are further integrated in a sequential circuit SAT solver for checking sequential equivalence. Experimental results demonstrate that the new sequential equivalence checking framework can efficiently verify large industrial designs that cannot be verified by existing solutions.      

Design and Implementation of Cost-Effective Probabilistic-Based Noise-Tolerant VLSI Circuits

As the size of CMOS devices is scaled down to nanometers, noise can significantly affect circuit performance. Because noise is random and dynamic in nature, a probabilistic-based approach is better suited to handle these types of errors compared with conventional CMOS designs. In this paper, we propose a cost-effective probabilistic-based noise-tolerant circuit-design methodology. Our cost-effective method is based on master-and-slave Markov random field (MRF) mapping and master-and-slave MRF logic-gate construction. The resulting probabilistic-based MRF circuit trades hardware cost for circuit reliability. To demonstrate a noise-tolerant performance, an 8-bit MRF carry-lookahead adder (MRF_CLA) was implemented using the 0.13-${rm mu}hbox{m}$ CMOS process technology. The chip measurement results show that the proposed master-and-slave MRF_CLA can provide a $7.00times 10^{-5}$ bit-error rate (BER) under 10.6-dB signal-to-noise ratio, while the conventional CMOS_CLA can only provide $8.84times 10^{-3}$ BER. Because of high noise immunity, the master-and-slave MRF_CLA can operate under 0.25 V to tolerate noise interference with only 1.9 ${rm mu}hbox{W/MHz}$ of energy consumption. Moreover, the transistor count can be reduced by 42% as compared with the direct-mapping MRF_CLA design .      

Modeling of Distributed RLC Interconnect and Transmission Line via Closed Forms and Recursive Algorithms

This paper presents the closed forms of the state-space models and the recursive algorithms of the transfer function models for fast and accurate modeling of the distributed RLC interconnect and transmission lines, which may be evenly or unevenly distributed. Considered models include the distributed RLC interconnect lines with or without external source and load connection. The effective closed forms and recursive algorithms do not involve any matrix inverse, LU matrix factorization, or matrix multiplication, thus reducing the computation complexity dramatically. Especially, the computation complexity of the closed forms for any evenly or unevenly distributed RLC interconnect line circuits is only O(1) or $ { O}(m)$, respectively, in sense of the scalar multiplication times, where $ { m}ll{ N}$ of the system order. The features of new recursive algorithms are two recursive s-polynomials and the low computation complexity. Examples illustrate the new methods in both time and frequency domains. Comparing with the PSpice, the new methods can dramatically reduce the runtime of the time responses and the Bode plots by 25% – 98.5% in the examples. The results can be applied to the RLC interconnect analysis and model reduction as a key to new approach.      

Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs

The RC-based power-rail electrostatic-discharge (ESD) clamp circuit with big field-effect transistor (BigFET) layout style in the main ESD clamp n-channel metal–oxide–semiconductor (NMOS) transistor was widely used to enhance the ESD robustness of a CMOS IC fabricated in advanced CMOS processes. To further reduce the occupied layout area of the RC in the power-rail ESD clamp circuit, a new ESD-transient detection circuit realized with smaller capacitance has been proposed and verified in a 0.13- $muhbox{m}$ CMOS process. From the experimental results, the power-rail ESD clamp circuit with the new proposed ESD-transient detection circuit can achieve a long-enough turn-on duration and higher ESD robustness under ESD stress condition, as well as better immunity against mistrigger and latch-on event under the fast-power-on condition.      

Interconnect Exploration for Energy Versus Performance Tradeoffs for Coarse Grained Reconfigurable Architectures

Modern portable embedded devices require processors that can provide sufficient performance for demanding multimedia and wireless applications. At the same time they have to be flexible to support a wide range of products and extremely energy efficient to provide a long battery life. Coarse Grained Reconfigurable Architectures (CGRAs) potentially meet these constraints by providing a mix of flexible computational resources and large amounts of programmable interconnect. The vast design space of CGRAs complicates the development of optimized processors. Most effort has been spent on improving the performance. However, the energy cost of the programmable interconnect is becoming more expensive and this cost can no longer be neglected. In this work we present an energy- and performance-aware exploration for the interconnect of a CGRA and show that important tradeoffs can be made for those metrics. This will enable designers to develop more efficient architectures, tuned to a targeted application domain.