Void detection in solder bumps with deep learning

Wafer level chip scale packages feature large numbers of solder bumps. These bumps are prone to having voids arising for instance from outgassing during the solder reflow. These voids are considered a reliability risk for the thermo-mechanical strength of the solder connection. Screening of bumps on void percentage is therefore required for quality control. Voids are well captured with X-ray radiography. Void detection in X-ray images is the topic of this paper. The large number of solder bumps necessitates the detection to be automated. In this article we first employ conventional threshold based methods to identify voids. Then, we apply a deep learning model to void percentage detection. We will demonstrate that with a proper training data set deep learning can successfully bin solder bumps on their void percentage.     

Defect inspection of solder bumps using the scanning acoustic microscopy and fuzzy SVM algorithm

Flip chip technology has been extensively used in high density electronic packaging over the past decades. With the decrease of solder bumps in dimension and pitch, defect inspection of solder bumps becomes more and more challenging. In this paper, an intelligent diagnosis system using the scanning acoustic microscopy (SAM) is investigated, and the fuzzy support vector machine (F-SVM) algorithm is developed for solder bump recognition. In the F-SVM algorithm, we apply a fuzzy membership to input feature data so that the different input features can make different contributions to the learning procedure of the network. It solves the problem of feature data aliasing in the traditional SVM. The SAM image of flip chip is captured by using an ultrasonic transducer of 230 MHz. Then the segmentation of solder bumps is based on the gradient matrix of the original image, and the statistical features corresponding to every solder bump are extracted and adopted to the F-SVM network for solder bump classification and recognition. The experiment results show a high accuracy of solder defect recognition, therefore, the diagnosis system using the F-SVM algorithm is effective and feasible for solder bump defect inspection.     

Fabrication on uniform plating-based flip chip solder bumps after reflow process using a polishing mechanism

This paper presents an innovative polishing process aimed at leveling rough surface of plating-based flip chip solder bumps so as to get uniform coplanarity across the whole substrate after both electroplating and reflow processes. This polishing mechanism is characteristic of combining mechanical-dominated polishing force with slight chemical reaction together. A large number of extremely but inevitably rugged mushroom-like structures after electroplating are drastically smoothed down with the help of this newly-developed polishing process. Nearly 70 μm solder bumps in height with two different profiles as square and circle on the substrates reach as flatly as ±3 μm between different substrates after reflow process; ±2.5 μm in single substrate; and even ±1 μm in die, respectively. Besides, surface roughness among the solder bumps is simultaneously narrowed down from Ra 0.6 to Ra 0.03 along with the coplanarity improvement. Excellent uniformity and smooth surface roughness in solder bumps are absolutely beneficial to pile up and deposit in the following steps in MEMS and semiconductor fields.     

Simulation and measurement of the flip chip solder bumps with a Cu-plated plastic core

With the aim to miniaturize and to reduce the cost, the increasing demand, regarding to advanced 3D-packages as well as high performance applications, accelerates the development of 3D-silicon integrated circuits. The trend to smaller and lighter electronics has highlighted many efforts towards size reduction and increased performance in electronic products. The radio frequency (RF) performances are limited by parasitic effects due to the resistor–inductor–capacitor (RLC) network, between the wire bond connections from the dies to the lead frame. The use of flip-chip bonding technology for very fine pitch packaging allows high integration and limits parasitic inductances. Electromigration (EM) and thermomigration (TM) may have serious reliability issues for fine-pitch Pb-free solder bumps in the flip-chip technology used in consumer electronic products. A possibility to extend the reliability is the use of plastic ball in the solder bumps. Bumps containing a plastic solder balls have an excellent reliability. Using a plastic ball with a low Young modulus, the solder hardness is moderated and the stress on a ball is relaxed. Due to this, the stress does not concentrate on the solder joint which prolongs the lifetime. In this investigation, the thermal–electrical–mechanical coupling of electromigration on bumps containing a plastic solder is studied.     

Formation of Pb/63Sn solder bumps using a solder droplet jetting method

Formation processes of Pb/63Sn solder droplets using a solder droplet jetting have not been sufficiently reported. Solving problems such as satellite droplets and position errors are very important for a uniform bump size and reliable flip-chip solder bump formation process. First, this paper presents the optimization of jet conditions of Pb/63Sn solder droplets and the formation process of Pb/63Sn solder bumps using a solder droplet jetting method. Second, interfacial reactions and mechanical strength of jetted Pb/63Sn solder bumps and electroless Ni-P/Au UBM joints have been investigated. Interfacial reactions have been investigated after the second solder reflow and aging, and results were compared with those of solder bumps formed by a solder screen-printing method. Third, jetted solder bumps with variable bump sizes have been demonstrated by a multiple jetting method and the control of waveform induced to a jet nozzle. Multiple droplets jetting method can control various height and size of solder bumps. Finally, real applications of jetted Pb/63Sn solder bumps have been successfully demonstrated on conventional DRAM chips and integrated passive devices (IPDs).     

Preparation of Sn-Ag-In ternary solder bumps by electroplating in sequence and reliability

This paper describes a technique that can obtain ternary Sn-Ag-In solder bumps with fine pitch and homogenous composition distribution.The main feature of this process is that tin-silver and indium are electroplated on copper under bump metallization（UBM） in sequence.After an accurate reflow process,Sn_1.8Ag_9.4In solder bumps are obtained.It is found that the intermetallic compounds（IMCs） between Sn-Ag-In solder and Cu grow with the reflow time,which results in an increase in Ag concentration in the solder area.So during solidification, more Ag₂In nucleates and strengthens the solder.     

Characteristics of current crowding in flip-chip solder bumps

For a flip-chip package assembly, current crowding occurs in the vicinity of the locations where traces connect the solder bumps. This feature contributes significantly to the electromigration failure of the solder bumps. In this study the finite element analysis is performed to investigate characteristics of current crowding in a flip-chip solder bump subjected to a constant applied current. It is found that under such a condition, current crowding is induced solely by the structural geometry of the system. It is independent of the magnitude of the applied current. A volumetric averaging technique is also applied to cope with the current crowding singularity.     

A study on coining processes of solder bumps on organic substrates

Solder flip chip bumping and subsequent coining processes on printed circuit board (PCB) were investigated to solve the warpage problem of organic substrates for high pin count flip chip assembly by providing good co-planarity. Coining of solder bumps on PCBs has been successfully demonstrated using a modified tension/compression tester with height, coining rate and coining temperature variables. It was observed that applied loads as a function of coined height showed three stages as coining deformation; region of elastic deformation; region of linearly increase of applied loads; region of rapidly increase of applied loads. In order to reduce applied loads for coining solder bumps on a PCB, the effects of coining process parameters were investigated. Coining loads for solder bump deformation strongly depended on coining rates and coining temperatures. As coining rates decreased and process temperature increased, coining loads decreased. Lower coining loads were needed to prevent potential substrate damages such as micro-via failure and build-up dielectric layer thickness change during applying coining loads. It was found that coining process temperature had more significant effect to reduce applied coining loads during the coining process.     

Characterization of small-sized eutectic Sn-Bi solder bumps fabricated using electroplating

We studied the effects of the cooling rate during the reflow process on the microstructure of eutectic Sn-Bi solder bumps of various sizes fabricated by electroplating. To fabricate eutectic Sn-Bi solder bumps of less than 50 μm in diameter, Sn-Bi alloys were electroplated on Cu pads and reflowed at various cooling rates using the rapid thermal annealing system. The interior microstructure of electroplated bumps showed a fine mixture of Sn-rich phases and Bi-rich phases regardless of the cooling rate. Such an interior microstructure of electroplated bumps was quite different from the reported microstructure of vacuum-evaporated bumps. Ball shear tests were performed to study the effects of the cooling rate on the shear strength of the solder bumps and showed that the shear strength of the bumps increased with increasing cooling rate probably due to the reduced grain size. Soft fractures inside the solder bump were observed during the ball shear test regardless of the cooling rate.     

The effect of solder bump pitch on the underfill flow

An underfill encapsulant was used to fill the gap between the chip and substrate around solder joints to improve the long-term reliability of flip chip interconnect systems. The underfill encapsulant was filled by the capillary effect. In this study, the filling time and pattern of the underfill flow in the process with different bumping pitch, bump diameter, and gap size were investigated. A modified Hele-Shaw flow model, that considered the flow resistance in both the thickness direction and the restrictions between solder bumps, was used. This model estimated the flow resistance induced by the chip and substrate as well as the solder bumps, and provided a reasonable flow front prediction. A modified model that considered the effect of fine pitch solder bumps was also proposed to estimate the capillary force in fine pitch arrangements. It was found that, on a full array solder bump pattern, the filling flow was actually faster for fine pitch bumps in some arrangements. The filling time of the underfill process depends on the parameters of bumping pitch, bump diameter, and gap size. A proposed capillary force parameter can provide information on bump pattern design for facilitating the underfilling process.     

Characterisation of electroplated Sn/Ag solder bumps

Environmental concerns as well as legal constraints have been pushing research on flip chip technology towards the development of lead-free solders and also to new deposition techniques [Z.S. Karim, R. Schetty, Lead-free bump interconnections for flip-chip applications, in: IEEE/CPMT 1nternational Electronics Manufacturing Technology Symposium, 2000, pp. 274-278, P. Wölflick, K. Feldmann, Lead-free low-cost flip chip process chain: layout, process, reliability, in: IEEE International Electronics Manufacturing Technology (IEMT) Symposium, 2002, pp. 27-34, M. McCormack, S. Jin, The design and properties of new, pb-free solder alloys, in: IEEE/CPMT International Electronics Manufacturing Technology Symposium, 1994, pp. 7-14, T. Laine-Ylijoki, H. Steen, A. Forsten, Development and validation of a lead-free alloy for solder paste applications. IEEE Transactions on Components, Packaging, and Manufacturing technology, 20(3) (1997) 194-198, D. Frear, J. Jang, J. Lin, C. Zhang, Pb-free solders for flip-chip interconnects, JOM, 53(6) (2001) 28-32].Binary and ternary tin alloys are promising candidates to substitute lead-content components. In this paper, we describe an electroplating technique for high density FlipChip packaging [M. Bigas, E. Cabruja, Electrodeposited Sn/Ag for flip chip connection, CDE (2003)]. An analysis using Auger Electron Spectroscopy (AES) together with additional Energy Dispersive Xray analysis (EDS) tests and Scanning Electron Microscope (SEM) analysis have been performed to optimize the reflow process of the electrodeposited bumps.     

Study of the UBM to copper interface robustness of solder bumps in flip chip packages

Shear tests on SnAg solder bumps were performed with a reduced height to the surface for a high shear force on the under bump metallurgy (UBM) to redistribution layer (RDL) copper interface. By this the failure mechanism of UBM–RDL delamination after stress tests simulating several assembly reflows could be reproduced. A design of experiment was done with corner wafers at worst case conditions for topography and interface clean. TEM cross sections confirmed nano scale carbon residues in the interface when reducing the clean efficiency. This results in a mechanically weakened interface with a present electrical contact. The shear test with reduced height is a more severe test beyond the JEDEC test to verify the bump robustness. This is important when existing bump technologies are used for flip chip package solutions with increased solder reflow requirements.     

Optoelectronic and microwave transmission characteristics of indium solder bumps for low-temperature flip-chip applications

This paper describes low-temperature flip-chip bonding for both optical interconnect and microwave applications. Vertical-cavity surface-emitting laser (VCSEL) arrays were flip-chip bonded onto a fused silica substrate to investigate the optoelectronic characteristics. To achieve low-temperature flip-chip bonding, indium solder bumps were used, which had a low melting temperature of 156.7/spl deg/C. The current-voltage (I-V) and light-current (L-I) characteristics of the flip-chip bonded VCSEL arrays were improved by Ag coating on the indium bump. The I-V and L-I curves indicate that optical and electrical performances of Ag-coated indium bumps are superior to those of uncoated indium solder bumps. The microwave characteristics of the solder bumps were investigated by using a flip-chip-bonded coplanar waveguide (CPW) structure and by measuring the scattering parameter with an on-wafer probe station for the frequency range up to 40 GHz. The indium solder bumps, either with or without the Ag coating, provided good microwave characteristics and retained the original characteristic of the CPW signal lines without degradation of the insertion and return losses by the solder bumps.     

Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages

Detailed three-dimensional finite element analysis was carried out for area-array solder-bumped flip-chip packages. The analysis enabled determinations of accurate three-dimensional effects on stress distributions as well as local fracture behaviors under thermal load. The 3D analysis also estimated thermal fatigue life of solder bumps. Since dimensions of various components span more than three orders of magnitude, the multi-scale finite element models were utilized to elucidate detailed deformation state near solder bumps. The global–local approach identified of critical solder bumps due to the overall deformation and investigated of interfacial delamination at microstructural level. The local model contained a single solder bump and sub-micron UBM layers. The two-step modeling approach enabled accurate fracture analysis otherwise difficult in large 3D models. Our analysis found the crack driving force and preferred delamination direction based on the 3D J-integral calculations. Shear deformations within and surrounding solder bump connectors were also investigated. The results revealed higher deformation in the 3D model than those predicted from 2D models. Additionally, the strain components were different. This has an important implication on the plastic flow characteristics during cyclic loading. Our model estimated about 25% greater steady-state shear strains in the 3D model than those in the 2D models. This result suggests a much shorter fatigue life than that based on the 2D analysis.     

A novel flip-chip interconnection technique using solder bumps forhigh-speed photoreceivers

A flip-chip interconnection technique using small solder bumps instead of conventional wire bonding for high-speed broadband photoreceivers is described. The technique achieves interconnection with low parasitic elements, no damage to devices, and easy assembly. A photoreceiver composed of a broadband p-i-n photodiode and a laser-speed GaAS metal-semiconductor field-effect transistor (MESFET) preamplifier connected using solder bumps that are about 26 μm in diameter, with a frequency response of over 22 GHz at 1.55 μm, is demonstrated. This confirms the effectiveness of the solder bump interconnection technique for future high-speed broadband optical modules     

Microstructure characterization of Sn-Ag solder joints between stud bumps and metal pads

The microstructure of the flip-chip solder joints fabricated using stud bumps and Pb-free solder was characterized. The Au or Cu stud bumps formed on Al pads on Si die were aligned to corresponding metal pads in the substrate, which was printed with Sn-3.5Ag paste. Joints were fabricated by reflowing the solder paste. In the solder joints fabricated using Au stud bumps, Au-Sn intermetallics spread over the whole joints, and the solder remained randomly island-shaped. The δ-AuSn, ε-AuSn₂, and η-AuSn₄ intermetallic compounds formed sequentially from the Au stud bump. The microstructure of the solder joints did not change significantly even after multiple reflows. The AuSn₄ was the main phase after reflow because of the fast dissolution of Au. In the solder joints fabricated using Cu stud bumps, the scallop-type Cu₆Sn₅ intermetallic was formed only at the Cu interface, and the solder was the main phase. The difference in the microstructure of the solder joints with Au and Cu stud bumps resulted from the dissolution-rate difference of Au and Cu into the solder.     

Connection of VLSI chips to printed circuit board using stacked solder bumps

A new type of flip-chip interconnection technology usingstacked solder bumps is proposed, where the diameter of theupper solder bump is less than that of the lower ones. This isto reduce the capacitance between the stacked solder bumps and the ground plane and to prolong the lifetime ofthe solder joints.     

A new COG technique using low temperature solder bumps for LCD driver IC packaging applications

A new chip on glass (COG) technique using flip chip solder joining technology has been developed for excellent resolution and high quality liquid crystal display (LCD) panels. The flip chip solder joining technology has several advantages over the anisotropic conductive film (ACF) bonding technology: finer pitch capability, better electrical performance, and easier reworkability. Conventional solders such as eutectic Pb-Sn and Pb-5Sn require high temperature processing which can lead to degradation of the liquid crystal or the color filter in LCD modules. Thus it is desirable to develop a low temperature process below 160/spl deg/C using solders with low melting temperatures for this application. In our case, we used eutectic 58 wt%Bi-42 wt%Sn solder for this purpose. Using the eutectic Bi-Sn solder bumps of 50-80/spl mu/m pitch sizes, an ultrafine interconnection between the IC and glass substrate was successfully made at or below 160/spl deg/C. The average contact resistance of the Bi-Sn solder joints was 19m/spl Omega/ per bump, which is much lower than the contact resistance of conventional ACF bonding technologies. The contact resistance of the underfilled Bi-Sn solder joints did not change during a hot humidity test. We demonstrate that the COG technique using low temperature solder joints can be applied to advanced LCDs that lead to require excellent quality, high resolution, and low power consumption.     

High-speed photoreceivers using solder bumps and microstrip linesformed on a silicon optical bench

High-speed photoreceiver modules using silicon optical benches are described. These modules employ solder bumps for chip assembly and microstrip lines for electrical signal transmission. The assembly and wiring technologies are the same as those used in the planar lightwave circuit platforms we developed. A photoreceiver module consisting of a waveguide photodiode showed a very wide bandwidth greater than 20 GHz, and together with a spotsize-converted semiconductor optical amplifier, operated as an optical preamplifier that showed good receiver sensitivity of -20.3 dBm at 10 Gb/s nonreturn-to-zero     

Manufacturing of Cu/electroless nickel/Sn-Pb flip chip solder bumps

A process for manufacturing Cu/electroless Ni/Sn-Pb solder bump is discussed in this paper. An attempt to replace zincation with a Cu film as an active layer for the electroless Ni (EN) deposition on Al electrode on Si wafer is presented. Cu/electroless Ni is applied as under bump metallurgy (UBM) for solder bump. The Cu film required repeated etches with nitric acid along with activation to achieve a satisfactory EN deposit. Fluxes incorporating rosin and succinic acid were investigated for wetting kinetics and reflow effectiveness of the electroplated solder bump. The solder plating current density and the reflow condition for achieving solder bumps with uniform bump height were described. The Cu/EN/Sn-Pb solder system was found to be successfully produced on Al terminal in this study that avoids using zincating process