Improved Electrical Characteristics and Reliability of MILC Poly-Si TFTs Using Fluorine-Ion Implantation

In this letter, fluorine-ion (F⁺) implantation was employed to improve the electrical performance of metal-induced lateral-crystallization (MILC) polycrystalline-silicon thin-film transistors (poly-Si TFTs). It was found that fluorine ions minimize effectively the trap-state density, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, low subthreshold slope, and high on/off-current ratio. F⁺-implanted MILC TFTs also possess high immunity against the hot-carrier stress and, thereby, exhibit better reliability than that of typical MILC TFTs. Moreover, the manufacturing processes are simple (without any additional thermal-annealing step), and compatible with typical MILC poly-Si TFT fabrication processes.     

An investigation of laser annealed and metal-induced crystallizedpolycrystalline silicon thin-film transistors

We report results on thin-film transistors (TFTs) made from a new hybrid process in which amorphous silicon (a-Si) is first converted to polycrystalline silicon (poly-Si) using Ni-metal-induced lateral crystallization (MILC), and then improved using excimer laser annealing (laser MILC or L-MILC). With only a very low shot laser process, we demonstrate that laser annealing of MILC material can improve the electron mobility from 80 to 170 cm²/Vs, and decrease the minimum leakage current by one to two orders of magnitude at a drain bias of 5 V. Similar trends occur for both p- and n-type material. A shift in threshold voltage upon laser annealing indicates the existence of a net positive charge in Ni-MILC material, which is neutralised upon laser exposure. The MILC material in particular exhibits a very high generation state density of ~10¹⁹ cm^-3 which is reduced by an order of magnitude in L-MILC material. The gate and drain field dependences of leakage current indicate that the leakage current in MILC transistors is related to this high defect level and the abruptness of the channel/drain junction. This can be improved with a lightly doped drain (LDD) implant, as in other poly-Si transistors     

Low temperature poly-Si thin-film transistor fabrication bymetal-induced lateral crystallization

A new low temperature crystallization method for poly-Si TFTs was developed: Metal-Induced Lateral Crystallization (MILC). The a-Si film in the channel area of a TFT was laterally crystallized from the source/drain area, on which an ultrathin nickel layer was deposited before annealing. The a-channel poly-Si TFTs fabricated at 500°C by MILC showed a mobility of 121 cm²/V·s, a threshold voltage of 1.2 V, and an on/off current ratio of higher than 10⁶ . These electrical properties are much better than TFTs fabricated by conventional crystallization at 600°C     

低温金属诱导横向晶化多晶硅材料和器件技术

使用金属镍诱导非晶硅晶化(MIC:metal-induced crystallization)技术,获得了低温(＜550℃)多晶硅.通常在镍覆盖区以外的晶化硅更加有用,这一技术被称为金属诱导横向晶化(MILC:metal-induced lateral crystallization)技术.通过对结晶动力学过程和材料特性的研究,提出了可同时适用于镍覆盖区和相连非覆盖区金属诱导结晶的同一晶化机制.虽然MILC多晶硅的材料特性明显优于固相晶化多晶硅的材料特性,薄膜晶体管沟道中存在MIC/MILC 的界面所形成的横向晶界会明显的降低其性能.若将这些界面从沟道中去除掉,即可获得可满足液晶和有机发光二极管等显示器进行系统集成所需的高性能器件.     

High-Performance Metal-Induced Laterally Crystallized Polycrystalline Silicon P-Channel Thin-Film Transistor With $hbox{TaN/HfO}_{2}$ Gate Stack Structure

In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral- crystallization (MILC) channel layer and TaN/HfO₂ gate stack is demonstrated for the first time. The devices of low threshold voltage V_TH ~ 0.095 V, excellent subthreshold swing S.S. ~83 mV/dec, and high field-effect mobility mu_FE ~ 240 cm²/V ldr s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO₂ gate dielectric with the effective oxide thickness of 5.12 nm.     

Fabrication of high-mobility p-channel poly-Si thin filmtransistors by self-aligned metal-induced lateral crystallization

High-mobility p-channel poly-Si TFTs were fabricated using a new low-temperature process (⩽500°C): self-aligned metal-induced lateral crystallization (MILC). With a one-step annealing at 500°C, activation of dopants in source/drain/gate a-Si films as well as the crystallization of channel a-Si films was achieved. The TFTs showed a threshold voltage of -1.7 V, and an on/off current ratio of ~10⁷ without post-hydrogenation. The mobility was measured to be as high as 90 cm²/V·s, which is two to three times higher than that of the poly-Si TFTs fabricated by conventional solid-phase crystallization at around 600°C     

The Electrical Properties of Unidirectional Metal-Induced Lateral Crystallized Polycrystalline-Silicon Thin-Film Transistors

It has been known that adjacent Pd enhances the crystallization rate in Ni metal-induced lateral crystallization (Ni-MILC) and this knowledge has been used to fabricate the unidirectional MILC thin-film transistors (TFTs), which eliminate the boundary formed at the center of TFT channel in a normal MILC TFTs. It is discovered that the MILC/MILC boundary (MMB) is responsible for the high leakage current and low field- effect mobility. The electrical properties of unidirectional MILC TFTs (Width/Length = 10/10 mum) improved considerably comparing to those of MILC TFTs containing the MMB. The leakage current and field-effect mobility, which have been regarded as obstacles for industrialization of the MILC process, measure to be 2.1 X 10-11 A and 83 cm²/ V ldr s, respectively.     

Improved Electrical Performance of MILC Poly-Si TFTs Using $hbox{CF}_{4}$ Plasma by Etching Surface of Channel

In this letter, a new manufacturing method for metal-induced lateral crystallization (MILC) polycrystalline silicon thin-film transistors (poly-Si TFTs) using $hbox{CF}_{4}$ plasma was proposed. It was found that $hbox{CF}_{4}$ plasma effectively minimizes the trap-state density by etching away the top surface of MILC and passivating the trap states, leading to superior electrical characteristics such as high field-effect mobility, low threshold voltage, low subthreshold slope, low leakage current, and high ON-/ OFF-current ratio. $hbox{CF}_{4}$ -plasma MILC TFTs also possess high immunity against the hot-carrier stress and thereby exhibit better reliability than that of conventional MILC TFTs. Moreover, the manufacturing processes are simple (without any additional thermal annealing step) and compatible with MILC TFT processes.      

The effects of high temperature annealing on metal-inducedlaterally crystallized polycrystalline silicon

Metal-induced laterally crystallized (MILC) polycrystalline silicon (poly-Si) with and without a post-crystallization high temperature anneal have been studied and compared. It was revealed using transmission electron microscopy (TEM) that the anneal resulted in significant improvement in the material quality. Consequently, the electrical properties of the annealed MILC poly-Si resistors were greatly enhanced, showing conduction behavior approaching that of single-crystal Si. Thin-film transistors realized on high-temperature annealed MILC poly-Si exhibited excellent device characteristics, thus making them potentially applicable to three-dimensional (3-D) device integration. Based on the TEM observations and a detailed consideration of the mechanism of grain growth during MILC, the effects of the anneal can be explained in terms of the evolution of the unique MILC grain structure during the high temperature treatment     

A new MoSi2/Thin poly-Si gate process technology without dielectric degradation of a gate oxide

The dielectric degradation phenomena in gate oxides of MoSi²/thin n⁺poly-Si (<100 nm) gate structure which appeared after high-temperature annealing have been analyzed in detail. Analyses included obtaining the correlation between gate oxide dielectric characteristics and various factors like phosphorus concentration in poly-Si, native oxide on poly-Si, sheet resistance of MoSi², and the SEM or TEM observations of textures of MoSi², poly-Si, and gate oxide. From analyses, it was concluded that the local reaction of molybdenum silicide with poly-Si under the presence of a barrier, like the thick native oxide on poly-Si formed before MoSi²deposition, results in the damage to a gate oxide through a thin poly-Si layer during annealing. Based upon analytical results, a new MoSi²/thin poly-Si gate process without dielectric degradation has been developed, in which the direct MoSi²deposition on undoped poly-Si to suppress the native oxide growth and phosphorus implantation into MoSi²were introduced. The process provided a good dielectric strength of a gate oxide even to the device with a poly-Si layer as thin as 50 nm, an easy dry etching without undercutting of poly-Si, and stable device characteristics and reliabilities compatible to a conventional poly-Si gate process.     

Fabrication of thin film transistors by chemical mechanicalpolished polycrystalline silicon films

A top-gate p-channel polycrystalline thin film transistor (TFT) has been fabricated using the polycrystalline silicon (poly-Si) film as-deposited by ultrahigh vacuum chemical vapor deposition (UHV/CVD) and polished by chemical mechanical polishing (CMP). In this process, long-term recrystallization in channel films is not needed. A maximum field effect mobility of 58 cm²/V-s, ON/OFF current ratio of 1.1 10⁷, and threshold voltage of -0.54 V were obtained. The characteristics are not poor. In this work, therefore, we have demonstrated a new method to fabricate poly-Si TFT's     

Study on hydrogenation of polysilicon thin film transistors by ionimplantation

Hydrogenation of polysilicon (poly-Si) thin film transistors (TFT's) by ion implantation has been systematically studied. Poly-Si TFT performance was dramatically improved by hydrogen ion implantation followed by a forming gas anneal (FGA). The threshold voltage, channel mobility, subthreshold swing, leakage current, and ON/OFF current ratio have been studied as functions of ion implantation dose and FGA temperature. Under the optimized conditions (H⁺ dose of 5×10¹⁵ cm^-2 and FGA temperature at 375°C), NMOS poly-Si TFT's fabricated by a low temperature 600°C process have a mobility of ~27 cm ²/V·s, a threshold voltage of ~2 V, a subthreshold swing of ~0.9 V/decade, and an OFF-state leakage current of ~7 pA/μm at V_DS=10 V. The avalanche induced kink effect was found to be reduced after hydrogenation     

Suppression of cobalt silicide agglomeration using nitrogen(N2+) implantation

In this paper, the effects of nitrogen coimplantation with boron into p⁺-poly gate in PMOSFETs on the agglomeration effects of CoSi₂ are studied. The thermal stability of CoSi₂/poly-Si stacked layers can be significantly improved by using nitrogen implantation. Samples with 40-nm cobalt silicide (CoSi ₂) on 210-nm poly-Si implanted by 2×10¹⁵/cm ² N₂⁺ are thermally stable above 950°C for 30 s in N₂ ambient. If the dose of nitrogen is increased up to 6×10¹⁵/cm², the sheet resistance of CoSi₂ film is not increased at all, and TEM photographs show that the agglomeration of CoSi₂ film is completely suppressed     

Effects of NH3 plasma passivation on N-channelpolycrystalline silicon thin-film transistors

The NH₃-plasma passivation has been performed on polycrystalline silicon (poly-Si) thin-film transistors (TFT's), It is found that the TFT's after the NH₃-plasma passivation achieve better device performance, including the off-current below 0.1 pA/μm and the on/off current ratio higher than 10⁸, and also better hot-carrier reliability than the H₂-plasma devices. Based on optical emission spectroscopy (OES) and secondary ion mass spectroscopy (SIMS) analysis, these improvements were attributed to not only the hydrogen passivation of the defect states, but also the nitrogen pile-up at SiO₂/poly-Si interface and the strong Si-N bond formation to terminate the dangling bonds at the grain boundaries of the polysilicon films. Furthermore, the gate-oxide leakage current significantly decreases and the oxide breakdown voltage slightly increases after applying NH₃-plasma treatment. This novel process is of potential use for the fabrication of TFT/LCD's and TFT/SRAM's     

A comprehensive study of suppression of boron penetration byamorphous-Si gate in P+-gate PMOS devices

This paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p⁺-gate devices. The characteristics and reliability for different gate structures (poly-Si, α-Si, poly-Si/poly-Si, poly-Si/α-Si, α-Si/poly-Si, and α-Si/α-Si) in p ⁺ polygate PMOS devices are investigated in detail. The suppression of boron penetration by the nitrided gate oxide is also discussed. The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p⁺ polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate. Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance. The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p⁺-gate PMOS device for future dual-gate CMOS process. In addition, by employing a long time annealing at 600°C prior to p⁺-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate. Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect     

Characteristics of offset-structure polycrystalline-siliconthin-film transistors

In order to reduce anomalous leakage current from n-channel polycrystalline-silicon thin-film transistors (poly-Si TFTs), an offset structure that has an n^- region between channel and n⁺ source-drain electrodes has been proposed. Drain-current measurements of the poly-Si TFT prove that the offset structure is effective in reducing the anomalous leakage current, and that the optimization of the offset length and the doping concentration in the offset region enlarge the ON/OFF current ratio. Implantation of 5×10¹³ cm^-2 phosphorus ions in the offset region makes the ON/OFF current ratio more than one order of magnitude larger than that of conventional structure TFTs     

Electrical properties of heavily doped polycrystallinesilicon-germanium films

The electrical properties of polycrystalline silicon-germanium (poly-Si_1-xGe_x) films with germanium mole fractions up to 0.56 doped by high-dose ion implantation are presented. The resistivity of heavily doped p-type (P⁺) poly-Si_1-x Ge_x is much lower than that of comparably doped poly-Si, because higher levels of boron activation and higher hole mobilities are achieved in poly-Si_1-xGe_x. The resistivity of heavily doped n-type (N⁺) poly-S_1-xGe_x is similar to that of comparably doped poly-Si for x<0.45; however, it is considerably higher for larger Ge mole fractions due to significant reductions in phosphorus activation. Lower temperatures (~500°C), as well as lower implant doses, are sufficient to achieve low resistivities in boron-implanted poly-Si_1-xGe_x films, compared to poly-Si films. The work function of P⁺ poly-Si_1-xGe_x decreases significantly (by up to ~0.4 Volts), whereas the work function of N⁺ poly-Si_1-xGe_x decreases only slightly, as Ge content is increased. Estimates of the energy bandgap of poly-Si_1-xGe_x show a reduction (relative to the bandgap of poly-Si) similar to that observed for unstrained single-crystalline Si_1-xGe_x for a 26% Ge film, and a reduction closer to that observed for strained single-crystalline Si _1-xGe_x for a 56% Ge film. The electrical properties of poly-Si_1-xGe_x make it a potentially favorable alternative to poly-Si for P⁺ gate-material applications in metal-oxide-semiconductor technologies and also for p-channel thin-film transistor applications     

Highly reliable polysilicon oxide grown by electron cyclotronresonance nitrous oxide plasma

Highly reliable inter-polysilicon oxide (polyoxide) for nonvolatile memory applications has been achieved using electron cyclotron resonance (ECR) N₂O-plasma. It is demonstrated that the N₂O-plasma polyoxide grown on doped poly-Si has a low leakage current and high breakdown field due to a smooth polyoxide/poly-Si interface and nitrogen incorporation during oxidation. Moreover, the polyoxide has much less electron trapping and over one order larger charge-to-breakdown (Q_bd) up to 10 C/cm² than thermal polyoxide. The N₂O-plasma polyoxide can be a good choice for the interpoly dielectric of nonvolatile memories     

Electrical characteristics of new LDD poly-Si TFT structuretolerant to process misalignment

A new lightly doped drain (LDD) poly-Si TFT structure having symmetrical electrical characteristics independent of the process induced misalignment is described in this paper. Based on the experimental results, we have established that there is no difference between the bi-directional I_D-V_G characteristics, and a low leakage current, comparable to a conventional LDD poly-Si TFT, has been maintained for this new poly-Si TFT. The maximum ON/OFF current ratio of about 1×10⁸ is obtained for the LDD length of 1.0 μm. In addition, the kink effect in the output characteristics has been remarkably improved in the new TFTs in comparison to the conventional non-LDD single- or dual-gate TFTs     

Inverse staggered poly-Si and amorphous Si double structure TFT'sfor LCD panels with peripheral driver circuits integration

Inverse staggered polycrystalline silicon (poly-Si) and hydrogenated amorphous silicon (a-Si:H) double structure thin-film transistors (TFT's) are fabricated based on the conventional a-Si:H TFT process on a single glass substrate. After depositing a thin (20 nm) a-Si:H using the plasma CVD technique at 300°C, Ar⁺ and XeCl (300 mJ/cm²) lasers are irradiated successively, and then a thick a-Si:H (200 nm) and n⁺ Si layers are deposited again. The field effect mobilities of 10 and 0.5 cm ²/V·s are obtained for the laser annealed poly-Si and the a-Si:H (without annealing) TFT's, respectively