Open-loop full-digital duty cycle correction circuit

The duty cycle of the clock is corrected to be 50% by an open-loop full-digital duty cycle correction (DCC) circuit. Due to its open-loop and full-digital architecture, the DCC completes its operation in less than five clock cycles and can be turned off during power-down state without any concern about losing its information. The DCC has been implemented in a 0.35 /spl mu/m CMOS process and the measured accuracy is /spl plusmn/0.8% for /spl plusmn/10% input clock duty error.     

CMOS on-chip clock for digital signal processors

An on-chip clock for frequencies up to 190 MHz is presented. This clock generator can be used for application specific digital signal processors which are clocked faster than the off-chip system clock. It is useful for both processors with a few cycles per sample or for high frequency bit-serial processors which need a large number of cycles.<>     

限制占空比的螺线管保护电路

在正常工作期间,汽车组装线的激光测量系统中的几个对安全性很关键的螺线管需要得到针对内部过热的保护。在60秒激活之后,螺线管在下一次激活之前需要180秒钟的冷却。一种显然直截了当的保护电路包含一个基于微控制器的计时器、一些支持元件、一个用C 写的短程序。但是,这个项目需要评估和选择合适的微控制器,需要购买或租借一个器件编程器,并需要花相当多时间来对微控制器编程并评估它的运行的危险性。     

数字钟电路的设计

数字钟是采用数字电路实现的计时装置,主要介绍了555定时器构成的多谐振荡电路作为时钟源的数字钟的基本组成和工作原理。电路元件大多为中小规模集成电路,是现下较为流行的数字钟的制作方案。     

High-performance single clock cycle CMOS comparator

A novel comparison algorithm is introduced, which uses a parallel MSB checking method instead of the traditional priority-encoding based comparison algorithm. Fast dynamic NOR gates are used instead of high-fanin NAND gates and this results in significant improvement in performance over the traditional design. The design was realised in AMS 0.35 /spl mu/m technology. It is shown that the proposed design is 22% faster than the existing fastest single-cycle comparator based on priority encoder.     

Clock duty cycle adjuster circuit for switched capacitor circuits

A pulse width locked loop, which can be used to generate an output clock with a wide range of duty cycle (25 to 75%) precisely, from a single-ended input clock with any duty cycle (25 to 75%) is explained. Measurement results of an application of this loop, in pipelined data converters, are reported     

ASMD with duty cycle correction scheme for high-speed DRAM

An analogue synchronous mirror delay with duty cycle-correction scheme (ASMDCC), to improve the data transmission performance between DRAM and system, is proposed. The ASMDCC achieves duty cycle correction and clock synchronisation at once within two clock cycles, by using a half value current source. The simulation results show the duty cycle of the internal clock is stabilised with less than ±100 ps deviation from 50% for the wide duty cycle range     

Analog phase measuring circuit for digital CMOS ICs

A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed     

70-Gb/s amplitude-shift-keyed system with 10-GHz clock recovery circuit using duty cycle division multiplexing

The performance of ASK over DCDM for up to seven channels is reported. The aggregate bit rate of 70 Gb/s is achieved with only 160-GHz modulation bandwidth. The clock and data recovery are realized at 10-GHz clock rate, which is very economic and efficient. At 7 × 10 Gb/s, the worst receiver sensitivity of −10 dBm, OSNR of 41.5 dB and chromatic dispersion tolerance of ±7 ps/nm are achieved. Whereas, for the best channel, the receiver sensitivity, OSNR, and chromatic dispersion tolerance are −23.5 dBm, 29 dB, and ±36 ps/nm, respectively.     

数字时钟电路的设计与仿真

数字时钟设计既是电子教学中最为典型的综合性实验之一,也在商业领域有着极为广泛地应用。文中介绍了一种以74LS190同步可预置的十进制可逆计数IC为主功能芯片,联合其他逻辑门器件共同实现数字时钟功能的电路。该电路包含4个子模块,分别是1Hz脉冲产生电路、计数电路、手动校时电路和整点报时电路。设计过程中利用EWB5.0软件仿真,既提高了设计效率,又节约了设计成本。经验证,该电路工作稳定可靠,达到了预期的效果。     

一种占空比可调的两相非重叠时钟发生器

本文通过调谐压控振荡器输出信号的占空比,直接产生了两相非重叠时钟信号。这一设计集振荡信号发生与非重叠时钟产生于一身,突破了传统标准电路的设计思路。本项工作获得了20%~80%的信号占空比可调范围,同时还实现了两相信号之间不重叠时间间隔的可调谐。利用SMIC 0.18μm 1P6M CMOS工艺,所需电源电压为1.8V,整个电路仅需30个晶体管。     

数字钟实验电路的设计与仿真

基于Multisim 10软件对数字钟电路进行设计和仿真。采用555定时器产生秒时钟信号,用时钟信号驱动计数电路进行计数,将计数结果进行译码,最终在LED数码管上以数字的形式显示时、分、秒时间。     

A floating gate CMOS signal conditioning circuit for nonlinearity correction

A high-speed signal conditioning circuit is presented that can be programmed for correction of nonlinearity in a sensor signal processing system. The function of the circuit is based on piecewise linear principles. Post-fabrication programming to adapt to existing nonidealities is done with floating gate devices fabricated in standard technology. Modeling of the sensor nonideality is not required. The circuit is a voltage-to-current converter with an input range of the full power-supply voltage swing. In a 12-module implementation in 2-µm CMOS technology less than 0.5% error over rail-to-rail input range and a speed of 10 MHz were achieved. The circuit is useful where a signal from a sensor with nonlinearity and high variation in its parameters has to be conditioned for further processing.1. The MOSIS Project, USC/ISI, 4676 Admiralty Way, Marina del Rey, CA 90292-6695.This work is supported by an NSF-Research Initiation Award, Grant MIP-90 11360, and by Analog Devices Inc.     

A CMOS clock recovery circuit for 2.5-Gb/s NRZ data

This paper describes a phase-locked clock recovery circuit that operates at 2.5 Gb/s in a 0.4-μm digital CMOS technology. To achieve a high speed with low power dissipation, a two-stage ring oscillator is introduced that employs an excess phase technique to operate reliably across a wide range. A sample-and-hold phase detector is also described that combines the advantages of linear and nonlinear phase detectors. The recovered clock exhibits an rms jitter of 10.8 ps for a PRBS sequence of length 2⁷-1 and a phase noise of -80 dBc/Hz at a 5-MHz offset. The core circuit dissipates a total power of 33.5 mW from a 3.3-V supply and occupies an area of 0.8×0.4 mm²     

A portable clock multiplier generator using digital CMOS standardcells

High frequency clock rate is a key issue in today's VLSI. To improve performance on-chip, clock multipliers are used. But it is a difficult task to design such circuits while maintaining low cost. This paper presents a circuit fabricated to test a new method of clock frequency multiplication. This new approach uses a digital CMOS process in order to implement a fully integrated digital delay locked loop. This multiplier does not require external components. Moreover, as it is primarily intended for ASIC design, it is generated by a parameterized generator written in C which relies on a portable digital standard cell library for automatic place and route. The design based on the delay locked loop allows the clock waveform to reach its operating point faster than conventional methods. Special techniques enable high multiplication factors (between 4 and 20) without compromising the timing accuracy. With a clock multiplier of 20, in 1 μm CMOS process and a 5 V supply voltage, a 170 MHz clock signal has been obtained from a 8.5 MHz external clock with a measured jitter lower than 300 ps     

Verilog HDL数字钟电路的设计研究

使用编程软件实现数字钟电路的设计过程,令电路自动实现与时间相关的各项功能,Verilog HDL是一种解释电路行为的编程语言,与C语言具有一定相似性,在数字逻辑电路中多有使用,通过多功能接口实现预期功能,既满足编程建模需要,又能令程序代码具有延展性与兼容性,并可实时完成对功能的修改,使编程过程具有简洁特点,将Veril...     

Hot-carrier-reliability design rules for translating devicedegradation to CMOS digital circuit degradation

Long term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict CMOS digital circuit speed degradation from transistor DC stress data. Initial fast degradation is noted and attributed to the “zero crossing” effect caused by PMOSFET current enhancement. Saturation drain current, measured at V_gs=V_ds=Vdd/2, is a better monitor for CMOS circuit hot-carrier reliability. We present generalized hot-carrier-reliability design rules, lifetime and speed factors, that translate DC device lifetime to CMOS digital circuit lifetime. The design rules can roughly predict CMOS circuit degradation during the initial design and can aid reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors are found to obey 4/ft_rise and 10/ft_fall, respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor while, for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET lifetime factors are 120 and 300, respectively     

单周期控制的功率因数校正电路设计

单周期控制是一种大信号、新颖的非线性PWM控制技术,其优点是能够自动消除一个周期内的稳态和瞬态误差,动态响应快,具有结构简单、控制精度高、控制性能不受电源参数变化影响.阐述一了单周期控制的工作原理,并在此基础上设计了以IR1150为控制芯片的200 W功率因数校正电路.实验结果表明.该电路简单可靠,外围元件少,功率因数超过0.98.系统性能优越.     

A synthesizable pseudo fractional-N clock generator with improved duty cycle output

A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13 μm CMOS technology and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146 μW at 304 MHz.