CAN总线中CRC原理及Verilog实现

CAN,即控制器局域网,是国际上应用最广泛现场总线之一。在CAN网络中传输报文时,噪声干扰或传输中断等因素往往使接收端收到的报文出现错码。为了及时可靠地把报文传输给对方并有效地检测错误,需要采用差错控制。本文详细介绍了CAN总线中循环冗余校验码的差错控制原理及其实现方法。     

基于C++的循环冗余校验协议算法实现

研究CRC循环冗余校验原理和实现方法,对基于C++语言的循环冗余校验算法进行重点研究。该CRC算法通过实际上机验证表明,检错重传后通信误码率降低至10-15以下,满足实际应用要求。     

循环冗余校验算法的查表法实现方法

介绍循环冗余校验算法的原理,分析循环冗余校验算法传统的移位计算法,并在此基础上推导出查表计算法,并用C语言实现该方法。与使用传统的移位计算法相比,使用查表法进行循环冗余校验,大大提高计算速度。     

基于流水线的FFT快速计算方法与实现技术

针对目前CDMA快速码捕获系统对捕获速度要求越来越高,在分析快速傅里叶算法理论的基础上,结合FPGA(Field Programmable Gate Array)的独特硬件结构,提出一种基于流水线的FFT(Fast Fourier Transform)快速实现方法,并对该方法进行了matlab仿真、ISE仿真和FPGA实验.研究结果证明:相比于传统的FFT实现方法,在保证计算精度的基础上,该方法实现了FFT计算数据的连续输入与输出.减小了捕获时延,缩短了至少1/3的计算时间,在100 MHz时钟时,完成4096点的FFT运算只需要42.05μs,为高速信号处理系统提供了一种更好的时频转换方法.     

S7-200PLC字节型CRC表驱动算法的实现

循环冗余码校验CRC是计算机通讯及测控领域中最常采用的数据校验方法之一,CRC方法能够很好地降低数据传输的误码率.文章简单介绍了CRC算法的原理和校验规则,针对字节型CRC算法,采用一种直观、紧凑、易于理解的表驱动字节型算法,通过实例演绎了算法的实现过程.同时,设计了S7-200 PLC的字节型CRC表驱动算法的程序.     

基于曙光1000A的并行查询核心系统的设计与实现

根据曙光１０００Ａ的特点，提出了查询核心系统的设计方案；经过分析比较，选定了数据划分方法，确定了ＳＱＬ子集。在此基础上，研究了物理库设计、并行事务管理、查询优化器的设计和事务的调度方法，旨在为在曙光１０００Ａ上建造并行数据库系统奠定基础。     

基于FPGA的CRC算法和VHDL设计

信息在传递过程中虽然扩频技术有利于克服多径衰落以提高信息传输的质量,但信道中的加性干扰不能通过均衡等方法完全消除,因此在一个实用的通信系统中,必须采取一定的措施来纠正错误,降低系统的误码率,信道编码就是一种非常有效的措施。本文介绍了一种基于FPGA的CRC算法的实现方案,该算法适合于反向业务信道的信道编码,并给出了具体的设计方法。     

基于SMS短消息传输的远端控制技术及其实现

本文主要叙述了基于短消息传输机制的远端控制技术原理及其系统的实现方法.提出并定义了一个可靠的并且具有纠错功能的命令协议子集.基于DSP芯片和SMS短消息模块实现了远端控制.该系统在汽车防盗中得到了极其成功的应用.     

基于PC集群机并行图形绘制技术的研究

由廉价PC机组成集群机的并行图形绘制系统具有高性价比、扩展性好、升级方便、适用面广等诸多优点。为此，本文结合近几年来这方面的研究成果，探讨基于PC集群机的并行图形绘制技术。     

CRC-32的算法研究与程序实现

循环冗余校脸CRC(Cyclic Redundancy Check)是一种编码简单,且高效、可靠的差错控制方法,广泛应用于工业测控及数据通信领城。首先分析了CRC的校验原理、冗余位的产生方法、性能分析。然后以CRC-32为例,给出了软件实现算法的C语言代码。     

Optoelectronic pipeline architecture for morphological image processing

An optoelectronic architecture for morphological image processing is presented. The architecture uses the pipelining principle, with its stages being implemented by use of optical fiber-based programmable logic arrays. These arrays are characterized by their high fan-in and fan-out factors, which make them suitable for implementing morphological operations with large structuring elements without decomposition. The pipeline has fewer stages and clock skew can be avoided, thus making the use of higher clock speeds and throughputs possible.     

A line-based parallel memory for QCA implementation

Quantum-dot cellular automata (QCA) has been widely advocated as a new device architecture for nanotechnology. Using QCA, the innovative design of digital systems can be achieved by exploiting the so-called capability of processing-in-wire, i.e., signal manipulation proceeds at the same time as propagation. QCA systems require low power together with the potential for high density and regularity. These features make QCA an attractive technology for manufacturing memories in which the in-wire paradigm can be exploited for storage purposes. This paper proposes a novel parallel memory architecture for QCA implementation. This architecture is based on storing information on a QCA line by changing the direction of signal flow among three clocking zones. Timing of these zones requires two additional clocks to implement a four-step process for reading/writing data to the memory. Its operation has been verified by simulation. It is shown that the requirements for clocking, number of zones, as well as the underlying CMOS circuitry are significantly reduced compared with previous QCA parallel architectures.     

Reduced processing element architecture for parallel local image processing

Abstract

The object of this paper is to propose new architecture which can reduce the number of processing elements for parallel local image processing under the premise of real‐time performance. For large‐sized local image processing, this architecture will save much space as it is suitable for being designed into VLSI chip. For example, the traditional parallel architecture will use 9 PEs for a 3×3 convolution, while the Reduced Processing Element Architecture (RPEA) only requires 2 PEs to achieve the real‐time performance.     

Unit-delay focusing architecture and integrated-circuit implementation for high-frequency ultrasound

High-frequency ultrasound (above 10 MHz) has been used successfully in many medical applications, including eye, skin, gastrointestinal, intravascular, and Doppler flow imaging. Most of these applications use single-element transducers, thereby imposing a tradeoff between resolution and depth of field. Fabrication difficulties and the need for high-speed electronic beamformers have prevented widespread use of arrays at high frequencies. In this paper, a unit-delay focusing architecture suitable for use with high-frequency ultrasound annular arrays is described. It uses a collection of identical, active delay cells that may be simultaneously varied to accomplish focusing. Results are presented for an analog integrated circuit intended for use with a five-element, 50-MHz planar annular array. Focusing is possible over an axial range for which the ratio of maximum to minimum f-number is 2.1. Unit-delay architectures also are described for curved annular arrays and linear arrays.     

Unilateral contact problem for finite bodies - parallel implementation

A numerical solution of the three dimensional frictionless contact problem and its data parallel implementation on the Connection Machine system CM-2 is presented. The numerical solution is obtained by means of boundary element discretization of a variational inequality and related extremum principle; the associated Green's function is approximated by means of standard direct boundary element procedure. A numerical method is applicable to any kind of geometry of the contacting bodies under arbitrary loading. The example presented illustrate a distinct ability of the method to capture the influence of the shape and the size of a body on the contact area and the pressure acting in it. It has been demonstrated that the symmetry properties of the Green's operator hold only asymptotically for the discretized problem.     

Development of a parallel processing multi-agent architecture for a virtual CIM system

Global manufacturing enterprises tend to rely on fully integrated manufacturing systems to satisfy constantly changing market requirements. In addition, small to medium enterprises are in a dilemma when competing with large organizations. Virtual computer-integrated manufacturing (VCIM) is a realistic concept that can provide the integration requirements for the globally distributed manufacturing resources and it has the potential to satisfy the market requirements of small to medium enterprises. The vision of the VCIM is to improve the efficiency and effectiveness of manufacturing enterprises by seamlessly integrating globally distributed manufacturing resources as much as possible. Meanwhile, intelligent agent technology provides a better means to implement distributed components as integrated application systems. The paper provides a parallel processing multi-agent architecture to support a global integrated manufacturing system in the form of the VCIM. In this architecture, a three-layered structure is proposed to accommodate all the agents no matter where they are located. Multiple Facilitator agents are proposed with similar functionalities to smooth the information flow across the integrated system in a parallel connection manner. In addition, a multi-agent VCIM model that describes the agent identification approaches for VCIM, Java environment implementation approaches and a simulation system to demonstrate the parallel processing multi-agent architecture are also discussed.     

Quasi-cyclic LDPC code construction for implementation of parallel joint row-column decoding

针对普通低密度校验(LDPC)码制约行列联合(JRC)译码算法并行度提高的问题,基于块渐进边增长(BPEG)算法,提出了一种用于并行JRC译码的LDPC码构造方法.该方法构造的准循环LDPC码(QC-LDPC)基矩阵由含r(r为大于1的整数)行的行组构成,允许一个行组内的r行进行并行JRC运算.仿真结果表明,用上述构造方法构造的LDPC码与BPEG码的误码性能相当.硬件实现表明,用此构造码的并行译码器的速率能达到典型传统准循环译码器的3倍以上,为面向译码器的LDPC码构造提供了范例.     

Optoelectronic parallel watershed implementation for segmentation of magnetic resonance brain images

An optoelectronic implementation for the morphological watershed transform is proposed. Fiber-optic programmable logic arrays are used in the implementation because of their high fan factors at high clock speeds. Image segmentation is one of the main applications of the watershed transform. Based on the optoelectronic implementation, an algorithm for the segmentation of axial magnetic resonance (MR) head images to extract information on brain matter is presented. Simulation results for the different steps of the segmentation process are presented.     

分步式并行MQ编码及其VLSI设计

针对MQ编码的环路反馈结构的高复杂度对实现快速图像压缩硬件的限制,研究分析了MQ编码的基本算法,提出了"区间编码"和"位填充"之间有一定的独立性,可用先进先出(FIFO)管道连接后并行处理的思想,并设计了一种适合MQ编码算法特点的异步流水线与有限状态机(FSM)相结合的分步式并行结构.该结构简单合理,FIFO管道的引入可支持异步流水电路,FSM的动态优化策略有效地防止了流水的阻塞,复杂环路的逐层分解显著降低了编码的反馈效应,根据程序运行过程中的数据操作动态特征,利用概率统计规律和状态机分割减小了系统的关键路径长度.该结构的资源利用率高,现场可编程门阵列(FPGA)原型系统最高时钟工作频率为233MHz,吞吐率与其它同类结构相比有明显提高,达到116.5Mbps.     

A parallel bi-level multidisciplinary design optimization architecture with convergence proof for general problem

Quite a number of distributed Multidisciplinary Design Optimization (MDO) architectures have been proposed for the optimal design of large-scale multidisciplinary systems. However, just a few of them have available numerical convergence proof. In this article, a parallel bi-level MDO architecture is presented to solve the general MDO problem with shared constraints and a shared objective. The presented architecture decomposes the original MDO problem into one implicit nonlinear equation and multiple concurrent sub-optimization problems, then solves them through a bi-level process. In particular, this architecture allows each sub-optimization problem to be solved in parallel and its solution is proven to converge to the Karush–Kuhn–Tucker (KKT) point of the original MDO problem. Finally, two MDO problems are introduced to perform a comprehensive evaluation and verification of the presented architecture and the results demonstrate that it has a good performance both in convergence and efficiency.