基于理想模型和遗传算法的模拟电路自动化设计研究

受模拟电路人工设计启发,以 MOSFET 电路为例提出一种模拟电路的自动化设计方法。首先以 MOSFET 的理想模型为基础,利用遗传算法(GA)产生电路拓扑并优化其参数;然后用实际元件替换其理想模型,通过少量调整即可得到最终电路。GA 在电路拓扑生成和参数优化方面具有优势,理想模型可有效缩小算法的搜索空间,因而所提方法在最优电路拓扑生成和加快电路设计速度两方面具有更为明显的优势。通过对三次方运算电路的设计,证实了所提方法的有效性。     

A generalized fault simulator for combinational logic circuits

A generalized approach to the design of fault simulator using a library of simulation primitives is presented in this paper. A comprehensive set of simulation primitives has been developed using C programming language on the IBM PC. This library of simulation primitives has been used in realizing a fault simulator for automatic test pattern generation in combinational logic circuits. The fault simulator employs a combination of random pattern generation, concurrent fault simulation and the FAN algorithm for generating the complete set of test vectors to cover all the faults in the fault dictionary of the circuit under test. The library of simulation primitives is general enough to facilitate the development of fault simulators using any other test algorithms such as DALG or PODEM.     

Controllable decoding for automated analog circuit structure design

The decoding scheme is a major problem in automated analog circuit topology synthesis since decoding schemes bias synthesized circuit structures. However, the proper decoding scheme varies depending on the method to realize a given function. In this paper, a controllable decoding scheme is proposed in which the method to realize a function is controlled by a set of prototype circuits. Thus, the system can generate different types of analog circuits in a unified method. The prototype circuits are designed by a human and suggested to the system as hints of configurations of new analog circuits to be synthesized by the system. In the synthesis process, the information on circuit connections is stored as sub-circuits extracted from the prototype circuits. A genetic algorithm is then used to search for an optimum combination of the sub-circuits that achieves the desired electronic specifications. The combinations of sub-circuits are generated with a proposed technique where the terminals of the sub-circuits are shared. The capabilities of the proposed method are demonstrated through synthesis examples of a cubing circuit synthesis as a current-mode design and a logic circuit synthesis as a voltage-mode.The authors would like to thank the reviewers for their valuable comments. The authors would like to express special thank to Dr. Andrew M. Abo for English corrections.     

A subthreshold MOS neuron circuit based on the Volterra system.

We present an analog neuron circuit consisting of a small number of metal-oxide semiconductor (MOS) devices operating in their subthreshold region. The dynamics of the circuit were designed to be equivalent to the well-known Volterra system to facilitate developing the circuit for a particular application. We show that a simple nonlinear transformation of system variables in the Volterra system enables designing a neuron-like oscillator, which can produce sequences in time of identically shaped pulses (spikes) by using current-mode subthreshold MOS circuits. We present experimental results of the fabricated neuron circuits as well as an application in an inhibitory neural network, where the neurons compete with each other in the frequency and time domains.     

Genetically Evolved Neural Networks for Fault Classification in Analog Circuits

A new fault classification system for analog circuits is presented. The proposed system utilises the pattern recognition potential of neural networks and the population-based search strategy of genetic algorithms in detecting and isolating faults in analog circuits. Features that characterise the circuit behaviour under fault-free and fault situations are first simulated or measured. An unsupervised fault-grouping algorithm that estimates the overlaps between different faults in the features space is then introduced. Accordingly, a suitable training set is constructed and employed to train a population of genetically evolved neural networks to recognise circuit faults. A two-phase analog fault classification strategy is also developed. Experimental results demonstrate the high classification accuracy of the proposed system. ID="A1" Correspondence and offprint requests to: M.A. El-Gamal, Department of Engineering Physics Mathematics, Cairo University, Giza, Egypt Email: mhgamal@alpha1-eng.cairo.eun.eg     

现代模拟电路故障诊断技术发展综述

模拟电路的故障率长期以来居高不下,但模拟电路由于其客观世界信号本质无法完全被数字电路取代,模拟电路的可靠性也成为制约电路系统可靠性的关键因素。主要针对模拟电路的软故障诊断方法进行了研究,分析了模拟电路在故障诊断中的难点,分别对传统和智能化的故障诊断发展和研究现状进行了综述,展望了未来模拟电路故障诊断的发展趋势。     

An analog circuit design environment based on cooperating blackboard systems

A novel approach to design automation for analog circuits is presented. The prototype implementation-OASE-has been realized as a set of cooperating expert systems with blackboard architecture. The circuit specific knowledge bases use hybrid representation schemes and are strictly separated from an execution engine containing the necessary control knowledge. This alleviates the knowledge acquisition process as well as the extension and maintenance of existing knowledge. OASE has been developed as a design assistant, featuring different levels of interactivity, a hierarchical design style and fully embedded algorithmic standard tools. In its current version it is able to design a broad range of different CMOS operational amplifiers.     

Qualitatively modelling the effects of electrical circuit faults

This paper presents a new method for the qualitative analysis of electrical circuit behaviour. This paper shows that a qualitative representation of electrical resistance provides a good intuitive model for reasoning about gross electrical effects due to connectivity faults. The motivation is to produce tools to assist engineers in the identification and analysis of circuit failures that have safety implications. This includes work in hazard analysis, safety-critical systems, and failure mode effects analysis (FMEA). The analysis algorithms efficiently locate state changes in circuits and assign qualitative symbols for voltage and current flow to all components. The input, Δr, is a list which specifies qualitative resistance changes between the nodes of a previously defined circuit and the output is a pair, (P_a, P_d), of sets of activated and deactivated paths, identifying the components that have changed state. The system has a layered priority approach precisely in keeping with failure mode analysis tasks and has been successfully tested in real applications.     

基于多修改点胚胎键合图的模拟电路自动设计*

采用键合图表示电路系统,研究了基于两种不同胚胎键合图的模拟电路进化设计方法。该方法利用遗传编程开放式拓扑搜索的特点,模拟一组特征值,并用键合图和遗传编程对该组初始胚胎进行进化,总结了两种结构对进化设计结果的影响,得出由三个可修改点胚胎进化的电路优于由一个可修改点胚胎进化的电路,三个可修改点胚胎进化具有更平衡的结构。最后进化设计了一个模拟带阻滤波器,进一步证明了该方法的可行性和有效性。     

A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity

We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.     

A two-variable silicon neuron circuit based on the Izhikevich model

The silicon neuron is an analog electronic circuit that reproduces the dynamics of a neuron. It is a useful element for artificial neural networks that work in real time. Silicon neuron circuits have to be simple, and at the same time they must be able to realize rich neuronal dynamics in order to reproduce the various activities of neural networks with compact, low-power consumption, and an easy-to-configure circuit. We have been developing a silicon neuron circuit based on the Izhikevich model, which has rich dynamics in spite of its simplicity. In our previous work, we proposed a simple silicon neuron circuit with low power consumption by reconstructing the mathematical structure in the Izhikevich model using an analog electronic circuit. In this article, we propose an improved circuit in which all of the MOSFETs are operated in the sub-threshold region.     

Time-domain analysis methodology for large-scale RLC circuits and its applications

With soaring work frequency and decreasing feature sizes, VLSI circuits with RLC parasitic components are more like analog circuits and should be carefully analyzed in physical design. However, the number of extracted RLC components is typically too large to be analyzed efficiently by using present analog circuit simulators like SPICE. In order to speedup the simulations without error penalty, this paper proposes a novel methodology to compress the time-descritized circuits resulted from numerical integration approximation at every time step. The main contribution of the methodology is the efficient structure-level compression of DC circuits containing many current sources, which is an important complement to present circuit analysis theory. The methodology consists of the following parts: 1) An approach is proposed to delete all intermediate nodes of RL branches. 2) An efficient approach is proposed to compress and back-solve parallel and serial branches so that it is error-free and of linear complexity to analyze circuits of tree topology. 3) The Y toπtransformation method is used to error-free reduce and back-solve the intermediate nodes of ladder circuits with the linear complexity. Thus, the whole simulation method is very accurate and of linear complexity to analyze circuits of chain topology. Based on the methodology, we propose several novel algorithms for efficiently solving RLC-model transient power/ground (P/G) networks. Among them, EQU-ADI algorithm of linear-complexity is proposed to solve RLC P/G networks with mesh-tree or mesh-chain topologies. Experimental results show that the proposed method is at least two orders of magnitude faster than SPICE while it can scale linearly in both time- and memory-complexity to solve very large P/G networks.     

基于结构矩阵的电路网表编码方法的研究

在模拟电路演化领域,电路知识表示是首要解决的问题。网表编码操作简单,对于拓扑结构没有限制,但是网表编码会在种群初始化和遗传操作过程中产生大量的非法电路个体。为解决这一问题,提出结构矩阵,并总结出合法电路结构矩阵所具有的性质,以结构矩阵为规范设计出合适的种群初始化步骤和能够用于网表编码的结构交叉算子,通过演化来验证效果,实验结果显示该方法能够较好地解决网表编码所存在的问题。     

A new wide range Euclidean distance circuit for neural network hardware implementations

In this paper, we describe an analog very large-scale integration (VLSI) implementation of a wide range Euclidean distance computation circuit - the key element of many synapse circuits. This circuit is essentially a wide-range absolute value circuit that is designed to be as small as possible (80 /spl times/ 76 /spl mu/m) in order to achieve maximum synapse density while maintaining a wide range of operation (0.5 to 4.5 V) and low power consumption (less than 200 /spl mu/W). The circuit has been fabricated in 1.5-/spl mu/m technology through MOSIS. We present simulated and experimental results of the circuit, and compare these results. Ultimately, this circuit is intended for use as part of a high-density hardware implementation of a self-organizing map (SOM). We describe how this circuit can be used as part of the SOM and how the SOM is going to be used as part of a larger bio-inspired vision system based on the octopus visual system.     

基于Fisher准则函数的相关向量机模拟电路故障诊断*

针对模拟电路故障与特征间存在的模糊组及交叠、分类效果不理想的情况,提出基于Fisher准则函数的最佳聚类数自适应估计方法和基于稀疏贝叶斯相关向量机(RVM)理论的模拟电路故障诊断模型,采用模糊核聚类选择最优可诊断故障集,然后在贝叶斯框架下对故障进行分类.该模型可以对分类函数的权重进行推断,辅助进行诊断决策,提高了RVM...     

基于Simulink的数模混合电路仿真平台设计与实现

针对数模混合电路仿真精度与性能之间的矛盾问题和仿真工业级复杂数模混合电路时仿真工具存在主流芯片和电路模块不足问题,提出了一种粘合模式的数模混合仿真平台模型架构,基于该架构设计并实现了一种基于Simulink软件,通过嵌入数字电路和模拟电路主流仿真引擎获得充足主流芯片和电路模块支持的数模混合电路仿真平台,设计了一种结合了拓扑排序算法的仿真控制方式,实现了对工业级复杂电路进行流程化、模块化的数模混合仿真;最后通过一个能够时序上可以逻辑拆分的典型数模混合电路仿真验证了仿真平台的有效性。     

Automated synthesis of multiple analog circuits using evolutionary computation for redundancy-based fault-tolerance

Analog circuits are one of the most important parts of modern electronic systems and the failure of electronic hardware presents a critical threat to the completion of modern aircraft, spacecraft, and robot missions. Compared to digital circuits, designing fault-tolerant analog circuits is a difficult and knowledge-intensive task. A simple but powerful method for robustness is a redundancy approach to use multiple circuits instead of single one. For example, if component failures occur, other redundant components can replace the functions of broken parts and the system can still work. However, there are several research issues to make the redundant system automatically. In this paper, we used evolutionary computation to generate multiple analog circuits automatically and then we combined the solutions to generate robust outputs. Evolutionary computation is a natural way to produce multiple redundant solutions because it is a population-based search. Experimental results on the evolution of the low-pass, high-pass and band-stop filters show that the combination of multiple evolved analog circuits produces results that are more robust than those of the best single circuit.     

基于边界扫描的混合信号电路可测性结构设计

在深入研究IEEE1149.1及IEEE1149.4标准的基础上,设计并实现了符合标准的混合信号电路边界扫描可测性结构各组成部分,包括测试访问口控制器、数字边界扫描单元、模拟边界扫描单元、测试总线接口电路及测试寄存器;构建验证电路进行了测试验证。测试结果表明,所设计的混合信号电路可测性结构是可行的,并可以应用到混合信号电路中提高电路的可测试性。     

基于模糊SVM和虚拟仪器的模拟电路故障诊断研究

基于模糊支持向量机理论构建模拟电路故障诊断网络,采用虚拟仪器技术开发故障诊断平台;通过对电路仿真软件与实际测量得到的数据进行分析,选取一种自适应小波变换特征提取方法对电路进行故障特征提取,提取电路输出响应的6个低频系数构成故障特征向量并作为FSVM诊断网络的学习样本,诊断网络采用C-SVM算法.规则化参数墩为200;在LabVIEW软件中调用以MAT-LAB-M文件编写的特征提取与故障诊断算法,将模拟电路的故障定位到元件级;最后,将网络的诊断结果与BP神经网络诊断方法做了对比,证明基于虚拟仪器的模糊SVM模拟电路诊断方法在故障诊断速度与准确性方面都具有明显优势,平均故障识别率达到90%以上.