Domain-decomposed MEI method for field computation in single andmultiple regions

The domain-decomposed measured equation of invariance (DDMEI) method is proposed for field computation in single and multiple regions. The whole computing domain is partitioned into a cluster of subdomains. For single region problems, this partition splits the computing domain into many subdomains artificially. For multiple regions problems, these subdomains can be taken as those regions separated geometrically. The contribution of sources residing in a subdomain is approximated by a set of sources selected out of these original sources with greatly reduced amounts. The approximation is implemented numerically by the MEI method. The resultant MEI matrices are blocked matrices and each submatrix is highly sparse. Approaches and numerical results are given respectively for the applications of the DDMEI to the scattering of single conducting cylinders, radiation of wire arrays, and capacitance matrix computation for multiconductor transmission lines. The DDMEI proposed in this paper is an improved version of the surface current MEI method (SCMEI). Compared with the SCMEI, the DDMEI improves the sparsity of the MEI matrices and the feasibility of measuring out the MEI coefficients. Furthermore, the DDMEI makes it possible to apply the kind of on-surface MEI methods (OSMEI) to multiple region problems for the first time     

三维多导体互连结构交扰问题的时域分析

本文利用时域有限差分法对多导体互连结构的交扰问题进行了分析,提取了各端口的S参数.利用AR模型中的Marple方法及参数提取、修正技术对解进行了优化,从而缩短了计算时间,提高了计算的精度.利用超吸收边界条件大大的减少了网格剖分数,节省了计算机的内存.数值结果揭示了导体间的交扰关系.     

Capacitance computations in a multilayered dielectric medium usingclosed-form spatial Green's functions

An efficient method to compute the 2-D and 3-D capacitance matrices of multiconductor interconnects in a multilayered dielectric medium is presented. The method is based on an integral equation approach and assumes the quasi-static condition. It is applicable to conductors of arbitrary polygonal shape embedded in a multilayered dielectric medium with possible ground planes on the top or bottom of the dielectric layers. The computation time required to evaluate the space-domain Green's function for the multilayered medium, which involves an infinite summation, has been greatly reduced by obtaining a closed-form expression, which is derived by approximating the Green's function using a finite number of images in the spectral domain. Then the corresponding space-domain Green's functions are obtained using the proper closed-form integrations. In both 2-D and 3-D cases, the unknown surface charge density is represented by pulse basis functions, and the delta testing function (point matching) is used to solve the integral equation. The elements of the resulting matrix are computed using the closed-form formulation, avoiding any numerical integration. The presented method is compared with other published results and showed good agreement. Finally, the equivalent microstrip crossover capacitance is computed to illustrate the use of a combination of 2-D and 3-D Green's functions     

Capacitance matrix calculation of a wire conductor line: a new FEMapproach

An original finite-element approach is presented to calculate the capacitance matrix of a uniform multiconductor wire line. The examined two-dimensional (2-D) domain is discretized by nodal-based triangular elements where the Laplace equation is solved. A new procedure is developed to take into account the presence of the wires, which are assumed to be located in the vertex nodes of the FEM mesh. Through the proposed procedure, the physical dimensions of the wire cross sections are considered modifying the terms of the local stiffness matrix in the finite elements surrounding the wires. A further modification of the local FEM matrices allows one to consider the logarithmic variation of the electrical potential around the wires. The procedure is efficient from a numerical point of view since it avoids the fine discretization of the nonconductive region surrounding the wire while achieving a good numerical accuracy. Numerical examples are given and compared with the analytical solutions for canonical configurations, including wires with a dielectric cover     

区域分裂法在提取多层介质中多导体三维复杂互连结构电磁参数中的应用

本文首次将区域分裂法（ＤＤＭ）用于多层介质中多导体三维复杂互连结构的电磁参数的提取，可以快速、准确地提取复杂互连结构的静态电容矩阵。由于区域分裂法能肥大问题化为若干独立的小问题，不仅可以缩小计算规划，而且可以在该算法框架下灵活地组合各种三维互连结构，具有很强的灵活性，再充分利用集成电路结构分层的特点，对各个小问题采用最恰当的计算方法，从而可大大减少整体设计所需的时间和存储空间。文中给出的计算结果Ａ     

Methodology for characterization of high-speed multi-conductor metal interconnections and evaluation of measurement errors

Analysis and design of interconnects in high speed integrated circuits and systems involves models in the form of multiconductor transmission lines. The fundamental parameters of those models are matrices of capacitance, (C), inductance, (L), resistance, (R), and conductance (G). We present a methodology for measurement of entries in capacitance matrix. The entries of capacitance matrices can be calculated using numerical solvers of electrostatic fields established under the assumption of suitable biasing of interconnect structures. Numerical calculations of complete field equations are very complex and expensive in terms of computer time, therefore several approximations are made in constructing interconnect dedicated software packages available on the market. Because of these approximations it is necessary to validate the calculations via measurements. Calculation of the off-diagonal entries of capacitance matrix from measurements of "two-terminal" capacitances is strongly corrupted by the measuring errors. The method involves direct capacitance measurement in multi-conductor structures and provides analysis of accuracy.     

A novel dimension-reduction technique for the capacitanceextraction of 3-D VLSI interconnects

In this paper, a new capacitance extraction method called the dimension-reduction technique (DRT) is presented for three-dimensional (3-D) very large-scale integration (VLSI) interconnects. The DRT converts a complex 3-D problem into a series of cascading simple two-dimensional (2-D) problems. Each 2-D problem is solved separately, thus we can choose the most efficient method according to the arrangement of conductors. We have used the DRT to extract the capacitance matrix of multilayered and multiconductor crossovers, bends, vias with signal lines, and open-end. The results are in close agreement with those of Ansoft's SPICELINK and the Massachusetts Institute of Technology's (MIT) FastCap, but the computing time and memory size used by the DRT are several (even ten) times less than those used by SPICELINK and FastCap     

Electrostatic solution for three-dimensional arbitrarily shapedconducting bodies using finite element and measured equation ofinvariance

Differential equation techniques such as the finite element (FE) and finite difference (FD) have the advantage of sparse system matrices that have relatively small memory requirements for storage and relatively short central processing unit (CPU) time requirements for solving electrostatic problems. However, these techniques do not lend themselves as readily for use in open-region problems as the method of moments (MoM) because they require the discretization of the space surrounding the object where the MoM only requires discretization of the surface of the object. A relatively new mesh truncation method known as the measured equation of invariance (MEI) is investigated augmenting the FE method for the solution of electrostatic problems involving three-dimensional (3-D) arbitrarily shaped conducting objects. This technique allows truncation of the mesh as close as two node layers from the object. The MEI views sparse-matrix numerical techniques as methods of determining the weighting coefficients between neighboring nodes and finds those weights for nodes on the boundary of the mesh by assuming viable charge distributions on the surface of the object and using Green's function to measure the potentials at the nodes. Problems in the implementation of the FE/MEI are discussed and the method is compared against the MoM for a cube and a sphere     

基于全电荷格林函数的MEI方法在超高速集成电路互连线参数提取中的应用

本文提出了将全电荷格林函数用于测度不变方程（ＭＥＩ）法中，即将全电荷格林函数代替完全格林函数积分以求得测量函数从而决定测度不变方程．并以这种ＭＥＩ法计算了某些多导体互连线的分布电容矩阵．     

基于分段预留法的互连线二维电容提取技术

随着制造工艺的不断演进、电路规模的不断增大,集成电路逐渐进入后摩尔时代。如何准确快速地进行寄生电容参数提取,对于保证设计质量、减少成本和缩短设计周期变得越来越重要。文章提出了一种基于分段预留法的二维电容提取技术,该技术基于改进的有限差分法,采用非均匀网格划分和求解不对称系数矩阵方程,模拟互连结构横截面,可以高效计算出主导体的单位长度总电容以及主导体和相邻导体之间的单位长度耦和电容。为了验证提出方法的准确性和有效性,进行了一系列验证实验。实验结果表明,提出的互连线二维电容提取技术在寄生电容计算精度上平均提高了140倍,运行时间平均缩了10%。     

芯片内互连线计算中的一种算法实现

文章解决了将"变方向隐式方法的三维时域有限差分法"(3D ADI-FDTD)应用于高速芯片内互连线的电磁场计算中很多关键问题,包括源的产生方案及其数值结构,具体边界吸收条件的差分格式.特别是针对芯片互连线中的多层介质、多导体线的结构,提出了稀疏的矩阵模型和可变网格的划分.数值实验表明,对原有ADI-FDTD方法所做的这些改进,能够在保证适当精度的情况下提高计算速度.     

有耗互连线频变电感提取及等效电路模型

采用二维电感模型，计算了带接地导体的有耗互连线的频变阻抗。阻抗函数用分式多项式近似，并表达为串接的并联电阻、电感的福斯特电路形式。考虑互连线分布电容参数，并根据多个频点阻抗值，用有限数量极点，综合得到互连线单位长度的等效电路模型。采用该模型进行互连线时域响应分析，其结果与改进特征法结果吻合较好，且便于与其他电路模型结合，进行大规模电路的时域分析。     

A multilevel parasitic interconnect capacitance modeling andextraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays     

An efficient solver for the three-dimensional capacitance of theinterconnects in high speed digital circuit by the multiresolutionmethod of moments

The computation of the equivalent capacitances for three-dimensional (3-D) interconnects features large memory usage and long computing time. In this paper, a matrix sparsification approach based on multiresolution representation is applied with the method of moments (MoM) to calculate 3-D capacitances of interconnects in a layered media. Instead of direct expansion of the charge distribution by the orthogonal wavelet basis functions, the large full matrix resulting from discretization of the integral equations is taken as a discrete image and sparsified by two-dimensional (2-D) multiresolution representations. The inverse of the obtained sparse matrix is efficiently implemented by Schultz's iterative approach. Several numerical examples are given and the results obtained show that the proposed method significantly sparsifies the matrix equation and the capacitance parameters computed by the matrix equation with high sparsity agree well with the results of other reports and those computed by an established capacitance extractor FASTCAP     

Surface Current Modelling of the Skin Effect for On-Chip Interconnections

In this paper, the skin effect for 2-D on-chip interconnections is predicted using a recently developed differential surface admittance concept. First, the features of the new approach are briefly recapitulated and details are given for a conductor with rectangular cross-section. Next, the 1-D situation is studied as a limiting case of the 2-D situation. The relationship with a local impedance formulation is investigated and illustrated with a numerical example. Finally, the new method is used to determine inductance and resistance matrices of 2-D on-chip interconnect examples with specifications taken from the international technology roadmap for semiconductors. Extra capacitance data are also provided.     

An efficient method for computing the capacitance matrix ofmulticonductor interconnects in very high-speed integrated circuitsystems

A new method for computing the capacitance matrix of multiconductor interconnects with finite metallization thickness is developed. Converting the vertical wall of the rectangular conductors into the equivalent horizontal strips allows the Green's function in the spectral domain and the FFT algorithm to be used, which makes the method more effective for computing capacitance matrix of the interconnects     

一种基于局部间断Galerkin方法的IC互连线电容提取策略

求解椭圆方程的局部间断Galerkin(LDG)方法具有精度高、并行效率高的优点,且能适用于各种网格。文章提出采用LDG方法来求解IC版图中电势分布函数满足的Laplace方程,从而给出了一个提取互连线电容的新方法。该问题的求解区域需要在矩形区域内部去掉数量不等的导体区域,在这种特殊的计算区域上,通过数值测试验证了LDG方法能达到理论的收敛阶。随着芯片制造工艺的发展,导体尺寸和间距也越来越小,给数值模拟带来新的问题。文章采用倍增网格剖分方法,大幅减小了计算单元数。对包含不同数量和形状导体的七个电路版图,用新方法提取互连线电容,得到的结果与商业工具给出的结果非常接近,表明了新方法的有效性。     

On the two-dimensional capacitance calculation of multiconductor multilayered interconnects

In this paper a method for analysis and modelling of transmission interconnect lines on multilayered dielectric media is presented. The analysis is based on semianalytical layered Green’s function and the electromagnetic concept of free charge density. It allows us to obtain integral equations between electric scalar potential and charge density distributions. These equations are solved by the Galerkin procedure of the Method of Moments. After this, the capacitance matrix of multiconductor interconnect lines in the presence of planar dielectric interfaces is calculated. When there exists no infinite ground plane, we enforce the constraint that the sum of all free charges is zero. The feasibility of the method has been shown by simulations of several transmission-line problems. The results have been compared with reported data obtained by free-space Green’s function method, conformai mapping formulas, generalized method of lines and inverted capacitance coefficient matrix technique. The proposed approach is not inferior to other procedures in terms of generality and memory requirements. At the same time, a reduction of the central processing unit (cpu) time is achieved because the integral equations are solved numerically only on the surface of conductor lines.     

Space-domain Green's function approach to the capacitancecalculation of multiconductor lines in multilayered dielectrics withimproved surface charge modeling

An integral equation method for the calculation of capacitance and inductance matrices is presented. The method is suitable for multiconductor transmission lines embedded in a multilayered dielectric medium on top of a ground plane. Conductors of arbitrary polygonal cross section can be handled, as well as infinitely thin conductors. The method is new in two respects. The kernel of the integral equation is the space-domain Green's function of the layered medium. The accuracy of the solution is enhanced by using basis functions that exactly model the singular behavior of the charge density in the neighborhood of a conductor edge. Numerical examples show the accuracy of the calculations and the complexity of the configurations that can be treated     

A unified RLC model for high-speed on-chip interconnects

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width (W/sub eff/) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new analytical "wall-to-wall" model. The effective width provides a physics-based approach to decompose any 3-D structure into a series of 2-D segments, resulting in an efficient and accurate capacitance extraction. In the inductance model, we use an effective loop inductance approach for an analytic and hierarchical model construction. In particular, we show empirically that high-frequency signals (above multi-GHz) propagating through random signal lines can be approximated by a quasi-TEM mode relationship, leading to a simple way to extract the high-frequency inductance from the capacitance of the wire. Finally, the capacitance and inductance models are combined into a unified frequency-dependent RLC model, describing successfully the wide-band characteristics of on-chip interconnects up to 100 GHz. Non-orthogonal wire architecture is also investigated and included in the proposed model.