Interpolation and decimation of digital signals—A tutorial review

The concepts of digital signal processing are playing an increasingly important role in the area of multirate signal processing, i.e. signal processing algorithms that involve more than one sampling rate. In this paper we present a tutorial overview of multirate digital signal processing as applied to systems for decimation and interpolation. We first discuss a theoretical model for such systems (based on the sampling theorem) and then show how various structures can be derived to provide efficient implementations of these systems. Design techniques for the linear-time-invariant components of these systems (the digital filter) are discussed, and finally the ideas behind multistage implementations for increased efficiency are presented.     

Multirate digital filters, filter banks, polyphase networks, andapplications: a tutorial

The basic concepts and building blocks in multirate digital signal processing (DSP), including the digital polyphase representation, are reviewed. Recent progress, as reported by several authors in this area, is discussed. Several applications are described, including subband coding of waveforms, voice privacy systems, integral and fractional sampling rate conversion (such as in digital audio), digital crossover networks, and multirate coding of narrowband filter coefficients. The M-band quadrature mirror filter (QMF) bank is discussed in considerable detail, including an analysis of various errors and imperfections. Recent techniques for perfect signal reconstruction in such systems are reviewed. The connection between QMF banks and other related topics, such as block digital filtering and periodically time-varying systems, is examined in a pseudo-circulant-matrix framework. Unconventional applications of the polyphase concept are discussed     

Adaptive McClellan transformations for quincunx filter banks

A technique is developed for the design of 2-D nonseparable two-channel filter banks for a quincunx sampling lattice, where the isopotentials of the frequency response can be optimized and adapted to the input signal's statistics. By employing known odd-length symmetric linear phase filter banks as the l-D prototype filters for 2-D filters parameterized by the McClellan transformation, conditions are derived such that the resulting 2-D two-channel filter bank retains the perfect-reconstruction or aliasing-free properties of the 1-D prototype two-channel filter bank. A particular two-parameter transformation function is developed that has sufficient flexibility to adapt its orientation in any direction and whose optimization involves a simple constrained least-squares problem in which the feasible set lies within a circle. The results have practical applications in many areas of image and video processing where multirate filter banks are used     

基于自适应Kalman滤波的二维有噪子带信号恢复

基于子带信号的多通道表示（multichannel representation)和输入信号的动态特征,本文尝试推出了一种多分辨率状态空间模型,它与带相加子带噪声的滤波器组（Filter Bank)系统是等价的,于是使有噪子带信号的恢复可表述为相应多分辨率态空间模型的最优状态估计问题。进一步又利用信号的向量动态模型,发展了适于二维Kalman滤波的二维多分辨率状态空间模型,根据信号行为的分布,目标平面（object plane)可分割为不同的区域并用不同的向量动态模型来表征信号的非平衡分布,计算机数字仿真结果进一步证实了本文所提出了二维多分辨率Kalman滤波器性能的优越性。     

Gröbner Bases and Multidimensional FIR Multirate Systems

The polyphase representation with respect to sampling lattices in multidimensional (M-D) multirate signal processing allows us to identify perfect reconstruction (PR) filter banks with unimodular Laurent polynomial matrices, and various problems in the design and analysis of invertible MD multirate systems can be algebraically formulated with the aid of this representation. While the resulting algebraic problems can be solved in one dimension (1-D) by the Euclidean Division Algorithm, we show that Gröbner bases offers an effective solution to them in the M-D case.     

A 10-bit 205-MS/s 1.0- mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications

This paper describes a 10-bit 205-MS/s pipeline analog-to-digital converter (ADC) for flat panel display applications with the techniques to alleviate the design limitations in the deep-submicron CMOS process. The switched source follower combined with a resistor-switch ladder eliminates the sampling switches and achieves high linearity for a large single-ended input signal. Multistage amplifiers adopting the complementary common-source topology increase the output swing range with lower transconductance variation and reduce the power consumption. The supply voltage for the analog blocks is provided by the low drop-out regulator for a high power-supply rejection ratio (PSRR) under the noisy operation environment. The pipeline stages of the ADC are optimized in the aspect of power consumption through the iterated calculation of the sampling capacitance and transconductance. The ADC occupies an active area of 1.0 mm² in a 90-nm CMOS process and achieves a 53-dB PSRR for a 100-MHz noise tone with the regulator and a 55.2-dB signal-to-noise-and-distortion ratio for a 30-MHz 1.0-V_PP single-ended input at 205 MS/s. The ADC core dissipates 40 mW from a 1.0-V nonregulated supply voltage.     

An 80/20-MHz 160-mW multimedia processor integrated with embeddedDRAM, MPEG-4 accelerator and 3-D rendering engine for mobileapplications

A low-power multimedia processor for mobile applications is presented. An 80-MHz 32-b RISC with enhanced multiplier, two 20-MHz hardware accelerators with 7.125-Mb embedded DRAM for MPEG-4 visual SP@L1 decoding and 3-D graphics processing, 2-kB dual-port SRAM, and peripheral blocks are integrated together on a single chip, MPEG-4 SP@L1 video decoding and 3-D graphics rendering with a 16-b depth-buffer alpha-blending double-buffering and gouraud-shading features at 2, 2-Mpolygons/s speed are realized with the help of the dedicated hardware accelerators/ The architecture of the processor is optimized in terms of power consumption and performance, and various low-power circuit techniques are adopted in each hardware block. The chip is implemented using 0.18-μm embedded memory logic (EML) technology. Its area is 84 mm², and power consumption is 160 mW when all of the functions are activated     

VLSI chip set for 2D HDTV subband filtering with on-chip linememories

A chip set for 2D subband filtering of HDTV signals has been designed, fabricated and successfully tested. The two chips perform 10*14 quadrature mirror filtering for analysis filtering at the coder and synthesis filtering at the decoder. In order to achieve a very compact realization, the architectures utilize all a priori known properties of the filter algorithm. A 2D polyphase filter structure reduces the processing clock rate from the 72-MHz sampling rate to a moderate 18 MHz. The memory for vertical filtering is realized by on-chip parallel shift registers with multiphase clocking. A small silicon area for the filter arithmetic is achieved by application of carry save adder trees with fixed filter coefficients represented by canonical signed digits. A complete filterbank for luminance and chrominance signals consists of four identical chips, each with 450 000 transistors on 92 mm²     

Efficient implementation of 3D filter for moving object extraction

In this paper the design and implementation of Multi-Dimensional (MD) filter, particularly 3-Dimensional (3D) filter, are presented. Digital (discrete domain) filters applied to image and video signal processing using the novel 3D multirate algorithms for efficient implementation of moving object extraction are engineered with an example. The multirate (decimation and/or interpolation) signal processing algorithms can achieve significant savings in computation and memory usage. The proposed algorithm uses the mapping relations of z-transfer functions between non-multirate and multirate mathematical expressions in terms of time-varying coefficient instead of traditional polyphase de- composition counterparts. The mapping properties can be readily used to efficiently analyze and synthesize MD multirate filters.     

利用插值法提高采样率的滤波器设计

随着数字信号的迅速发展,在现代数字系统中对超过单一采样率的处理已经越来越普遍,这直接导致了多采样率处理作为数字信号处理(DSP)中一个新的分支领域的出现。其中在进行D/A(数字/模拟)转换的场合,往往需要提高数字信号采样率来降低对模拟滤波器的要求。论述利用插值的方法来提高采样速率,介绍了内插原理和给出了一种多相滤波器的设计方法,使性能和资源占有率得到较大的突破,最大限度地减少资源消耗。     

A 90-dB SNR 2.5-MHz output-rate ADC using cascaded multibitdelta-sigma modulation at 8× oversampling ratio

A 16-b 2.5-MHz output-rate analog-to-digital converter (ADC) for wireline communications and high-speed instrumentation has been developed. A 2-1-1 cascaded delta-sigma modulator (DSM) employing 4-b quantizers in every stage makes all quantization noise sources negligible at 8× oversampling ratio, Data weighted averaging with bi-directional rotation eliminates tones generated by multibit digital-to-analog converter (DAC) nonlinearity to increase the spurious-free dynamic-range (SFDR). Switched-capacitor design techniques using low-threshold transistors reduce front-end sampling distortion. The 24.8 mm² chip in 0.5-μm CMOS also integrates the decimation filter and voltage reference. The ADC achieves 90-dB signal-to-noise ratio (SNR) in the 1.25-MHz bandwidth and 102-dB SFDR with 270-mW power dissipation     

Multirate analog-digital systems for signal processing andconversion

Systems containing both analog and digital functions have been investigated with the purpose of realizing mixed-signal integrated circuits with higher levels of functionality and integration. In most cases, such mixed-signal systems are inherently multirate because of the different sampling rates employed at various stages of the system. The multirate concepts have been used for traditional applications, such as subband coding and narrowband filter design. Some unconventional applications of multirate signal processing are also emerging, both for converting between analog samples and digital words, and for realizing processing functions in an easier and more economical way than would be possible using purely digital or analog techniques. This paper reviews fundamental multirate concepts, discusses some developments in this area of integrated multirate analog-digital systems, and outlines some possible future directions for research and application     

分数阶傅里叶域两通道滤波器组

 基于两通道滤波器组构建的子带信号处理方法已在图像、语音信号处理中得到广泛的应用.本文从分数阶傅里叶域多抽样率信号处理基本理论和分数阶卷积定理出发,推导了分数阶傅里叶域两通道滤波器组准确重建的基本条件,并基于传统傅里叶域有限长标准正交镜像滤波器组和共轭正交镜像滤波器组的原型滤波器设计了分数阶傅里叶域标准正交镜像滤波器组和共轭正交镜像滤波器组.本文所提出的结论为分数阶傅里叶域滤波器组理论的建立提供了基本依据,同时也为分数阶傅里叶变换在图像、语音信号处理等工程实践中的应用奠定了理论基础.最后,仿真实验验证了所提分数阶傅里叶域滤波器设计方法的有效性.     

Cascadable one/two-dimensional digital convolver

An architecture and a design for a high-speed CMOS digital convolver which can be used for real-time one-dimensional (1-D) and two-dimensional (2-D) signal processing are presented. In the 2-D mode this device can be used to convolve 10-bit image data with a 3×3 or 2×5 2-D eight-bit-per-coefficient impulse response at 20 M samples/s throughput. In 1-D applications it can be used as a ten-tap finite-impulse response (FIR) filter. Devices can be cascaded to increase the order of the convolution reference in both dimensions     

Synthesis of folded pipelined architectures for multirate DSPalgorithms

In this paper we formalize a novel multirate folding transformation which is a tool used to systematically synthesize control circuits for pipelined VLSI architectures which implement multirate algorithms. Although multirate algorithms contain decimators and expanders which change the effective sample rate of a discrete-time signal, multirate folding time-multiplexes the multirate algorithm to hardware in such a manner that the resulting synchronous architecture requires only a single-clock signal. Multirate folding equations are derived and these equations are used to address two related issues. The first issue is memory requirements in folded architectures. We derive expressions for the minimum number of registers required by a folded architecture which implements a multirate algorithm. The second issue is retiming. Based on the noble identities of multirate signal processing, we derive retiming for folding constraints which indicate how a multirate data-flow graph must be retimed for a given schedule to be feasible. The techniques introduced in this paper can be used to synthesize architectures for a wide variety of digital signal processing applications which are based on multirate algorithms, such as signal analysis and coding based on subband decompositions and wavelet transforms     

Multirate signal processing techniques for high-speed communication over power lines

With the widespread use of Internet and multimedia applications, there is renewed interest in utilizing the electric power lines for transmission of high data rate communication signals. Power lines offer a convenient and pervasive communication medium that does not require new cable installation. However, power lines are classified as a noisy and unpredictable communication channel. Advanced signal processing techniques, such as wavelet filter banks and multirate systems, can be utilized to improve the quality of communication over power lines. In this article an overview of the diverse applications of wavelet filter banks in power line communications is presented with particular reference to wavelet-based multicarrier modulation techniques. Moreover, some suggestions are given regarding the future applications of multirate signal processing techniques in PLC.     

A video codec LSI for high-definition TV systems withone-transistor DRAM line memories

A video codec LSI for high-definition television (HDTV) systems has been developed. By using a time-compressed integration encoding technique, it converts a 20.0-MHz bandwidth luminance signal and two 5.0-MHz chrominance signals into a compressed image signal at 48.6-MHz sampling frequency. It is useful in many HDTV application systems, such as 400-Mb/s digital transmission system, a video disk player system, or an analog transmission system. Over 288000 elements, including a 52-kb one-transistor DRAM (dynamic random access memory) line memory specially developed for this LSI, were integrated on a 12.16×12.10-mm² chip. A standard cell layout method and a 1.2-μm CMOS logic LSI process were used     

A high-speed digital filter LSI for video signal processing

A ninth-order symmetrical filter has been developed for use in two-dimensional (2-D) processing in TV video systems, especially in high-definition TV receivers. A 2-D filter that is composed of only two types of LSIs (one-dimensional (1-D) digital filter LSI and delay-line) is discussed. The architecture of the digital filter LSI and circuit techniques are presented to obtain high-speed operation, to save chip area, and to decrease power consumption. The order and the transfer function of the filter can be altered by means of the external terminals. The chip, achieved through 2-/spl mu/m CMOS technology, contains about 52000 transistors and occupies an area of 50 mm/SUP 2/. It operates at a high clock frequency of over 33 MHz, and dissipates only 600 mW of power.     

Multirate filter banks with block sampling

Multirate filter banks with block sampling were recently studied by Khansari and Leon-Garcia (1993). In this paper, we want to systematically study multirate filter banks with block sampling by studying general vector filter banks where the input signals and transfer functions in conventional multirate filter banks are replaced by vector signals and transfer matrices, respectively. We show that multirate filter banks with block sampling studied by Khansari and Leon-Garcia are special vector filter banks where the transfer matrices are pseudocirculant. We present some fundamental properties for the basic building blocks, such as Noble identities, interchangeability of down/up sampling, polyphase representations of M-channel vector filter banks, and multirate filter banks with block sampling. We then present necessary and sufficient conditions for the alias-free property, finite impulse response (FIR) systems with FIR inverses, paraunitariness, and lattice structures for paraunitary vector filter banks. We also present a necessary and sufficient condition for paraunitary multirate filter banks with block sampling. As an application of this theory, we present all possible perfect reconstruction delay chain systems with block sampling. We also show some examples that are not paraunitary for conventional multirate filter banks but are paraunitary for multirate filter banks with proper block sampling. In this paper, we also present a connection between vector filter banks and vector transforms studied by Li. Vector filter banks also play important roles in multiwavelet transforms and vector subband coding     

Analog RRS cells—An alternative approach for sampled-data low-pass filters

Running recursive sum (RRS) or moving average filters are simple building blocks that are commonly applied in digital signal processing for prefiltering and decimation purposes. This paper presents an efficient implementation of RRS filters employing switched-capacitor techniques. The resulting filter topologies are stray-capacitance insensitive. In order to improve the inherent low-frequency selectivity of these low-pass cells, two novel sharpening procedures are proposed. The zero locations of the analog RRS blocks are, analogous to their digital counterparts, determined exclusively by the applied sampling rate and the order of the filter cell. Hence, the corresponding analog circuits exhibit extremely low element sensitivities. The feasibility of the presented approach is demonstrated by means of two 24th-order silicon prototype filters implemented by a 2-m double-poly CMOS process.