Scaled silicon MOSFETs: degradation of the total gate capacitance

We use a fully quantum-mechanical model to study the influence of image and exchange-correlation effects on the inversion layer and total gate capacitance in scaled Si MOSFETs. We show that, when the device is in weak and moderate inversion, the inclusion of image and many-body exchange-correlation effects increases both the inversion layer and total gate capacitances and shifts the N_s=N_s(VG) characteristics of the device toward lower gate voltages     

Consistent model for the hot-carrier degradation in n-channel andp-channel MOSFETs

A model is derived using the charge-pumping technique for the evaluation of the interface characteristics, in combination with the behavior of the drain and the substrate currents after degradation. For n-channel transistors the degradation is mainly caused by the generation of interface traps. Only in the region of hole injection (V_g≈V_t) is the degradation dominated by the trapped holes, which mask the effect of the generated interface traps. The degradation of p-channel transistors, although completely different at first sight, occurs by the same mechanisms. For this case, the degradation is caused by trapped negative charge, which masks the influence of the interface traps. The latter are nevertheless generated in comparable amounts as in n-channel transistors. Based on these insights, improved procedures for accelerated-lifetime experiments are proposed for both channel types. Finally, the peculiar degradation behavior of n-channel transistors under alternating injection conditions is discussed and fully explained based on the static stress degradation model     

Modeling for reduced gate capacitance of nanoscale MOSFETs

As gate oxides become thinner, in conjunction with scaling of MOS technologies, a discrepancy arises between the gate oxide capacitance and the total gate capacitance, due to the increasing importance of the carrier distributions in the polysilicon electrodes. For the first time, based on least-squares curve fit, we quantitatively explore the impact of quantum mechanics effects in polysilicon gate region on gate capacitance. Comparing the theoretical curves with an extensive set of simulation ones has validated this model.     

A model for AC hot-carrier degradation in n-channel MOSFETs

A recently developed model for AC hot-carrier lifetimes is shown to be valid for typical and worst-case stress waveforms found in CMOS circuits. Three hot-carrier damage mechanisms are incorporated into the model: interface states created at low and medium gate voltages, oxide electron traps created at low gate voltages, and oxide electron traps created at high gate voltages. It is shown that the quasi-static contributions of these three mechanisms fully account for hot-carrier degradation under inverterlike AC stress. No transient effects are required to explain AC stress results, at least for frequencies up to 1 MKz     

Suppression of hot-carrier degradation in Si MOSFETs by germaniumdoping

Presently there are two approaches to the reduction of hot-carrier effects in Si MOSFETs: the use of lightly-doped-drain/double-diffused-drain (LDD/DDD) structures and the reduction of applied bias. Both of these suffer certain penalties. A technique for incorporating Ge impurities in the channel that creates additional scattering so that `lucky' hot carriers are less probable is introduced. Results indicate that while the initial MOSFET characteristics are maintained, the degradation rate under voltage stress is much reduced     

On the channel-length dependence of the hot-carrier degradation ofn-channel MOSFETs

The channel-length dependence of lifetime plots is analyzed. It is shown that no unique τ*I_d versus I_sub/I_d relation can be obtained when threshold-voltage shifts are used for measuring the lifetime. In contrast, when using charge pumping as a monitor for the degradation, the lifetime plot for a given technology proves to be independent of the channel length     

Research into charge pumping method technique for hot-carrier degradation measurement of LDMOS

A measuring technique based on the CP (charge pumping) method for hot-carrier degradation measure ment of high voltage N-LDMOS is researched in depth. The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail. At the same time, the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed. The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.     

LDMOS器件热载流子退化特性测试中的电荷泵技术研究

A measuring technique based on the CP（charge pumping）method for hot-carrier degradation measurement of high voltage N-LDMOS is researched in depth.The impact of the special configuration on the CP spectrum and the gate voltage pulse frequency range which is suitable for high voltage N-LDMOS in CP measurements is investigated in detail.At the same time,the impacts of different reverse voltage applied on the source and drain electrodes and of the gate pulse shape on the CP curve change in N-LDMOS are also proposed and analyzed.The conclusions give guidance on measuring the density of interface states with experimental instructions and offer theoretic instructions for analyzing CP curves in high voltage N-LDMOS more accurately.     

Modelling of hot-carrier degradation and its application for analog design for reliability

An analytical CMOS transistor ageing model is presented and a new procedure that allows the extraction of its parameters are presented in this paper. Then, we show how this model can be used to forecast and understand the drifts of the main characteristics of a CMOS circuit. Further, we demonstrate that this model can also be used to help the analog designer to choose and/or modify a circuit in order to minimise the hot-carrier induced degradations. Finally, we use an ageing simulation tool realised in VHDL-AMS to validate the analytical study, and we present our first experimental results.     

Voltage-splitting technique for reliability evaluation of off-state mode of MOSFETs in ultrathin gate oxides

A simple and practical new methodology is proposed for reliability evaluation of off-state mode in ultrathin oxides. By applying a negative voltage on the gate while the drain region is biased at the operating voltage; the so-called voltage-splitting technique (VST), we successfully resolve the difficulty associated with the unrealistic high drain-bias stress otherwise required, which leads to the excessive damage to oxide integrity in the overlap region. In comparison with a high drain-bias stress, the time-dependent dielectric breakdown measurements using VST show the well-behaved breakdown distribution and correlate with the measured device characteristics. In addition, this methodology may provide a possible method to extrapolate stress data to operational voltage for realistic off-state reliability projection.     

Analysis of the charge pumping technique and its application forthe evaluation of MOSFET degradation

It is shown that the charge pumping technique is able not only to determine the degradation mechanisms in MOS transistors under all kinds of aging conditions (e.g., irradiation, hot-carrier, Fowler-Nordheim stress), but also in several cases to evaluate and to quantify the degradation. It is further shown that the technique can be applied to separate the presence of fixed oxide changes due to charge trapping and the generation of interface traps. It can be used to analyze degradations that occur uniformly over the transistor channel, as well as strongly localized transistor degradations (e.g., for the case of hot-carrier degradations). All possible cases of uniform and nonuniform degradations, for p-channel as well as for n-channel transistors, are described, and for most of them experimental examples are given     

Modelling hot-carrier degradation of LDD NMOSFETs by using a high-resolution measurement technique

By using a new, state-of-the-art measurement technique, the hot-carrier degradation of LDD nMOSFETs is studied. This high-resolution measurement technique, allows the measurement of degradation levels as low as 0.03 %. A new model based on Goo et al. [1] has been developed and verified in the full region between 0.03 up to almost 10 % for the ageing parameter I_d,lin. The introduction of a simultaneous non-linear least-square fit of the degradation curves has been successful for predicting the complete degradation behaviour at real life operating conditions.     

On the gate capacitance limits of nanoscale DG and FD SOI MOSFETs

An analytical total gate capacitance C/sub G/ model for symmetric double-gate (DG) and fully depleted silicon-on-insulator (FD/SOI) MOSFETs of arbitrary Si film is developed and demonstrated. The model accounts for the effects of carrier-energy quantization and inversion-layer screening and is verified via self-consistent numerical solutions of the Poisson and Schro/spl uml/dinger equations. Results provide good physical insight regarding C/sub G/ degradation due to quantization and screening governed by device structure and/or transverse electric field for nanoscale DG and FD/SOI MOSFETs. Two limits of C/sub G/ at ON-state are then derived when the silicon film t/sub Si/ approaches zero and infinity. The effect of inversion-layer screening on C/sub G/, which is significant for ultrathin Si-film DG MOSFETs, is quantitatively defined for the first time. The insightful results show that the two-dimensional screening length for DG MOSFETs is independent of the doping density and much shorter than the bulk Debye length as a result of strong structural confinement.     

High-energy tail electrons as the mechanism for the worst-case hot-carrier stress degradation of the deep submicrometer N-MOSFET

Experimental evidence, based on sensitively modulating the concentration of the high-energy tail of the electron energy distribution, reveals an important trend in the mid-to-high gate stress voltage (V/sub g/) regime, where device degradation is seen to continuously increase with the applied V/sub g/, for a given drain stress voltage V/sub d/. The shift in the worst-case degradation point from V/sub g//spl ap/V/sub d//2 to V/sub g/=V/sub d/, depicting an uncorrelated behavior with the substrate current, is caused by the injection of the high-energy tail electrons into the gate oxide, when the oxide field near the drain region becomes increasingly favorable as V/sub g/ approaches V/sub d/. This letter offers an improved framework for understanding the worst-case hot-carrier stress degradation of deep submicrometer N-MOSFETs under low bias condition.     

Hot carrier degradation of n-channel MOSFETs characterized by agated-diode measurement technique

The gated-diode measurement technique characterizes the physical damage induced in n-channel MOSFETs during hot-carrier stress. The results show that the gate oxide in the channel region is not affected by hot-carrier stress. The most severe damage is located in the gate oxide above the drain-gate overlap region. Furthermore, the measurements show that the density of generation centers in the substrate is increased after hot-carrier stress     

Small-signal gate-to-drain capacitance of MOSFET as a diagnostic tool for hot-carrier induced degradation

In this paper a method for the study of hot-carrier induced charge centers in MOSFETs based on a small-signal gate-to-drain capacitance measurement is described. Numerical modeling and simulation is used to provide an understanding of the effects of spatially localized trapped carriers and interface states on this capacitance. Experimental gate-to-drain capacitance results are presented and compared with charge pumping measurements. This method is used to investigate hot-carrier degradation of n- and p-channel MOSFETs after drain avalanche hot-carrier stress conditions. It is concluded that under this stress condition the degradation of both n- and p-channel devices is due to the trapping of majority carriers and the generation of acceptor type interface states in the top half of the silicon bandgap.     

A comparison of hot-carrier degradation in tungsten polycide gateand poly gate p-MOSFETs

A study is made of hot-carrier immunity of tungsten polycide and of non-polycide, n⁺ poly gate, buried-channel p-MOSFETs, under conditions of maximum gate current injection. Increased hot-carrier degradation is observed for WSi_x p-MOSFETs under low drain voltage stress, where trap filling by injected electrons is the dominant degradation process. Stress-induced damage evaluated by gate-to-drain capacitance C_gd^s measurement shows increased susceptibility to electron trapping in the WSi_x device. F-induced oxide bulk defects introduced during polycidation may be responsible for the increased trapping observed. In addition, a significant decrease in electron detrapping rate is observed, which suggests a deeper energy distribution of F-related traps. The greater susceptibility to electron trapping, coupled with a decrease in electron detrapping rate, result in the reduction in DC hot-carrier lifetime over four orders of magnitude (based on ΔV_t=50 mV criterion) under normal operating voltages. As hot-carrier effects in p-MOSFETs continue to be a concern for effective channel lengths less than 0.5 μm, the reduced hot-carrier lifetime of WSi_x p-MOSFETs suggests that WF₆-based silicidation may not be appropriate for deep submicrometer CMOS devices     

Impact of hot-carrier degradation on the low-frequency noise in MOSFETs under steady-state and periodic large-signal excitation

This letter reports the diagnostic power of the low-frequency noise analysis (steady-state and periodic large-signal excitation) in MOSFETs subjected to hot-carrier degradation. The LF noise under periodic large-signal excitation is shown to increase more rapidly than the LF noise in steady-state. Moreover the improvement in the LF noise performance due to periodic large-signal excitation, observed for fresh devices, gradually diminishes as the devices are subjected to hot-carrier stress.     

Analysis of the narrow gate effect in submicrometer MOSFET's

The narrow gate effect produces an increasing threshold voltage with decreasing gate width. Our previous approximate formulae, based on shifting the gate-edge position, predicts the variation of the threshold voltage with gate width accurately in the super-micrometer width range, but error begins to increase when the gate width is less than a critical valueW_{min}which is about 1 µm for 200-A gate oxide 7000-A field oxide and2 times 10^{16}cm^-3substrate doping. The physical reason of this error is delineated and combined with two-dimensional numerical analyses to give a new formulae based on shifting the gate-center position as the gate width narrows. The parameters of this new formula may be obtained either from two-dimensional computation or experimental measurements. The error is less than 2 percent at a dc gate bias of 5 V.     

A methodology for projecting SiO2 thick gate oxide reliability on trench power MOSFETs and its application on MOSFETs VGS rating

In this work, a methodology based on the E-model for the reliability projection of a thick (> 20 nm) SiO₂ gate oxide on a vertical trench power MOSFET, is presented. Experimental results suggest that a Logic Level (LL) trench MOSFET with 35 nm of gate oxide can be rated at V_GS = + 12 V if one assumes continuous DC Gate-Source bias of V_GS = + 12 V at T = 175 °C for 10 years at a defect level of 1 Part Per Million (PPM). We will demonstrate that if we take into account MOSFET device lifetime as dictated by the Automotive Electronics Council (AEC Q101) mission profile, then devices can be rated higher to V_GS = + 14.7 V at T = 175 °C for the same PPM level (1 PPM). The application of the methodology for establishing the oxide thickness, t_ox, for any required voltage rating, is discussed.