A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Modeling and Analysis of the Asymmetric Source/Drain Extension CMOS Transistors for Nanoscale Technologies

The asymmetric source/drain extension (ASDE) transistor can be a suitable option because of improved short channel effects in technology nodes beyond 32 nm. In this paper, we have analyzed the impact of asymmetric drain extension reduction on the device metrics, namely, gate-to-drain capacitance, drain current, subthreshold leakage, and gate tunneling leakage current. Also, analytical models have been developed to model the effect of the ASDE devices. Based on our proposed analytical model, SPICE-compatible transistor models have been developed to include the ASDE device structure as possible design options. With our SPICE-compatible transistor models, large-scale circuit simulation can be performed to evaluate the benefits and the overheads associated with the ASDE devices. It is observed from circuit simulations that there is an optimal drain extension length which is different from the source extension length. With the ASDE devices, the circuit power delay product can effectively be reduced by almost 35% with respect to the conventional symmetric devices.     

Channel length independent subthreshold characteristics insubmicron MOSFETs

This work reports an anomalous subthreshold characteristic of the MOSFET for the first time. It is observed that the subthreshold characteristic does not change as the channel length decreases. The cause of channel length independent subthreshold characteristics is identified as the localized pileup of channel dopants near the source and drain ends of the channel. The low surface potential of this pileup region limits the subthreshold current of MOSFET. As a result, the ratio of on-current to off-current for this MOSFET increases as the channel length is reduced, which is an important parameter for low-voltage operation. It is found that a MOSFET with channel length independent subthreshold characteristic is more suitable for low-voltage operation     

A compact double-gate MOSFET model comprising quantum-mechanicaland nonstatic effects

In this work, we investigate the electrical properties of the Double-Gate MOSFET (DG-MOSFET), which turn out to be very promising for device miniaturization below 0.1 μm. A compact model which accounts for charge quantization within the channel, Fermi statistics, and nonstatic effects in the transport model is worked out. The main results of this investigation are: (1) the ideality factor in subthreshold is equal to unity, i.e., the slope of the turn-on characteristic is 60 mV/decade at room temperature; (2) the drain-induced barrier lowering is minimized by the shielding effect of the double gate, which allows us to reduce the channel length below 30 nm; and (3) the device transconductance per unit width is maximized by the combination of the double gate and by a strong velocity overshoot which occurs in response to the sudden variation of the electric field at the source end of the channel, and which can be further strengthened near the drain in view of the short device length. As a result, a sustained electron velocity of nearly twice the saturation velocity is achievable. The above results prove that the potential performance advantages of the double-gate device architecture may be worth the development effort     

Quarter-micrometer SPI (Self-aligned Pocket Implantation) MOSFET'sand its application for low supply voltage operation

A novel SPI (Self-aligned Pocket Implantation) technology has been presented, which improves short channel characteristics without increasing junction capacitance. This technology features a localized pocket implantation using gate electrode and TiSi₂ film as self-aligned masks. An epi substrate is used to decrease the surface impurity concentration in the well while maintaining high latch-up immunity. The SPI and the gate to drain overlapped structure such as LATID (Large-Angle-Tilt Implanted Drain) technology allow use of the ultra low impurity concentration in the channel region, resulting in higher saturation drain current at the same gate over-drive compared to conventional device. The carrier velocity reaches 8×10⁶ cm/sec and subthreshold slope is less than 75 mV/dec, which can be explained by low impurity concentration in the channel and in the substrate. The small gate depletion layer capacitance of SPI MOSFET was estimated by C-V measurement, and it can explain high performance such as small subthreshold slope. On the other hand, the problem and the possibility of low supply voltage operation have been discussed, and it has been proposed that small subthreshold slope is prerequisite for low power device operated at low supply voltage. In addition, the drain junction capacitance of SPI is decreased by 65% for N-MOSFET's, and 69% for P-MOSFET's both compared with conventional devices. This technology yields an unloaded CMOS inverter of 48 psec delay time at the supply voltage of 1.5 V     

An SOI voltage-controlled bipolar-MOS device

This paper describes a new operation mode of the SOI MOSFET. Connecting the floating substrate to the gate in a short-channel SOI MOSFET allows lateral bipolar current to be added to the MOS channel current and thereby enhances the current drive capability of the device. Part of the bipolar current emitted by the source terminal merges into the channel before reaching the drain, which renders the base width substantially shorter than the gate length. This novel operating mode of a short-channel SOI transistor is particularly attractive for high-speed operation, since the device is capable of both reduced voltage swing operation and high current drive, n-p-n and p-n-p devices, as well as complementary inverters have been successfully fabricated.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

A DC model for asymmetric trapezoidal gate MOSFET's in stronginversion

Asymmetric trapezoidal gate (ATG) MOSFET is an innovative device having a structure of a relatively narrow drain-side width in order to reduce parasitic effects for enhancing device performance. In this paper, we develop a DC model for ATG MOSFET's. We use a charge-based approach to explore the asymmetric feature between source and drain of ATG MOSFET's, and obtain analytic formulae for threshold voltage, body effect, drain current, and channel length modulation effect in linear and saturation regions for both forward and reverse modes of operations. The model provides a physical analysis of the ATG structure, shows good agreement with measurement data, and is useful in circuit simulation with ATG devices     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

Analytical I–V model of SOI and SON MOSFETs: a comparative analysis

A generalised three-interface compact capacitive threshold voltage model for horizontal silicon-on-insulator/silicon-on-nothing (SOI/SON) MOSFET has been developed. The model includes different threshold voltage-modifying short-channel phenomena like fringing field, junction-induced 2D-effects, etc. Based on the threshold voltage model, an analytical current voltage model is formulated from the basic charge control analysis of MOSFET. In order to provide a better explanation to various observations and applicable to short-channel SOI and SON structures, the present current voltage model includes the effect of carrier velocity saturation and channel length modulation. Identical structures for both the devices, SOI and SON, are considered but for SON MOSFET, the buried oxide layer is replaced by air. The performance of the two devices are studied and compared in terms of threshold voltage roll-off, subthreshold slope, drain current and drain conductance. The SON MOSFET technology is found to offer devices with further scalability and enhanced performance in terms of threshold voltage roll-off, sub-threshold slope and greater current derivability, thereby providing scope for further miniaturisation of devices and much better performance improvement.     

A new extraction algorithm for the metallurgical channel length ofconventional and LDD MOSFETs

A new extraction algorithm for the metallurgical channel length of conventional and LDD MOSFETs is presented, which is based on the well-known resistance method with a special technique to eliminate the uncertainty of the channel length and to reduce the influence of the parasitic source/drain resistance on threshold-voltage determination. In particular, the metallurgical channel length is determined from a wide range of gate-voltage-dependent effective channel lengths at an adequate gate overdrive. The 2-D numerical analysis clearly show that adequate gate overdrive is strongly dependent on the dopant concentration in the source/drain region. Therefore, an analytic equation is derived to determine the adequate gate overdrive for various source/drain and channel doping. It shows that higher and lower gate overdrives are needed to accurately determine the metallurgical channel length of conventional and LDD MOSFET devices, respectively. It is the first time that we can give a correct gate overdrive to extract L_met not only for conventional devices but also for LDD MOS devices. Besides, the parasitic source/drain resistance can also be extracted using our new extraction algorithm     

Subthreshold current in MODFETs of tenth-micrometer gate

The subthreshold current of conventional GaAs/AlGaAs MODFETs and pseudomorphic InGaAs/AlGaAs MODFETs with the gate length down to 0.12 μm is investigated. The gate swing increases with the drain voltage and decreases with the gate length. It is attributed to charge injection from source to drain, limited by the channel potential barrier, which is a function of both the drain and the gate voltages. The pseudomorphic InGaAs/AlGaAs MODFETs show much better control than the conventional GaAs/AlGaAs MODFETs for the subthreshold current, especially with high drain biases. This shows that the pseudomorphic quantum-well structures can suppress the subthreshold current passing through the GaAs buffer region and reduce the undesirable short-channel effects     

Effects of various implant species and post-anneal treatments on SI N-channel MOSFETs

This paper presents a detailed analysis of physical and electrical characterizations of N-channel MOSFETs with gate lengths of 2 to 8 microns. The fabrication sequence features a self-aligned polysilicon gate and a LOCOS process with variations in the source/drain implant species (arsenic or phosphorous) and anneal ambients (dry O₂ or N₂. TEM micrographs show a difference in the defect configuration for arsenic or phosphorous implants: arsenic produces dislocation loops while phosphorous produces a rigid “square-grid” dislocation network or an “x” or “y” shaped dislocation network dependinon the anneal ambient. All defects were found to terminate at the source/drain periphery for gate lengths greater than or equal to 2 microns. Electrical characterization show typical MOSFET performance for the devices with gate lengths greater than 4 microns. The dry O₂ anneal ambient appears to give a slightly lower subthreshold leakage current (in the region of picoamperes) than the N₂ ambient. For the devices with gate lengths of 2 microns, the depletion regions of the source and drain overlap and nearly overlap for the phosphorous and arsenic cases, respectively, due to fast diffusivity of phoshorous.     

Vertical Enhancement-Mode InAs Nanowire Field-Effect Transistor With 50-nm Wrap Gate

We present results on fabrication and dc characterization of vertical InAs nanowire wrap-gate field-effect transistor arrays with a gate length of 50 nm. The wrap gate is defined by evaporation of 50-nm Cr onto a 10-nm-thick HfO₂ gate dielectric, where the gate is also separated from the source contact with a 100-nm SiO_x, spacer layer. For a drain voltage of 0.5 V, we observe a normalized transconductance of 0.5 S/mm, a subthreshold slope around 90 mV/dec, and a threshold voltage just above 0 V. The highest observed normalized on current is 0.2 A/mm, with an off current of 0.2 mA/mm. These devices show a considerable improvement compared to previously reported vertical InAs devices with SiN_x, gate dielectrics.     

Influence of dielectric breakdown on MOSFET drain current

Breakdown of gate dielectric is one of the most dangerous threats for reliability of MOSFET devices in operating conditions. Not only the gate leakage resulting from breakdown is a problem for power consumption issues, but the "on" drain current can be strongly affected. In this paper, we show that in recent technologies, featuring ultrathin gate dielectrics, the corruption of drain current due to breakdown can be modeled as the effect of a portion of channel being damaged by the opening of the breakdown spot. Devices featuring 2.2- and 3.5-nm-thick gate oxide and various channel widths are stressed by using a specialized setup, and the degradation of transistor parameters is statistically studied. The analysis shows that the radius of the damaged region responsible for drain current degradation can be estimated between 1.4 and 1.8 /spl mu/m.     

器件与电路参数对SET波形影响仿真研究

利用Sentaurus TCAD仿真软件,建立并校准了MOSFET仿真模型。分析了NMOS器件在重离子轰击下产生的SET波形。结果表明,轰击位置在漏极且入射角呈120°时,器件具有最大的峰值电流。通过建立MIX、TCAD、SPICE三种反相器模型并施加重离子轰击,研究了不同模拟方式下电路响应对SET波形的影响,指出了采用双指数电流源在SPICE电路中模拟的不准确性。采用MIX模型探究了器件结构及电路环境对SET波形的影响。结果表明,LET能量、栅极长度、轨电压和负载电容都会对SET波形脉宽及平台电流大小产生显著影响,说明了建立SET模拟波形时须综合考虑这些因素。     

一种带有斜向扩展源的双栅隧穿场效应晶体管

设计并研究了一种带有轻掺杂漏(LDD)和斜向扩展源(OES)的双栅隧穿场效应晶体管(DG-TFET),并利用Sentaurus TCAD仿真工具对栅长及扩展源长度等关键参数进行了仿真分析。对比了该器件与传统TFET的亚阈值摆幅、关态电流和开关电流比,并从器件的带带隧穿概率分析其优势。仿真结果表明,该器件的最佳数值开关电流比及亚阈值摆幅分别可达3.56×10¹²和24.5 mV/dec。另外,该DG-TFET在双极性电流和接触电阻方面性能良好,且具有较快的转换速率和较低的功耗。     

Source/drain optimization of underlapped lightly doped nanoscale double-gate MOSFETs

The impact of the spacer length at the source (L_s) and drain (L_d) on the performance of symmetrical lightly-doped double-gate (DG) MOSFET with gate length L = 20 nm is analyzed, with the type and doping concentration of the spacers kept the same as in the channel material. Using the transport parameters extracted from experimental data of a double-gate FinFET, simulations were performed for optimization of the underlapped gate-source/drain structure. The simulation results show that the subthreshold leakage current is significantly suppressed without sacrificing the on-state current for devices designed with asymmetrical source/drain extension regions, satisfying the relations L_s = L/2 and L_d = L. In independent drive configuration, the top-gate response can be altered by application of a control voltage on the bottom-gate. In devices with asymmetrical source/drain extension regions, simulations demonstrate that the threshold voltage controllability is improved when the drain extension region length is increased.     

An ultrathin vertical channel MOSFET for sub-100-nm applications

An ultrathin vertical channel (UTVC) MOSFET with an asymmetric gate-overlapped low-doped drain (LDD) is experimentally demonstrated. In the structure, the UTVC (15 nm) was obtained using the cost-effective solid phase epitaxy, and the boron-doped poly-Si/sub 0.5/Ge/sub 0.5/ gate was adopted to adjust the threshold voltage. The fabricated NMOSFET offers high-current drive due to the lightly doped (<1/spl times/10/sup 15/ cm/sup -3/) channel, which suppresses the electron mobility degradation. Moreover, an asymmetric gate-overlapped LDD was used to suppress the offstate leakage current and reduce the source/drain series resistance significantly as compared to the conventional symmetrical LDD. The on-current drive, offstate leakage current, subthreshold slope, and DIBL for the fabricated 50-nm devices are 325 /spl mu/A//spl mu/m, 8/spl times/10/sup -9/ /spl mu/A//spl mu/m, 87 mV/V, and 95 mV/dec, respectively.     

Impact of nonuniform graded dopant profile in polysilicon gate on gate leakage current

In a MOSFET, a nonuniform, graded vertical dopant profile in the polysilicon gate causes a potential drop at the polysilicon/oxide interface. In this paper, the effect of this potential drop on the gate leakage current has been evaluated for the first time. The extent of variations of this affected gate leakage current with gate oxide thickness, gate length, and gate and drain bias conditions have been assessed with device simulation for an nMOS at 0.13 /spl mu/m low-voltage process. The results provide a guideline to the severity of this effect from the point of view of device and circuit operation and standby power consumption.