A simple approach to fabrication of high-quality HfSiON gate dielectrics with improved nMOSFET performances

A simple technique to form high-quality hafnium silicon oxynitride (HfSiON) by rapid thermal processing oxidation of physical vapor deposition hafnium nitride (HfN) thin films on ultrathin silicon oxide (SiO/sub 2/) or silicon oxynitride (SiON) layer is presented. Metal TaN gate electrode is also introduced into such HfSiON stacks. Excellent performances including large electron mobility (85%SiO/sub 2/at0.2 MV/cm), low leakage current (10/sup -4/ of SiO/sub 2/), and superior time-dependant dielectric breakdown reliability are achieved in HfSiON/SiO/sub 2/ stacks, and these results suggest such stacks are very promising for the low-power SOC applications in the near future. In addition, the improvement of the electron mobility in this HfSiON/SiO/sub 2/ stack by a reduction of the border traps in the HfSiON dielectric is demonstrated.     

On the impact of TiN film thickness variations on the effective work function of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON gate stacks

The impact of TiN film thickness variations on the effective work function (WF) of poly-Si/TiN/SiO/sub 2/ and poly-Si/TiN/HfSiON interfaces has been investigated. The electrical signatures of these gate stacks indicate that the concentration of Hf-Ti and Ti-Si bonds at the (poly-Si/TiN)/HfSiON and (poly-Si/TiN)/SiO/sub 2/ interface plays a significant role on the control of the gate stacks' WF. The density of these interfacial bonds and the related work function changes are correlated to the degree of nucleation of the TiN film on the dielectric.     

Co-optimization of the metal gate/high-k stack to achieve high-field mobility >90% of SiO/sub 2/ universal mobility with an EOT=/spl sim/1 nm

HfO/sub 2/ and HfSiON gate dielectrics with high-field electron mobility greater than 90% of the SiO/sub 2/ universal mobility and equivalent oxide thickness (EOT) approaching 1 nm are successfully achieved by co-optimizing the metal gate/high-k/bottom interface stack. Besides the thickness of the high-/spl kappa/ dielectrics, the thickness of the ALD TiN metal gate and the formation of the bottom interface also play an important role in scaling EOT and achieving high electron mobility. A phase transformation is observed for aggressively scaled HfO/sub 2/ and HfSiON, which may be responsible for the high mobility and low charge trapping of the optimized HfO/sub 2/ gate stack.     

Improved device performance and reliability in high /spl kappa/ HfTaTiO gate dielectric with TaN gate electrode

The device performance and reliability of higher-/spl kappa/ HfTaTiO gate dielectrics have been investigated in this letter. HfTaTiO dielectrics have been reported to have a high-/spl kappa/ value of 56 and acceptable barrier height relative to Si (1.0 eV). Through process optimization, an ultrathin equivalent oxide thickness (EOT) (/spl sim/9 /spl Aring/) has been achieved. HfTaTiO nMOSFET characteristics have been studied as well. The peak mobility of HfTaTiO is 50% higher than that of HfO/sub 2/ and its high field mobility is comparable to that of HfSiON with an intentionally grown SiO/sub 2/ interface, indicative of superior quality of the interface and bulk dielectric. In addition, HfTaTiO dielectric has a reduced stress-induced leakage current (SILC) and improved breakdown voltage compared to HfO/sub 2/ dielectric.     

Highly Manufacturable and Reliable HfSiON N-FET With Poly-Si/a-Si Stacked Gate for LSTP Applications

We have proposed a novel poly-Si/a-Si/HfSiON transistor to enhance reliabilities without performance degradation for a 65-nm-node low standby power (LSTP) application. By insertion of a thin amorphous-Si layer between the Poly-Si gate electrode and HfSiON, both phosphorus penetration from gate electrode and a reaction at gate electrode/HfSiON interface are successfully suppressed, so that positive bias temperature instability, one of the biggest issues for high-k gate dielectric, is drastically improved by two orders of magnitude. By carefully optimizing the gate stack structure of HfSiON, the HfSiON device can satisfy both lower gate leakage and gate-induced drain leakage at the same time. As a result, an excellent I_on- I_standby (= I_g + l_off) characteristic can be achieved, compared to the conventional SiON device. The a-Si insertion technique can realize the combination between the high-k gate dielectric and Poly-Si for future LSTP applications.     

Charge trapping and detrapping characteristics in hafnium silicate gate stack under static and dynamic stress

The V/sub th/ instability of nMOSFET with HfSiON gate dielectric under various stress conditions has been evaluated. It is shown that after constant voltage stress, the threshold voltage (V/sub th/) relaxes to its initial prestress value. The relaxation rate is strongly affected by the stress duration and magnitude rather than injected charge flux or magnitude of the V/sub th/ shift. It is proposed that spatial distribution of trapped charges, which is strongly affected by the stress conditions, determines the relaxation rate. The implications of the electron trapping/detrapping processes on electrical evaluation of the high-/spl kappa/ gate dielectrics are discussed.     

Physical Understanding of Gate-Depletion Phenomena in Poly-Si/HfSiON Stacks Based on C–V Differentiation Analysis

We propose sub-1-A-resolution analysis of gate surface layer In scaled-T_inv (capacitance equivalent thickness at substrate inversion) gate stacks by differentiating their C-V curves. By introducing the universal derivative-of-capacitance curve, gate stacks with different equivalent oxide thickness of gate insulator and substrate-impurity concentration JVSub can be analyzed in one and the same plot. By applying this analysis technique to p+ poly-Si/HfSiON stack, it is found that gate depletion increases due to both lower poly impurity concentration N_poly and high pinning charge density N_ox inside the dielectric. Ultrathin SiN cap insertion onto HfSiON recovers the degradation in N_poly and N_ox leading to suppression of gate depletion and flatband voltage shift.     

Demonstration of short-channel self-aligned Pt/sub 2/Si-FUSI pMOSFETs with low threshold voltage (-0.29 V) on SiON and HfSiON

Short gate-length Pt full-silicidation (FUSI) (PtSi and Pt/sub 2/Si) pMOSFETs were fabricated for the first time using a self-aligned Pt-FUSI process, demonstrating scalability (with no linewidth effects) down to /spl sim/ 60-nm gate lengths. The electrical results are compared to the Ni-FUSI (NiSi and Ni/sub 31/Si/sub 12/) pMOSFET devices. A low threshold voltage /spl les/|-0.29 V| was obtained for the Pt/sub 2/Si-FUSI pMOSFETs on SiON and HfSiON indicating that the Pt/sub 2/Si FUSI does not suffer from the Fermi-level pinning or gate-dielectric-charge effects on the HfSiON.     

The electrical and material characterization of hafnium oxynitride gate dielectrics with TaN-gate electrode

Electrical and material characteristics of hafnium oxynitride (HfON) gate dielectrics have been studied in comparison with HfO/sub 2/. HfON was prepared by a deposition of HfN followed by post-deposition-anneal (PDA). By secondary ion mass spectroscopy (SIMS), incorporated nitrogen in the HfON was found to pile up at the dielectric/Si interface layer. Based on the SIMS profile, the interfacial layer (IL) composition of the HfON films appeared to be like hafnium-silicon-oxynitride (HfSiON) while the IL of the HfO/sub 2/ films seemed to be hafnium-silicate (HfSiO). HfON showed an increase of 300/spl deg/C in crystallization temperature compared to HfO/sub 2/. Dielectric constants of bulk and interface layer of HfON were 21 and 14, respectively. The dielectric constant of interfacial layer in HfON (/spl sim/14) is larger than that of HfO/sub 2/ (/spl sim/7.8). HfON dielectrics exhibit /spl sim/10/spl times/ lower leakage current (J) than HfO/sub 2/ for the same EOTs before post-metal anneal (PMA), while /spl sim/40/spl times/ lower J after PMA. The improved electrical properties of HfON over HfO/sub 2/ can be explained by the thicker physical thickness of HfON for the same equivalent oxide thickness (EOT) due to its higher dielectric constant as well as a more stable interface layer. Capacitance hysteresis (/spl Delta/V) of HfON capacitor was found to be slightly larger than that of HfO/sub 2/. Without high temperature forming gas anneal, nMOSFET with HfON gate dielectric showed a peak mobility of 71 cm/sup 2//Vsec. By high temperature forming gas anneal at 600/spl deg/C, mobility improved up to 256 cm/sup 2//Vsec.     

Fully silicided NiSi gate on La/sub 2/O/sub 3/ MOSFETs

We have fabricated the fully silicided NiSi on La/sub 2/O/sub 3/ for n- and p-MOSFETs. For 900/spl deg/C fully silicided CoSi/sub 2/ on La/sub 2/O/sub 3/ gate dielectric with 1.5 nm EOT, the gate dielectric has large leakage current by possible excess Co diffusion at high silicidation temperature. In sharp contrast, very low gate leakage current density of 2/spl times/10/sup -4/ A/cm/sup 2/ at 1 V is measured for 400/spl deg/C formed fully silicided NiSi and comparable with Al gate. The extracted work function of NiSi was 4.42 eV, and the corresponding threshold voltages are 0.12 and -0.70 V for respective n- and p-MOSFETs. Electron and hole mobilities of 156 and 44 cm/sup 2//V-s are obtained for respective n- and p-MOSFETs, which are comparable with the HfO/sub 2/ MOSFETs without using H/sub 2/ annealing.     

High-k Al/sub 2/O/sub 3/ gate dielectrics prepared by oxidation of aluminum film in nitric acid followed by high-temperature annealing

A simple, cost-effective, and room temperature process was proposed to prepare high-k gate dielectrics. An aluminum oxide (Al/sub 2/O/sub 3/) gate dielectric was prepared by oxidation of ultrathin Al film in nitric acid (HNO/sub 3/) at room temperature then followed by high-temperature annealing in O/sub 2/ or N/sub 2/. The substrate injection current behavior and interface trap-induced capacitance were introduced to investigate the interfacial property between the gate dielectric and Si substrate. Al/sub 2/O/sub 3/ gate dielectric MOS capacitors with and without initial SiO/sub 2/ layers were characterized. It was shown that the Al/sub 2/O/sub 3/ gate dielectrics with initial oxide exhibit better electrical properties than those without. The 650/spl deg/C N/sub 2/-POA Al/sub 2/O/sub 3/-SiO/sub 2/ sample with an equivalent oxide thickness of 18 /spl Aring/ exhibits three orders of magnitude reduction in gate leakage current in comparison with the conventional thermal SiO/sub 2/ sample.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-K dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-K dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/ A(2-5 /spl times/ 10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8 /spl times/ 10/sup 17/ cm/sup -3/ eV/sup -1/ to 1, 3 /spl times/ 10/sup 19/ cm/sup -3/ eV/sup -1/ somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-K/gate stacks, relative comparison among them and to the Si-SiO/sub 2/ system.     

Improvement of interfacial layer reliability by incorporation of deuterium into HfAlOx formed by D/sub 2/O-ALD

Deuterium was incorporated into the HfAlOx /SiON gate dielectric by the use of heavy water (D/sub 2/O) instead of H/sub 2/O in the atomic layer deposition (ALD) process of HfAlOx. The HfAlOx formed by D/sub 2/O-ALD acts as a deuterium reservoir, and the deuterium atoms are effectively incorporated into the SiON after full CMOS processing. It is clarified that the deuterium incorporation suppresses interfacial trap generation and interfacial SiON breakdown, while charge-trapping in the HfAlOx bulk traps is barely affected. The D/sub 2/O-ALD process is useful for improving the interfacial layer reliability under gate negative stress; therefore it is not only effective for HfAlOx, but also for high-/spl kappa//SiO/sub 2/(SiON) gate stacks with other high-/spl kappa/ materials such as HfO/sub 2/ or HfSiON.     

Low-frequency noise in submicrometer MOSFETs with HfO/sub 2/, HfO/sub 2//Al/sub 2/O/sub 3/ and HfAlO/sub x/ gate stacks

Low-frequency noise measurements were performed on p- and n-channel MOSFETs with HfO/sub 2/, HfAlO/sub x/ and HfO/sub 2//Al/sub 2/O/sub 3/ as the gate dielectric materials. The gate length varied from 0.135 to 0.36 /spl mu/m with 10.02 /spl mu/m gate width. The equivalent oxide thicknesses were: HfO/sub 2/ 23 /spl Aring/, HfAlO/sub x/ 28.5 /spl Aring/ and HfO/sub 2//Al/sub 2/O/sub 3/ 33 /spl Aring/. In addition to the core structures with only about 10 /spl Aring/ of oxide between the high-/spl kappa/ dielectric and silicon substrate, there were "double-gate oxide" structures where an interfacial oxide layer of 40 /spl Aring/ was grown between the high-/spl kappa/ dielectric and Si. DC analysis showed low gate leakage currents in the order of 10/sup -12/A(2-5/spl times/10/sup -5/ A/cm/sup 2/) for the devices and, in general, yielded higher threshold voltages and lower mobility values when compared to the corresponding SiO/sub 2/ devices. The unified number-mobility fluctuation model was used to account for the observed 1/f noise and to extract the oxide trap density, which ranged from 1.8/spl times/10/sup 17/ cm/sup -3/eV/sup -1/ to 1.3/spl times/10/sup 19/ cm/sup -3/eV/sup -1/, somewhat higher compared to conventional SiO/sub 2/ MOSFETs with the similar device dimensions. There was no evidence of single electron switching events or random telegraph signals. The aim of this paper is to present a general discussion on low-frequency noise characteristics of the three different high-/spl kappa//gate stacks, relative comparison among them and to the Si--SiO/sub 2/ system.     

DRAM plate electrode bias optimization for reducing leakage current in UV-O/sub 3/ and O/sub 2/ annealed CVD deposited Ta/sub 2/O/sub 5/ dielectric films

A new plate biasing scheme is described which allowed the use of 65% higher supply voltage without increasing the leakage current for the UV-O/sub 3/ and O/sub 2/ annealed chemical-vapor-deposited tantalum pentaoxide dielectric film capacitors in stacked DRAM cells. Dielectric leakage was reduced by biasing the capacitor plate electrode to a voltage lower than the conventionally used value of V/sub cc//2. Ta/sub 2/O/sub 5/ films with 3.9 nm effective gate oxide, 8.5 fF//spl mu/m/sup 2/ capacitance and <0.3 /spl mu/A/cm/sup 2/ leakage at 100/spl deg/C and 3.3 V supply are demonstrated.<>     

Ni fully GermanoSilicide for gate electrode application in pMOSFETs with HfSiON gate dielectrics

A study on using a novel metal gate-the Ni fully GermanoSilicide (FUGESI)-in pMOSFETs is presented. Using HfSiON high-/spl kappa/ gate dielectrics and comparing to Ni fully Silicide (FUSI) devices, this paper demonstrates that the addition of Ge in poly-Si gate (with Ge/(Si+Ge)/spl sim/50%) results in: 1) an increase of the effective work function by /spl sim/ 210 mV due to Fermi-level unpinning effect; 2) an improved channel interface; 3) a reduced gate leakage; and 4) the superior negative bias temperature instability characteristics. Low-frequency noise measurement reveals a decreased 1/f and generation-recombination noise in FUGESI devices compared to FUSI devices, which is attributed to the reduced oxygen vacancies (V/sub o/)-related defects in the HfSiON dielectrics in FUGESI devices. The reduced V/sub o/-related defects stemming from Ge at FUGESI /HfSiON interface are correlated with the Fermi-level unpinning effect and the improved electrical characteristics observed in FUGESI devices.     

Linewidth effect and phase control in Ni fully silicided gates

The scalability of Ni fully silicided (FUSI) gate processes to short gate lengths was studied for NiSi, Ni/sub 2/Si, and Ni/sub 31/Si/sub 12/. It is shown that the control of the deposited Ni-to-Si ratio is not effective for phase and V/sub t/ control at short gate lengths. A transition to Ni-richer phases at short gate lengths was found for nonoptimized NiSi and Ni/sub 2/Si processes with excessive thermal budgets, resulting in significant V/sub t/ shifts for devices on HfSiON consistent with the difference in work function among the Ni silicide phases. Linewidth-independent phase control with smooth V/sub t/ rolloff characteristics was demonstrated for NiSi, Ni/sub 2/Si, and Ni/sub 31/Si/sub 12/ FUSI gates by controlling the Ni-to-Si reacted ratio through optimization of the thermal budget of silicidation (prior to selective Ni removal). Phase characterization over a wide temperature range indicated that the process windows for scalable NiSi and Ni/sub 2/Si are less than or equal to 25 /spl deg/C, whereas a single-phase Ni/sub 31/Si/sub 12/ is obtained over an /spl sim/200/spl deg/C temperature range.     

Characterization and reliability of dual high-k gate dielectric stack (poly-Si-HfO/sub 2/-SiO/sub 2/) prepared by in situ RTCVD process for system-on-chip applications

We investigate for the first time the possibility of integrating chemical vapor deposition (CVD) HfO/sub 2/ into the multiple gate dielectric system-on-a-chip (SoC) process in the range of 6-7 nm, which supports higher voltage (2.5-5 V operation/tolerance). Results show that CVD HfO/sub 2/-SiO/sub 2/ stacked gate dielectric (EOT =6.2 nm) exhibits lower leakage current than that of SiO/sub 2/ (EOT =5.7 nm) by a factor of /spl sim/10/sup 2/, with comparable interface quality (D/sub it//spl sim/1/spl times/10/sup 10/ cm/sup -2/eV/sup -1/). The presence of negative fixed charge is observed in the HfO/sub 2/-SiO/sub 2/ gate stack. In addition, the addition of HfO/sub 2/ on SiO/sub 2/ does not alter the dominant conduction mechanism of Fowler-Nordheim tunneling in the HfO/sub 2/-SiO/sub 2/ gate stack. Furthermore, the HfO/sub 2/-SiO/sub 2/ gate stack shows longer time to breakdown T/sub BD/ than SiO/sub 2/ under constant voltage stress. These results suggest that it may be feasible to use such a gate stack for higher voltage operation in SoC, provided other key requirements such as V/sub t/ stability (charge trapping under stress) can be met and the negative fixed charge eliminated.     

Si interlayer passivation on germanium MOS capacitors with high-/spl kappa/ dielectric and metal gate

We have demonstrated the advantages of silicon interlayer passivation on germanium MOS devices, with CVD HfO/sub 2/ as the high-/spl kappa/ dielectric and PVD TaN as the gate electrode. A silicon interlayer between a germanium substrate and a high-/spl kappa/ dielectric, deposited using SiH/sub 4/ gas at 580/spl deg/C, significantly improved the electrical characteristics of germanium devices in terms of low D/sub it/ (7/spl times/10/sup 10//cm/sup 2/-eV), less C- V hysteresis and frequency dispersion. Low leakage current density of 5/spl times/10/sup -7/ A/cm/sup 2/ at 1 V bias with EOT of 12.4 /spl Aring/ was achieved. Post-metallization annealing caused continuing V/sub fb/ positive shift and J/sub g/ increase with increased annealing temperature, which was possibly attributed to Ge diffusion into the dielectric during annealing.     

Enhanced negative substrate bias degradation in nMOSFETs with ultrathin plasma nitrided oxide

The degradation induced by substrate hot electron (SHE) injection in 0.13-/spl mu/m nMOSFETs with ultrathin (/spl sim/2.0 nm) plasma nitrided gate dielectric was studied. Compared to the conventional thermal oxide, the ultrathin nitrided gate dielectric is found to be more vulnerable to SHE stress, resulting in enhanced threshold voltage (V/sub t/) shift and transconductance (G/sub m/) reduction. The severity of the enhanced degradation increases with increasing nitrogen content in gate dielectric with prolonged nitridation time. While the SHE-induced degradation is found to be strongly related to the injected electron energy for both conventional oxide , and plasma-nitrided oxide, dramatic degradation in threshold voltage shift for nitrided oxide is found to occur at a lower substrate bias magnitude (/spl sim/-1 V), compared to thermal oxide (/spl sim/-1.5 V). This enhanced degradation by negative substrate bias in nMOSFETs with plasma-nitrided gate dielectric is attributed to a higher concentration of paramagnetic electron trap precursors introduced during plasma nitridation.