Dual work function metal gates using full nickel silicidation of doped poly-Si

This paper investigates the work function adjustment on fully silicided (FUSI) NiSi metal gates for dual-gate CMOS, and how it is effected by the poly-Si dopants. By comparing FUSI on As-, B-, and undoped poly-Si using the same p-Si substrates, it is shown that both As and B influence the work function of NiSi FUSI gate significantly, with As showing more effects than B possibly due to more As pile-up at the NiSi-SiO/sub 2/ interface. No degradations on the underlying gate dielectrics are observed in terms of interface state density (D/sub it/), fixed oxide charges, leakage current, and breakdown voltage, suggesting that NiSi FUSI is compatible with dual-gate CMOS processing.     

Fabrication of metal gated FinFETs through complete gate silicidation with Ni

Metal-gate FinFETs were fabricated using complete gate silicidation with Ni, combining the advantages of metal-gate and double-gate transistors. NiSi-gate workfunction control is demonstrated using silicide induced impurity segregation of As, P, and B over a range of 400 mV. High device performance is achieved by integrating the NiSi metal gate with an epitaxial raised source/drain, silicided separately with CoSi/sub 2/. Process considerations for this dual silicide integration scheme are discussed. Poly-Si gated FinFETs are also fabricated and used as references for workfunction and transconductance.     

点接触平面栅型硅单电子晶体管

设计了点接触平面栅型硅单电子晶体管,利用自对准技术实现了点接触平面栅,并通过给平面栅施加偏压实现了量子点。讨论了点接触平面栅型单电子晶体管与其通道宽度和平面栅上电压的关系。对一个具有70nm宽通道的器件,先在其表面栅上施加很小的正偏压,然后又在其平面栅上施加负偏压耗尽通道,最终的研究结果显示在通道中形成了单个量子点。     

A study on the leakage current of poly-Si TFTs fabricated by metal induced lateral crystallization

Leakage current of poly-Si TFT fabricated by a metal induced lateral crystallization(MILC) process was investigated in terms of metal contamination and crystallization mechanisms. MILC poly-Si TFTs showed a higher leakage current than those by the solid phase crystallization method at high drain voltages. It turned out that the Ni rich phases in the depleted junction region played the role of trapping and recombination centers to generate the leakage currents and that the leakage current was generated by thermionic field emission. The leakage current could be drastically reduced to 5 pA/μm at V_GS=0 V and V_DS=15 V after the exclusion of the Ni-rich phase from the junction region by a Ni offset MILC process.     

Advanced poly-Si TFT with fin-like channels by ELA

The advanced low-temperature polysilicon (poly-Si) thin-film transistor with three-dimensional channels of fin-like profile has been demonstrated using excimer laser annealing and unique undercut structure without any additional patterning process. This approach provides a very narrow fin-like channel in devices with high ratio of film thickness to the width as well as a high-quality poly-Si film in channels with better crystallinity for the effect of columnar-like grain growth following the shrinkage of silicon stripe after laser irradiation. Due to that and the stronger electrical stress on the channel by the multigate, the new device with a fin-like channel structure shows good characteristics of the highest mobility up to 395 cm/sup 2//V/spl middot/s, a subthreshold voltage slope below 400 mV/dec, and an ON-OFF current ratio higher than 10/sup 6/.     

The fabrication and dry etching of poly-Si/TaN/Mo gate stack in the metal inserted poly-Si stack structure

The Mo-based metal inserted poly-Si stack (MIPS) structure is an appropriate choice for metal gate and high-k integration in sub-45 nm gate-first CMOS device. A novel metal nitride layer of TaN or AlN with high thermal stability has been introduced between Mo and poly-Si as a barrier material to avoid any reaction of Mo during poly-Si deposition. After Mo-based MIPS structure is successfully prepared, dry etching of poly-Si/TaN/Mo gate stack is studied in detail. The three-step plasma etching using the Cl₂/HBr chemistry without soft landing step has been developed to attain a vertical poly-Si profile and a reliable etch-stop on the TaN/Mo metal gate. For the etching of TaN/Mo gate stack, two methods using BCl₃/Cl₂/O₂/Ar plasma are presented to get both vertical profile and smooth etched surface, and they are critical to get high selectivity to high-k dielectric and Si substrate. In addition, adding a little SF₆ to the BCl₃/O₂/Ar plasma under the optimized conditions is also found to be effective to smoothly etch the TaN/Mo gate stack with vertical profile.     

Direct silicidation of Co on Si by rapid thermal annealing

Rapid thermal annealing is used to form cobalt silicide directly on unimplanted as well as B-, As-, and P-implanted wafers. The films are characterized by sheet resistance, X-ray diffraction, SEM, TEM, SIMS, and contact resistance measurements. The direct silicidation of Co on Si by rapid thermal annealing yields smooth low-resistivity films with minimal dopant redistribution.     

Fabrication of short channel MOSFETs with refractory metal gates using RF sputter etching

Fabrication of sub-μm p-channel MOSFETs with refractory metal gates using novel refinements of conventional photolithographic procedures is described. The method avoids the need for direct electron beam writing on the wafer and for ion implantation instead of diffusion. Autoregistration Mo gate structures down to 2 μm corresponding to an estimated channel length of 0 · 7 μm were made using RF sputter etching for the drain-source windows while masking with a positive photoresist. This was contact patterned using a chromium-on-glass mask made by electron beam writing and RF sputter etching. Sputter-deposited boron-doped SiO₂ was used as the diffusion source for the source-drain areas.The transistors were made on (100) phosphorus doped n-type silicon with an impurity concentration of 2 . 10¹⁶ cm^?3. Fabricated devices with channel lengths ≥ 1 · 7 μm had an apparent threshold voltage of 2·5 V (10 μA criterion) and for 1·7 μm channel length an apparent punch-through voltage of 18 V. A sputtered Mo layer ? 1 μm thick was used as gate material.A distinct advantage of using sputter etching with a single system capable of both deposition and etching is that it is possible to go directly to the next steps without exposure to air. These steps are mask removal in a partial H₂ and O₂ plasma, followed by further Argon sputter-etching and sputter deposition of a doped oxide diffusion source on the sputter-etched cleaned surface. This promises a better reproducibility of surface doping as there should be less oxide and less contamination than in conventional processes. The characteristics of the fabricated transistors did not indicate any un-annealable drift or gate oxide damage due to the presence of the plasma provided the Mo layer was sufficiently thick. Thus sputter etching which offers good resolution can be used in MOS fabrication.Due to its lower resistivity, Mo, which can be used an an additional interconnection layer (isolated from the A1 layer) offers better speed potential than Si, in certain types of circuits, e.g. high speed memories with long address lines.With a proper background doping of the wafer and diffusion time and temperature it was possible to obtain $\text{? 0 · 6 μm}$ lateral diffusion below the gate from both source and drain regions. It was thus possible to obtain sub-μm p-channel MOSFETs even while working close to the limits of normal optical contact production of micropatterns, which is 1–2 μm.     

Performance of poly-Si TFTs fabricated by SELAX

Selectively enlarging laser crystallization (SELAX) has been proposed as a new crystallization process for use in the fabrication of thin-film transistors (TFTs). This method is capable of producing a large-grained and flat film of poly-Si. The average grain size is 0.3/spl times/5 /spl mu/m, and the surface roughness of the poly-Si layer is less than 5 nm. The TFTs fabricated with this method have better performance and are more uniform than those produced with the conventional excimer laser crystallization (ELC) method. The average values of field-effect mobility are 440 cm/sup 2//Vs (n-type), and 130 cm/sup 2//Vs (p-type). The subthreshold slope for both types is 0.20 V/dec. Values for standard deviation of threshold voltage are 0.03 V (n-type) and 0.20 V (p-type). The delay time of the CMOS-inverter of SELAX TFTs is less than half that of ELC TFTs.     

Manufacturability of 20-nm ultrathin body fully depleted SOI devices with FUSI metal gates

Ultrathin body (UTB) fully depleted silicon-on-insulator (FDSOI) devices show great performance due to undoped channels and excellent electrostatic control. Very high drive currents and good off-state leakage, ideal subthreshold slope, and small drain-induced barrier lowering (DIBL) have been reported with devices as short as 20 nm. The ultrathin channel enables high device performance, but it imposes a new set of problems. The control of the silicon thickness has become the dominant source of device variations. Selective epitaxial growth has become a necessity to achieve high performance and reliable contacts to UTB FDSOI devices. This work discusses silicon thickness control, selective epitaxial growth, and the mid-gap gate module needed for fully depleted devices. Very good control of short channel effect is shown and drive current fluctuations are discussed.     

High-performance poly-Si TFTs fabricated by implant-to-silicide technique

High-performance poly-Si thin-film transistors (TFTs) with fully silicided source/drain (FSD) and ultrashort shallow extension (SDE) fabricated by implant-to-silicide (ITS) technique are proposed for the first time. Using the FSD structure, the S/D parasitic resistance can be suppressed effectively. Using the ITS technique, an ultrashort and defect-free SDE can also be formed quickly at about 600/spl deg/C. Therefore, the FSD poly-Si TFTs exhibits better current-voltage characteristics than those of conventional TFTs. It should be noted that the on/off current ratios of FSD poly-Si TFT (W/L=1/4/spl mu/m) is over 3.3/spl times/10/sup 7/, and the field-effective mobility of that device is about 141.6 (cm/sup 2//Vs). Moreover, the superior short-channel characteristics of FSD poly-Si TFTs are also observed. It is therefore believed that the proposed FSD poly-Si TFT is a very promising TFT device.     

Fabrication of poly-Si thick films by electrophoretic deposition

The electrophoresis of silicon particles in acetone, and the electrophoretic deposition of poly-silicon thick films are reported for the first time. The anodic deposition of Si particles was achieved by applying DC electric fields of ~100 V/cm between two electrodes soaked in a semistable acetone suspension. Uniform layers were reproducibly formed on gold, graphite and silicon wafer anodes (substrates). The technique was successfully applied on substrates of complicated shapes     

High-performance poly-Si TFTs with ECR-plasma hydrogen passivation

High-performance thin-film transistors (TFTs) with electron-cyclotron resonance (ECR) plasma hydrogen passivation fabricated by the use of laser-recrystallized multiple-strip-structure poly-Si film are discussed. These TFTs have n-channel enhancement-mode characteristics with a large transconductance, a high switching ratio, and a threshold voltage as low as 0.4 v. The ECR-plasma hydrogen passivation of laser-recrystallized poly-Si, reduces the trap density of poly-Si and increases the carrier mobility thus, desirable TFT characteristics are obtained. This passivation increased the transconductance (g_m) of a TFT and decreased the leakage current between the source and the drain. As a result, a switching ratio as high as 2.5×10⁹ and very low leakage current of the order of 10¹⁴ A can be achieved by these high-performance TFTs     

A poly-Si AMOLED display with high uniformity

An active-matrix organic light-emitting diode (AMOLED) display based on the polycrystalline silicon backplane technology has been fabricated that employs a new pixel circuit to compensate for the variation in the threshold voltage of the thin film transistors (TFT). The new pixel circuit also copes with the voltage drop in the supply line and a very high contrast ratio can be achieved. The uniformity of the new AMOLED display is remarkably improved compared with the basic two-TFT pixel structure, and it can be readily applied in the mass production of commercial AMOLED displays.     

Excimer-laser crystallized poly-Si TFT's with transparent gate

A new poly-crystal silicon thin-film transistor (poly-Si TFT) with a transparent bottom-gate electrode has been fabricated by XeF excimer-laser light irradiation from the glass substrate side. Compared with poly-Si TFTs made by XeF or ArF excimer-laser light irradiation to the top Si surface, the new TFT shows a higher electron mobility of about 100 cm²/Vs, independent of the Si film thickness. Therefore, poly-Si driver TFTs and amorphous-silicon (a-Si) TFTs for the matrix can be formed with the same channel-etch type bottom-gate structure simultaneously on the same glass substrate by using the same starting materials. This is expected to open the way for making driver monolithic and active matrix liquid crystal displays     

Submicrometer poly-Si CMOS fabrication with low-temperature laserdoping

The laser doping process for submicrometer CMOS devices with leakage currents as low as 10^-12 A/μm for both n-channel and p-channel devices is discussed. The I-V characteristics are comparable to those of poly-Si devices fabricated using ion implantation and high-temperature annealing processes. The laser-induced melting of predeposited impurity doping (LIMPID) process was used to fabricate submicrometer polycrystalline-Si CMOS devices. This process uses a very low temperature, so no dopant atom can diffuse along the grain boundaries in the solid region. The use of stacked Al/SiO₂ films as a protection layer made it possible to reduce the leakage current from several tens of picoamperes per micrometer to 1 pA/μm     

Thin-film transistors fabricated with poly-Si films crystallized atlow temperature by microwave annealing

Solid phase crystallization of amorphous silicon films for poly-Si thin film transistors (TFTs) has advantages of low cost and excellent uniformity, but the crystallization temperature is too high. Using a microwave annealing method, we lowered the crystallization temperature and shortened the crystallization time. The complete crystallization time at 550°C was within 2 h. The device parameters of TFTs with the poly-Si films crystallized by microwave annealing were similar to those of TFTs with the poly-Si films crystallized by conventional furnace annealing. The new crystallization method seems attractive because of low crystallization temperature, short crystallization time, and comparable film properties     

Thickness determination of poly-Si/poly-oxide/poly-Si/SiO/sub 2//Si structure by ellipsometer

An ellipsometry measurement method is proposed to measure poly-Si/poly-oxide/poly-Si/SiO/sub 2//Si structure. The thickness of each layer in this structure can be easily obtained by a conventional ellipsometry measurement. The measured result is consistent with that of cross-sectional TEM.<>     

Improved control of momentary rapid thermal annnealing for silicidation

Temperature control and wafer-to-wafer reproducibility during momentary annealing via rapid thermal annealing is critical for TiSi₂ Self-Aligned siLICIDE (SALICIDE) processing for deep submicron complementary metal oxide semiconductor. TiSi₂ must undergo a transformation from the high resistivity C49 phase to the low resistivity C54 phase for applications where it is used as a gate conductor. A process modification to achieve improved wafer-to-wafer and within wafer temperature reproducibility is demonstrated. It has the additional benefit to the TiSi₂ salicide process of enabling anneals of reduced duration, enhancing suicide transformation to the desired phase without leading to agglomeration.