A Comparative NBTI Study of $hbox{HfO}_{2}$, $hbox{HfSiO}_{x}$, and SiON p-MOSFETs Using UF-OTF $I_{rm DLIN}$ Technique

The time, temperature, and oxide-field dependence of negative-bias temperature instability is studied in $hbox{HfO}_{2}/hbox{TiN}$, $ hbox{HfSiO}_{x}/hbox{TiN}$, and SiON/poly-Si p-MOSFETs using ultrafast on-the-fly $I_{rm DLIN}$ technique capable of providing measured degradation from very short (approximately microseconds) to long stress time. Similar to rapid thermal nitrided oxide (RTNO) SiON, $hbox{HfO}_{2}$ devices show very high temperature-independent degradation at short (submilliseconds) stress time, not observed for plasma nitrided oxide (PNO) SiON and $hbox{HfSiO}_{x}$ devices. $hbox{HfSiO}_{x}$ shows lower overall degradation, higher long-time power-law exponent, field acceleration, and temperature activation as compared to $hbox{HfO}_{2}$, which are similar to the differences between PNO and RTNO SiON devices, respectively. The difference between $ hbox{HfSiO}_{x}$ and $hbox{HfO}_{2}$ can be attributed to differences in N density in the $hbox{SiO}_{2}$ IL of these devices.      

Nitrided Tetragonal $hbox{ZrO}_{2}$ as the Charge-Trapping Layer for Nonvolatile Memory Application

Employment of a tetragonal $hbox{ZrO}_{2}$ film as the charge-trapping layer for nonvolatile memory was investigated and the $ hbox{NH}_{3}$ nitridation effect of the $hbox{ZrO}_{2}$ film on memory performance was also explored in this letter. The permittivity of the tetragonal $hbox{ZrO}_{2}$ film is slightly reduced from 38.7 to 36.9 after nitridation; nevertheless, nitridation introduces more trapping sites and passivates the grain boundary channel which results in a high operation speed in terms of 2.6-V flatband voltage shift by programming at $+$10 V for 10 ms and a good retention characteristic with 20.2% charge loss after ten-year operation at 125 $^{circ}hbox{C}$, both are superior to that without $hbox{NH}_{3}$ nitridation. Most importantly, the process is fully compatible with existent ULSI technology and paves the way to adopt a high-permittivity crystalline dielectric as the charge-trapping layer for future high-performance nonvolatile memory.      

Impacts of $hbox{N}_{2}$ and $hbox{NH}_{3}$ Plasma Surface Treatments on High-Performance LTPS-TFT With High-$kappa$ Gate Dielectric

Low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFTs) with high- $kappa$ gate dielectrics and plasma surface treatments are demonstrated for the first time. Significant field-effect mobility $mu_{rm FE}$ improvements of $sim$86.0% and 112.5% are observed for LTPS-TFTs with $hbox{HfO}_{2}$ gate dielectric after $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments, respectively. In addition, the $hbox{N}_{2}$ and $ hbox{NH}_{3}$ plasma surface treatments can also reduce surface roughness scattering to enhance the field-effect mobility $mu_{rm FE}$ at high gate bias voltage $V_{G}$, resulting in 217.0% and 219.6% improvements in driving current, respectively. As a result, high-performance LTPS-TFT with low threshold voltage $V_{rm TH} sim hbox{0.33} hbox{V}$, excellent subthreshold swing S.S. $sim$0.156 V/decade, and high field-effect mobility $mu_{rm FE} sim hbox{62.02} hbox{cm}^{2}/hbox{V} cdot hbox{s}$ would be suitable for the application of system-on-panel.      

Scaling Properties of $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ Core–Shell Nanowire Field-Effect Transistors

We demonstrate the fabrication of high-performance $hbox{Ge}$ –$hbox{Si}_{x}hbox{Ge}_{1 - x}$ core–shell nanowire (NW) field-effect transistors with highly doped source (S) and drain (D) and systematically investigate their scaling properties. Highly doped S and D regions are realized by low-energy boron implantation, which enables efficient carrier injection with a contact resistance much lower than the NW resistance. We extract key device parameters, such as intrinsic channel resistance, carrier mobility, effective channel length, and external contact resistance, as well as benchmark the device switching speed and on/off current ratio.      

Nonvolatile-Memory Characteristics of $hbox{AlO}^{-}$ -Implanted $hbox{Al}_{2}hbox{O}_{3}$

The nonvolatile-memory (NVM) characteristics of $hbox{AlO}^{-}$ -implanted $hbox{Al}_{2}hbox{O}_{3}$ structures are reported and shown to exhibit promising behaviors, including fast program/erase speeds and high-temperature data retention. Photoconductivity spectra show the existence of two dominant trap levels, located at around 2 and 4 eV below the conduction band minimum of $hbox{Al}_{2}hbox{O}_{3}$, and our calculations show that these levels are likely attributed to the defects in the $hbox{Al}_{2}hbox{O}_{3}$, such as the Al–O divacancy. The relative concentrations of these defects vary with the implant fluence and are shown to explain the NVM characteristics of the samples irradiated to different fluences.      

Resistive Switching Properties of $hbox{Au}/ hbox{ZrO}_{2}/hbox{Ag}$ Structure for Low-Voltage Nonvolatile Memory Applications

The reliable resistive switching properties of $hbox{Au}/hbox{ZrO}_{2}/ hbox{Ag}$ structure fabricated with full room temperature process are demonstrated in this letter. The tested devices show low operation voltages ($≪hbox{1}$ V), high resistance ratio (about $hbox{10}^{4}$), fast switching speed (50 ns), and reliable data retention (ten years extrapolation at both RT and 85 $^{circ}hbox{C}$). Moreover, the benefits of high yield and multilevel storage possibility make them promising in the next generation nonvolatile memory applications.      

Improvement of Resistive Switching in $hbox{Cu}_{x} hbox{O}$ Using New RESET Mode

Wide dispersions of memory switching parameters are observed in resistive random access memory based on $hbox{Al/Cu}_{x}hbox{O/Cu}$ structure. Moreover, the switching instability induced by these dispersions is studied. In this letter, a ramped-pulse series operation method is put forward, which can improve switching stability and cycling endurance remarkably. A method for minimizing the dispersion of $V_{rm reset}$ by optimizing the amplitude of pulse is proposed further. The write–read–erase–read operations can be over $hbox{8} times hbox{10}^{3}$ cycles without degradation by using the new operation mode. The role of Joule heating behind this behavior of $ hbox{Al/Cu}_{x}hbox{O/Cu}$ device is discussed.      

$hbox{HfO}_{x}$ Bipolar Resistive Memory With Robust Endurance Using AlCu as Buffer Electrode

A novel method of fabricating $hbox{HfO}_{x}$-based resistive memory device with excellent nonvolatile characteristics is proposed. By using a thin AlCu layer as the reactive buffer layer into the anodic side of a capacitor-like memory cell, excellent memory performances, which include reliable programming/erasing endurance $(≫ hbox{10}^{5} hbox{cycles})$, robust data retention at high temperature, and fast operation speed ( $≪$ 50 ns), have been demonstrated. The resistive memory based on AlCu/$hbox{HfO}_{x}$ stacked layer in this letter shows promising application in the next generation of nonvolatile memory.      

High-Performance $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ -Channel MOSFETs With High-$kappa$ Gate Dielectrics and $alpha$-Si Passivation

Long and short buried-channel $hbox{In}_{0.7}hbox{Ga}_{0.3}hbox{As}$ MOSFETs with and without $alpha$-Si passivation are demonstrated. Devices with $alpha$-Si passivation show much higher transconductance and an effective peak mobility of 3810 $hbox{cm}^{2}/ hbox{V} cdot hbox{s}$. Short-channel MOSFETs with a gate length of 160 nm display a current of 825 $muhbox{A}/muhbox{m}$ at $V_{g} - V_{t} = hbox{1.6} hbox{V}$ and peak transconductance of 715 $muhbox{S}/muhbox{m}$. In addition, the virtual source velocity extracted from the short-channel devices is 1.4–1.7 times higher than that of Si MOSFETs. These results indicate that the high-performance $hbox{In}_{0.7}hbox{Ga}_{0.3} hbox{As}$-channel MOSFETs passivated by an $alpha$ -Si layer are promising candidates for advanced post-Si CMOS applications.      

High-Performance Poly-Silicon TFTs Using a High-$k$ $hbox{PrTiO}_{3}$ Gate Dielectric

In this letter, a polycrystalline-silicon thin-film transistor (poly-Si TFT) with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is proposed for the first time. Compared to TFTs with a $hbox{Pr}_{2}hbox{O}_{3}$ gate dielectric, the electrical characteristics of poly-Si TFTs with a $hbox{PrTiO}_{3}$ gate dielectric can be significantly improved, such as lower threshold voltage, smaller subthreshold swing, higher $I_{rm on}/I_{rm off}$ current ratio, and larger field-effect mobility, even without any hydrogenation treatment. These improvements can be attributed to the high gate capacitance density and low grain-boundary trap state. All of these results suggest that the poly-Si TFT with a high- $k$ $hbox{PrTiO}_{3}$ gate dielectric is a good candidate for high-speed and low-power display driving circuit applications in flat-panel displays.      

Improved Electrical Properties of Ge p-MOSFET With $ hbox{HfO}_{2}$ Gate Dielectric by Using $hbox{TaO}_{x} hbox{N}_{y}$ Interlayer

The electrical characteristics of germanium p-metal-oxide-semiconductor (p-MOS) capacitor and p-MOS field-effect transistor (FET) with a stack gate dielectric of HfO₂/TaOxNy are investigated. Experimental results show that MOS devices exhibit much lower gate leakage current than MOS devices with only HfO₂ as gate dielectric, good interface properties, good transistor characteristics, and about 1.7-fold hole-mobility enhancement as compared with conventional Si p-MOSFETs. These demonstrate that forming an ultrathin passivation layer of TaOxNy on germanium surface prior to deposition of high-k dielectrics can effectively suppress the growth of unstable GeOx, thus reducing interface states and increasing carrier mobility in the inversion channel of Ge-based transistors.     

ZnO Nanowire and $hbox{WS}_{2}$ Nanotube Electronics

In this paper, we report on the synthesis and applications of semiconducting nanostructures. Nanostructures of interest were zinc oxide (ZnO) nanowires and tungsten disulfide $(hbox{WS}_{2})$ nanotubes where transistors/phototransistors and photovoltaic (PV) energy conversion cells have been fabricated. ZnO nanowires were grown with both high- and low-temperature approaches, depending on the application. Individual ZnO nanowire side-gated transistors revealed excellent performance with a field-effect mobility of 928 $hbox{cm}^{2}/hbox{V} cdot hbox{s}$. ZnO networks were proposed for large-area macroelectronic devices as a less lithographically intense alternative to individual nanowire transistors where mobility values in excess of 20 $ hbox{cm}^{2}/hbox{V} cdot hbox{s}$ have been achieved. Flexible PV devices utilizing ZnO nanowires as electron acceptors and for photoinduced charge separation and transport have been presented. Phototransistors were fabricated using individual $hbox{WS}_{2}$ nanotubes, where clear sensitivity to visible light has been observed. The results presented here simply reveal the potential use of inorganic nanowires/tubes for various optoelectronic devices.      

The $hbox{Pd/TiO}_{2}$/ $hbox{n}$-LTPS Thin-Film Schottky Diode on Glass Substrate for Hydrogen Sensing Applications

A $hbox{Pd/TiO}_{2}$/n-type low-temperature-polysilicon (n-LTPS) MOS thin-film Schottky diode fabricated on a glass substrate for hydrogen sensing is reported. The n-LTPS is an excimer-laser-annealed and $hbox{PH}_{3}$ -gas-plasma-treated amorphous-silicon (a-Si) thin film. At room temperature and $-$2-V bias, the developed MOS Schottky diode exhibited a high signal ratio of 1540 to 50 ppm of hydrogen gas, with a fast response time of 40 s, respectively. The signal ratio is better or comparable with that of other reported MOS-type hydrogen gas sensors prepared on Si or III–V compound substrate. In addition, the signal ratio is 7.6, 14, and 30 times over other interfering gases of $ hbox{C}_{2}hbox{H}_{5}hbox{OH}$, $hbox{C}_{2}hbox{H}_{4}$ , and $hbox{NH}_{3}$ at room temperature and a concentration of 8000 ppm at $-$2-V bias, respectively. Thus, the developed MOS Schottky diode shows promise for the future development and commercialization of a low-cost hydrogen sensor.      

AlGaN/GaN MOS-HEMT With $hbox{HfO}_{2}$ Dielectric and $hbox{Al}_{2}hbox{O}_{3}$ Interfacial Passivation Layer Grown by Atomic Layer Deposition

We have developed a novel AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistor using a stack gate HfO₂/Al₂O₃ structure grown by atomic layer deposition. The stack gate consists of a thin HfO₂ (30-A) gate dielectric and a thin Al₂O₃ (20- A) interfacial passivation layer (IPL). For the 50-A stack gate, no measurable C-V hysteresis and a smaller threshold voltage shift were observed, indicating that a high-quality interface can be achieved using a Al₂O₃ IPL on an AlGaN substrate. Good surface passivation effects of the Al₂O₃ IPL have also been confirmed by pulsed gate measurements. Devices with 1- mum gate lengths exhibit a cutoff frequency (fT) of 12 GHz and a maximum frequency of oscillation (f _MAX) of 34 GHz, as well as a maximum drain current of 800 mA/mm and a peak transconductance of 150 mS/mm, whereas the gate leakage current is at least six orders of magnitude lower than that of the reference high-electron mobility transistors at a positive gate bias.     

Excellent Switching Uniformity of Cu-Doped $hbox{MoO}_{x}/hbox{GdO}_{x}$ Bilayer for Nonvolatile Memory Applications

We have investigated a Cu-doped MoO_x/GdO_x bilayer film for nonvolatile memory applications. By adopting an ultrathin GdO_x layer, we obtained excellent device characteristics such as resistance ratio of three orders of magnitude, uniform distribution of set and reset voltages, switching endurance up to 10⁴ cycles, and ten years of data retention at 85degC. By adopting bilayer films of Cu-doped MoO_x/GdO_x, a local filament was formed by a two-step process. Improved memory characteristics can be explained by the formation of nanoscale local filament in the ultrathin GdO_x layer.     

$hbox{VO}_{2}$ Thin-Film Varistor Based on Metal-Insulator Transition

For electronic applications, we have fabricated VO₂ thin-film variable resistors (varistors) using metal-insulator transition regarded as the abrupt current jump. The increase of the number of parallel stripe patterns in the varistor leads to the increase in current below a current-jump voltage, which endures a high surge voltage with high current and short rising time. Electrostatic discharge (ESD) experiments show that the varistic coefficient of 500 is larger than 30-80, which is known for commercial ZnO varistors. In overvoltage-protection tests applying high ESD voltages up to 3.3 kV to a varistor, the maximum response voltage is lower than 200 V at an ESD voltage of 1600 V, and the electronic response time is less than 20 ns. This is sufficient to protect a device perfectly.     

Improvement of On–Off-Current Ratio in $ hbox{TiO}_{rm x}$ Active-Channel TFTs Using $hbox{N}_{2} hbox{O}$ Plasma Treatment

Without sacrificing the on-current in the transfer characteristics, we have successfully reduced the off-current part by the optimal $hbox{N}_{2}hbox{O}$ plasma treatment to improve the on–off-current ratio in n-type titanium oxide $( hbox{TiO}_{rm x})$ active-channel thin-film transistors. While the high-power (275 W) $hbox{N}_{2}hbox{O}$ plasma treatment oxidizes the whole $hbox{TiO}_{rm x}$ channel and results in the reduction of both on- and off-current, the optimized low-power (150 W) process makes the selective oxidation of the top portion in the channel and reduces only the off-current significantly. Increase in on–off ratio by almost five orders of magnitude is achieved without change in on-current by using the presented method.      

A Novel 4.5$hbox{F}^{2}$ Capacitorless Semiconductor Memory Device

This letter proposes a novel 4.5$hbox{F}^{2}$ capacitorless dynamic random access memory cell with a floating gate (FG) connected to drain via a gated p-n junction diode. The FG in the proposed memory device is for charge storage and can electrically be charged or discharged by current flowing through a gated p-n junction diode.      

Negative Differential Resistance in Buried-Channel $hbox{Ge}_{x} hbox{C}_{1 - x}$ pMOSFETs

We study the device characteristics of Si-capped $hbox{Ge}_{x}hbox{C}_{1 - x}$ pMOSFETs from room temperature down to 77 K. The output characteristics of these devices reveal a negative differential resistance (NDR) at temperatures below 150 K. Our measurements indicate a higher effective carrier mobility in the buried-channel $hbox{Ge}_{x}hbox{C}_{1 - x}$ with respect to the Si-reference sample, which suggests that the observed NDR is due to real-space transfer of hot holes from the higher mobility $hbox{Ge}_{x}hbox{C}_{1 - x}$ channel layer into the lower mobility Si cap layer.      

Unipolar Switching Behaviors of RTO $hbox{WO}_{X}$ RRAM

The microstructure and electrical properties of the $hbox{WO}_{X}$ -based resistive random access memory are investigated in this letter. The $hbox{WO}_{X}$ layer is formed by converting the surface of the W plug with a CMOS-compatible rapid thermal oxidation process. The conductive-atomic-force-microscopy result indicates that nanoscale conducting channels exist in the $hbox{WO}_{X}$ layer and result in a low initial resistance. This letter studies the unipolar operation—the programming, reading, and reliability behaviors of the device are characterized systematically. The low programming voltages for RESET (3.3 V/50 ns) and fast SET speed (3 V/300 ns) are achieved along with cycling endurance greater than $hbox{10}^{7}$ times. In addition, the device is immune to read disturb. A 2-bit/cell operation is also demonstrated for high-density applications.