A circuit-level methodology for leakage power reduction of high-efficient compressors in 22-nm CMOS technology

Analog Integrated Circuits and Signal Processing - A new circuit-level methodology called input controlled leakage restrainer transistor (ICLRT) compatible with single threshold CMOS technology is...     

A VLSI design methodology for distributed arithmetic

Real-time signal processing requires fast computation of inner products. Distributed arithmetic is a method of inner product computation that uses table-lookup and addition in place of multiplication. Distributed arithmetic has previously been shown to produce novel and seemingly efficient architectures for a variety of signal processing computations; however the methods of design, analysis and comparison have been ad hoc. We propose a systematic method for synthesizing optimal VLSI architectures using distributed arithmetic.A partition of the inner product computation at the word and bit level produces a computation consisting of lookups and additions. We study two classes of algorithms to implement this computation, regular iterative algorithms and tree algorithms, each of which can be expressed in the form of a dependency graph. We use linear and nonlinear maps to assign computations to processors in space and time. Expressions are developed for the area, latency, period and arithmetic error for a particular partition and space/time map of the dependecy graph. We use these expressions to formulate a constrained optimization problem over a large class of architectures. We compare distributed arithmetic with more conventional methods for inner product computation and show how area, latency and period may be traded off while maintaining constant error.This work was supported by Ball Aerospace, Boulder, CO and by the Office of Naval Research, Electronics Branch, Arlington, VA under contract ONR 89-J-1070.     

A distributed intelligence methodology for railway traffic control

A distributed approach to railway traffic control is described. The approach overcomes the upper bounds imposed on the size of controlled areas by the requirement for real-time processing when centralized methodologies are applied. The control problem is modeled in terms of resource allocation tasks, and the concept of priority is generalized to rule local control decisions. The analysis of a global network's behavior, as derived from the integration of local microdecisions, prefigures a depletion effect which will protect the system from traffic jam collapses. Simulation runs are reported to show the control system's overall operation     

Ground bouncing noise reduction technique considering wake-up delay in MTCMOS circuits

Multi-Threshold CMOS (MTCMOS) is an effective technique for controlling leakage power with low delay overhead. However the large magnitude of ground bouncing noise induced by the sleep to active mode transition may cause signal integrity problem in MTCMOS circuits. We propose a methodology for reducing ground bouncing noise under the wake-up delay constraint. An improved two-stage parallel power gating structure that can suppress the ground bouncing noise through turn on sets of sleep transistors consecutively is proposed. The size of each sleep transistor is optimized by a novel sizing algorithm based on a simple discharging model. Simulation results show that the proposed techniques achieve at least 23% improvement in the product of the peak amplitude of ground bouncing noise and the wake-up time when compared with other existing techniques.     

静态存储器保持状态下几种不同漏电流压制技术的漏电流拆分式分析

SRAM standby leakage reduction plays a pivotal role in minimizing the power consumption of application processors.Generally,four kinds of techniques are often utilized for SRAM standby leakage reduction: V_dd lowering（VDDL）,V_ss rising（VSSR）,BL floating（BLF） and reversing body bias（RBB）.In this paper,we comprehensively analyze and compare the reduction effects of these techniques on different kinds of leakage.It is disclosed that the performance of these techniques depends on the leakage composition of the SRAM cell and temperature.This has been verified on a 65 nm SRAM test macro.     

A 0.5-V MTCMOS/SIMOX logic gate

This paper proposes a multithreshold CMOS (MTCMOS) circuit that uses SIMOX process technology. This MTCMOS/SIMOX circuit combines fully depleted low-threshold CMOS logic gates and partially depleted high-threshold power-switch transistors. The low-threshold CMOS gates have a large noise margin for fluctuations in operating temperature in addition to high-speed operation at the low supply voltage of 0.5 V. The high-threshold power-switch transistor in which the body is connected to the gate through the reverse-diode makes it possible to obtain large channel conductance in the active mode without any increase of the leakage current in the sleep mode. The effectiveness of the MTCMOS/SIMOX circuit is confirmed by an evaluation of a gate-chain test element group (TEG) and an experimental 0.5-V, 40-MHz, 16-b ALU, which were designed and fabricated with 0.25-μm MTCMOS/SIMOX technology     

An MTCMOS technology for low-power physical design

Multi-threshold CMOS (MTCMOS) technology is an effective sub-threshold leakage power reduction method in CMOS circuits, which satisfies high-performance and low-power design requirements. The optimization of virtual supply network plays an important role in MTCMOS low-power design. Existing low-power works are mainly on gate level, without any optimization on physical design level, which can lead to a large amount of virtual supply networks. Merging the objective of virtual networks minimization into physical design, this paper presents (1) a low-power-driven physical design flow; (2) a novel low-power placement to simultaneously place standard cells and sleep transistors; and (3) the sleep transistor relocation technique to further reduce the virtual supply networks. Experimental results are promising for both achieving up to 28.15% savings for virtual supply networks and well controlling the increase of signal nets.     

一种新型的抑制地线反弹噪声的Tri-ModeMTCMOS电路结构

提出了一种新型的MTCMOS电路结构。该结构在Tri-Mode MTCMOS电路基础上,结合叠加门控技术,进行电路结构改进,解决了Tri-Mode MTCMOS电路结构在高电压情况下抑制地线反弹噪声效果不明显的问题。电路采用SMIC 0.18 μm CMOS工艺设计,使用HSPICE进行仿真。仿真结果表明,该结构与传统的MTCMOS电路相比,平均地线反弹减少约70%,比Tri-Mode MTCMOS结构提高15%以上,特别在高电压情况下,平均提升40%。     

A 1-V high-speed MTCMOS circuit scheme for power-down applicationcircuits

This paper proposes a new multithreshold-voltage CMOS circuit (MTCMOS) concept aimed at achieving high-speed, ultralow-power large-scale integrators (LSI's) for battery-driven portable equipment. The “balloon” circuit scheme based on this concept preserves data during the power-down period in which the power supply to the circuit is cut off in order to reduce the standby power. Low-power, high-speed performance is achieved by the small preserving circuit which can be separated from the critical path of the logic circuit. This preserving circuit is not only three times faster than a conventional MTCMOS one, but it consumes half the power and takes up half the area. Using this scheme for an LSI chip, 20-MHz operation at 1.0 V and only a few nA standby current was achieved with 0.5-μm CMOS technology. Moreover, this scheme is effective for high speed and low-power operation in quarter-micrometer and finer devices     

A methodology for the design of distributed search in P2P middleware

Important research efforts are being conducted in the area of search, lookup, and routing, and are even increasing in the quest for P2P middleware that is both scalable and decentralized. To structure and classify current as well as facilitate and give direction to future research, this methodology proposes a top-down two-dimensional design space. This design space has been developed for exhaustiveness so as to cover all possible design options, existing or yet to be conceived. A comprehensive survey of P2P search systems serves as a reference for the reader while at the same time validating the framework. An identification of areas in the design space not covered by current systems leads to the design of a novel peer-to-peer-based keyword routing scheme. Finally, an evaluation of possible design options along the most important requirement will help guide system designers.     

A combined gate replacement and input vector control approach for leakage current reduction

Input vector control (IVC) is a popular technique for leakage power reduction. It utilizes the transistor stack effect in CMOS gates by applying a minimum leakage vector (MLV) to the primary inputs of combinational circuits during the standby mode. However, the IVC technique becomes less effective for circuits of large logic depth because the input vector at primary inputs has little impact on leakage of internal gates at high logic levels. In this paper, we propose a technique to overcome this limitation by replacing those internal gates in their worst leakage states by other library gates while maintaining the circuit's correct functionality during the active mode. This modification of the circuit does not require changes of the design flow, but it opens the door for further leakage reduction when the MLV is not effective. We then present a divide-and-conquer approach that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits. Our experimental results on all the MCNC91 benchmark circuits reveal that 1) the gate replacement technique alone can achieve 10% leakage current reduction over the best known IVC methods with no delay penalty and little area increase; 2) the divide-and-conquer approach outperforms the best pure IVC method by 24% and the existing control point insertion method by 12%; and 3) compared with the leakage achieved by optimal MLV in small circuits, the gate replacement heuristic and the divide-and-conquer approach can reduce on average 13% and 17% leakage, respectively.     

A design methodology for low-leakage and high-performance buffer based on deviant behavior of gate leakage

Based on the observation that both subthreshold and gate leakage depend on transistors width, this paper introduces a feasible method to fast estimate leakage current in buffers. In simulating of leakage current with swept transistor width, we found that gate leakage is not always a linear function of the device geometry. Subsequently, this paper presented the theoretical analysis and ex- perimental evidence of this exceptional gate leakage behavior and developed a design methodology to devise a low-leakage and high-performance buffer with no penalty in area using this deviation.     

A Robust Power Gating Structure and Power Mode Transition Strategy for MTCMOS Design

The large magnitude of supply/ground bounces, which arise from power mode transitions in power gating structures, may cause spurious transitions in a circuit. This can result in wrong values being latched in the circuit registers. We propose a design methodology for limiting the maximum value of the supply/ground currents to a user-specified threshold level while minimizing the wake up (sleep to active mode transition) time. In addition to controlling the sudden discharge of the accumulated charge in the intermediate nodes of the circuit through the sleep transistors during the wake up transition, we can eliminate short circuit current and spurious switching activity during this time. This is, in turn, achieved by reducing the amount of charge that must be removed from the intermediate nodes of the circuit and by turning on different parts of the circuit in a way that causes a uniform distribution of current over the wake up time. Simulation results show that, compared to existing wakeup scheduling methods, the proposed techniques result in a 1-2 orders of magnitude improvement in the product of the maximum ground current and the wake up time     

Gate leakage reduction for scaled devices using transistor stacking

In this paper, the effect of gate tunneling current in ultra-thin gate oxide MOS devices of effective length (L/sub eff/) of 25nm (oxide thickness=1.1 nm), 50 nm (oxide thickness=1.5 nm) and 90 nm (oxide thickness=2.5 nm) is studied using device simulation. Overall leakage in a stack of transistors is modeled and the opportunities for leakage reduction in the standby mode of operation are explored for scaled technologies. It is shown that, as the contribution of gate leakage relative to the total leakage increases with technology scaling, traditional techniques become ineffective in reducing overall leakage current in a circuit. A novel technique of input vector selection based on the relative contributions of gate and subthreshold leakage to the overall leakage is proposed for reducing total leakage in a circuit. This technique results in 44% savings in total leakage in 50-nm devices compared to the conventional stacking technique.     

INDEP approach for leakage reduction in nanoscale CMOS circuits

Complementary metal oxide semiconductor (CMOS) technology scaling for improving speed and functionality turns leakage power one of the major concerns for nanoscale circuits design. The minimization of leakage power is a rising challenge for the design of the existing and future nanoscale CMOS circuits. This paper presents a novel, input-dependent, transistor-level, low leakage and reliable INput DEPendent (INDEP) approach for nanoscale CMOS circuits. INDEP approach is based on Boolean logic calculations for the input signals of the extra inserted transistors within the logic circuit. The gate terminals of extra inserted transistors depend on the primary input combinations of the logic circuits. The appropriate selection of input gate voltages of INDEP transistors are reducing the leakage current efficiently along with rail to rail output voltage swing. The important characteristic of INDEP approach is that it works well in both active as well as standby modes of the circuits. This approach overcomes the limitations created by the prevalent current leakage reduction techniques. The simulation results indicate that INDEP approach mitigates 41.6% and 35% leakage power for 1-bit full adder and ISCAS-85 c17 benchmark circuit, respectively, at 32 nm bulk CMOS technology node.     

FELERION: a new approach for leakage power reduction

The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%–94% as compared to the conventional approach.     

基于NB-IoT的分布式光伏电站漏电监测系统

针对分布式光伏电站缺少漏电流无线监测设备的实际情况,介绍一种基于NB-IoT(窄带物联网)无线高精度磁调制电流传感器的漏电监测系统。该系统由感知层、传输层、平台层和应用层四部分构成。通过对影响磁调制传感器精度的定性和定量研究,提出双磁芯半波激励方案,优化传感器设计,提高其精度。汇流箱中的电流传感器采集数据信息通过单片机经由NB-IoT网络传输至云平台。该系统能够实现使用云平台对分布式光伏电站系统漏电流进行在线实时监测和故障定位,且能有效解决分布式光伏电站的漏电监测问题。     

Microarchitecture-level leakage reduction with data retention

In this paper, we study microarchitecture-level leakage energy reduction by power gating. We consider the virtual power/ground rails clamp (VRC) and multithreshold CMOS (MTCMOS) techniques and apply VRC to memory-based units for data retention and MTCMOS to the other units. We propose a systematic methodology for leakage reduction at the microarchitecture level, in which profiling of idle period distribution and ideal power gating analysis are used to select a target component for realistic power gating. We show that the ideal leakage energy reduction can be up to 30% of the total energy for the modern high-performance very long instruction word processors we study and that the secondary level (L2) cache contributes most to the reduction. We further improve the existing adaptive cache decay method for leakage reduction by using VRC for data retention and name it VRC decay . Applied to L2 cache, the VRC decay, on average, increases performance by 5.6% and reduces system energy by 24.1%, compared to the adaptive cache decay without data retention.     

A mechanism and a reduction technique for large reverse leakage current in p-n junctions

The origin of anomalously large p-n junction leakage current in Si is investigated. The leakage has strong electric field dependence and weak temperature dependence, and therefore cannot be explained by either generation-recombination current or diffusion current. It may be explained by the local Zener effect at local enhancement of the electric field around small precipitates in the depletion layer. Supposing a spherical precipitate, the electric field will be enhanced as much as 1.3 times for a SiO/sub 2/ precipitate and 3 times for a metal precipitate. The leakage features are explained by the electric field dependence and the temperature dependence of the local Zener probability. A new approach to reduce the local Zener probability by controlling the profile of the electric field is proposed, and the validity of the approach is confirmed by direct experiment and by improvement in the refresh operation of DRAM cells.<>