宽带数字信道化接收机的FPGA实现

为解决现代电子战对接收机处理带宽宽、灵敏度高及实时性处理的要求,提出一种数字信道化接收机的设计方法。在推导高效信道化接收机模型的基础上,采用多相滤波器结构实现的数字信道化接收机。该接收机利用超高速A/D对数据进行高速采样,然后由高性能FPGA进行数据抽取、多相滤波、CORDIC算法等信道化实时处理。为了提高实时性,采用并行IFFT实现。该信道化接收机不仅能稳定输出载频及相位信息,还能处理三路同时到达的不同信号。实际的性能测试结果表明该接收机的功能正确并达到预定指标。     

双/多基地综合脉冲孔径地波雷达的信道化接收技术研究

双/多基地综合脉冲孔径地波雷达在发射站为多载频信号同时辐射,在接收站综合形成发射方向图之前需要对各发射信号分量进行分离.尽管采用数字混频和低通滤波器组可以对各发射分量进行分离,但运算量太大,难以实时实现.为此提出采用多相滤波器组信道化接收技术,设计该雷达的多相滤波器组信道化接收机.这种多相滤波器组信道化接收机与低通滤波器组信道化接收相比,运算量减少N²倍(N为信道数).最后给出了该雷达试验系统的实测数据处理结果,验证了这种多相滤波器组信道化接收技术在该雷达信号处理中的有效性.     

Design and research of equally divided channel filter banks

信道化作为软件无线电系统和宽带数字接收机的关键技术之一,而多相滤波结构的信道化处理技术和滤波器组的设计一直是研究难点。根据多相滤波结构,本文给出一种有限冲激响应滤波器的设计方法,然后根据均匀信道化的要求设计出均匀滤波器组,设计出的原型滤波器能够无失真采样滤波并能重构。利用等波纹设计的同时,使优化所得通带波纹数量级达到10^3,衰减达到-100dB。利用MATLAB设计及仿真表明,该设计是可靠的,可作为高速率滤波器设计的方法。     

基于均匀信道化滤波器组的研究与设计

信道化作为软件无线电系统和宽带数字接收机的关键技术之一,而多相滤波结构的信道化处理技术和滤波器组的设计一直是研究难点。根据多相滤波结构,本文给出一种有限冲激响应滤波器的设计方法,然后根据均匀信道化的要求设计出均匀滤波器组,设计出的原型滤波器能够无失真采样滤波并能重构。利用等波纹设计的同时,使优化所得通带波纹数量级达到10-3,衰减达到-100dB。利用MATLAB设计及仿真表明,该设计是可靠的,可作为高速率滤波器设计的方法。     

信道化接收处理方法研究

现代雷达接收机要求具有瞬时频带宽,良好的灵敏度和动态范围,检测同时到达信号的能力等特点。针对这些问题,采用多相滤波组信道化接收的处理方法,将两个线性调频脉冲信号通过多相滤波组信道化接收机,经信道划分、采样、移频等处理后,实现对多路信号的信道分离,并成功检测到同时到达的信号,降低了信号处理的复杂度,提高了接收机实时处理能力,尤其是提高了雷达接收机全概率截获目标的能力。     

基于多相滤波器的高分辨率信道化接收机设计

针对无盲区的多相数字信道化接收机,综合考虑了原型滤波器的瞬态响应时间和系统后续处理速度,推导出选择滤波器过渡带宽的数学公式,为信道化接收机的滤波器合理设计提供了评判标准。针对信道化接收机的频率分辨率受信道带宽限制的缺点,在系统后续处理中提出了重叠的离散傅里叶变换算法,减小计算量的同时提高了系统的实时性。能够灵活设置单组DFT运算点数,提高了接收机频率测量的精度。最后,通过仿真分析验证了该高效设计的可行性。     

全概率截获信道化接收机的设计

文章重点研究了基于多相滤波技术实现全概率截获的信道化接收机,推导了实信号的多相滤波器组信道化接收机数学模型,并基于模型利用MATLAB针对四路信号进行了仿真分析,仿真结果证明了接收机模型的正确性和可操作性,为通信系统具体应用该接收机提供了重要的理论依据.     

一种基于MMF-FRM的低复杂度信道化接收机结构

为实现时域重叠信号的全概率接收和跨信道信号重构，降低窄过渡带信道化结构的复杂度，提出一种基于调制屏蔽滤波器频率响应屏蔽（Modulation Masking Filter Frequency Response Masking, MMF-FRM）技术的信道化接收机结构.通过对原型屏蔽滤波器进行调制得到两个分支屏蔽滤波器，给出了基于MMF-FRM的窄过渡带滤波器设计方法 .推导出一种基于MMF-FRM的低复杂度信道化接收机结构，该信道化结构解决了多相分解受FRM(Frequency Response Masking)滤波器组限制的问题，并分析了该结构的有限字长性质和纹波系数.用Xilinx System Generator进行了硬件实现与仿真，在采样速率为1 GHz，信道数为8的条件下，提出的信道化接收机结构比多相信道化结构节省74.1%的乘法器资源，比FRM信道化结构节省13.5%的乘法器资源.     

一种大带宽高分辨力数字信道化接收机

阐述了两种基于多相滤波器结构的数字信道化模型，就电子对抗领域中雷达侦察接收机的实际应用，提出了一种大带宽数字信道化接收机的方案，该方案采用文中阐述的两种信道化模型级联的方式，具有瞬时带宽大，频率分辨力高等特点，能够在单片FPGA中实现。     

基于多相滤波器的信道化接收机及其应用研究

本文主要研究了应用多相滤波技术的信道化接收机建模问题。在给定信道频谱划分方案下,推导了基于多相 滤波器的信道化接收机数学模型。并由此模型设计了一个四信道模拟系统。最后用仿真实验结果验证了模型的正确性。     

Design of M‐Channel IIR Uniform DFT Filter Banks Using Recursive Digital Filters

In this paper, we propose a method for designing a class of M‐channel, causal, stable, perfect reconstruction, infinite impulse response (IIR), and parallel uniform discrete Fourier transform (DFT) filter banks. It is based on a previously proposed structure by Martinez et al. [1] for IIR digital filter design for sampling rate reduction. The proposed filter bank has a modular structure and is therefore very well suited for VLSI implementation. Moreover, the current structure is more efficient in terms of computational complexity than the most general IIR DFT filter bank, and this results in a reduced computational complexity by more than 50% in both the critically sampled and oversampled cases. In the polyphase oversampled DFT filter bank case, we get flexible stop‐band attenuation, which is also taken care of in the proposed algorithm.     

SVD-Based Techniques for Zero-Padded Block Transmission Over Fading Channels

In this paper, the performance of filter bank transceivers in the presence of a dispersive time-variant channel is investigated. It is well known that filter bank transceivers can be adapted to the channel transfer function to yield intersymbol interference (ISI) cancellation. When the channel is time variant, several problems arise, since the transceiver should be changed whenever the channel evolves. In this paper, we will allow both the transmitter and the receiver to change and satisfy the interference-free condition, under the assumption of a zero-padded block transmission. In this case, the optimum transmitter-receiver pair can be computed by using a singular value decomposition (SVD) of the channel matrix. A fast receiver adaptation based on SVD tracking is presented. Simulation results show that minimum performance loss with respect to the optimum receiver can be achieved for our reduced complexity receiver     

基于AD6652数字下变频模块的实现

提出了数字接收机基于AD6652的宽中频采样结构,使整个系统的灵活性、重构性、适应性得到很大的提升.AD6652采用矩阵输入,输入灵活,减少交叉连接产生的寄生信号,同时可以根据应用的不同在抽取滤波后进行多相合并,增加带宽.通过理论分析和仿真检验表明,该系统性能优良,结构简单,易于实现,具有实际应用价值.     

宽带数字下变频的一种高效实现结构

宽带数字接收系统要以大的调谐带宽截获窄带信号,要求数字下变频器具有高的数据率和快的调谐时间,现有的商用数字下变频器不能满足这些要求。本文提出一种高效实现结构,综合利用DFT滤波器的灵活性和多相滤波的高效性,按照先抽取数据,再低通滤波、混频的顺序,较好地解决了硬件速度和高速数据流不匹配的问题。计算机模拟结果证明了处理结构的有效性。     

A subband adaptive filter allowing maximally decimation

Conventional subband adaptive filters (ADF) using filter banks have shown degradation in performance because of the nonideal nature of filter banks. For this problem, the authors propose an alias free subband structure for adaptive filtering using polyphase frequency sampling filter (FSF) banks. As a preliminary, they make it clear that the conventional polyphase discrete Fourier transform (DFT) bank is equivalent to a class of the FSF bank. Then, they propose a new class of ADF using the FSF banks based on the frequency sampling theorem. As a result, the proposed technique enables subband adaptive filtering without the degradation effect of both the aliasing and cross terms, even if one chooses critical subsampling     

Filter Bank Channelizers for Multi-Standard Software Defined Radio Receivers

The ability to support multiple channels of different communication standards, in the available bandwidth, is of importance in modern software defined radio (SDR) receivers. An SDR receiver typically employs a channelizer to extract multiple narrowband channels from the received wideband signal using digital filter banks. Since the filter bank channelizer is placed immediately after the analog-to-digital converter (ADC), it must operate at the highest sampling rate in the digital front-end of the receiver. Therefore, computationally efficient low complexity architectures are required for the implementation of the channelizer. The compatibility of the filter bank with different communication standards requires dynamic reconfigurability. The design and realization of dynamically reconfigurable, low complexity filter banks for SDR receivers is a challenging task. This paper reviews some of the existing digital filter bank designs and investigates the potential of these filter banks for channelization in multi-standard SDR receivers. We also review two low complexity, reconfigurable filter bank architectures for SDR channelizers based respectively on the frequency response masking technique and a novel coefficient decimation technique, proposed by us recently. These filter bank architectures outperform existing ones in terms of both dynamic reconfigurability and complexity.     

Modulated filter banks with arbitrary system delay: efficientimplementations and the time-varying case

We present a new method for the design and implementation of modulated filter banks with perfect reconstruction. It is based on the decomposition of the analysis and synthesis polyphase matrices into a product of two different types of simple matrices, replacing the polyphase filtering part in a modulated filter bank. Special consideration is given to cosine-modulated as well as time-varying filter banks. The new structure provides several advantages. First of all, it allows an easy control of the input-output system delay, which can be chosen in single steps of input sampling rate, independent of the filter length. This property can be used in audio coding applications to reduce pre-echoes. Second, it results in a structure that is nearly twice as efficient as performing the polyphase filtering directly. Perfect reconstruction is a structurally inherent feature of the new formulation, even for nonlinear operations or time-varying coefficients. Hence, the structure is especially suited for the design of time-varying filter banks where both the number of bands as well as the prototype filters can be changed while maintaining perfect reconstruction and critical sampling. Further, a proof of effective completeness is given, and the design of equal magnitude-response analysis and synthesis filter banks is described. Filter design can be performed by nonconstrained optimization of the matrix coefficients according to a given cost function. Design and audio-coding application examples are given to show the performance of the new filter bank     

基于多相滤波的通用数字信道化技术

传统的信道化技术一旦信道带宽确定后,滤波计算时分解的相数和信道化后的时域分辨率也相应确定,耦合性较强,导致信道化技术在实际工程使用时灵活性存在一定的不足。文中首先给出了基于多相滤波的实信号数字信道化数学模型;然后,在此基础上推导了通用数字信道化数学表达式;最后,通过仿真验证了通用数字信道化技术的正确性。文中提出的通用数字信道化技术有效实现了信道带宽与多相滤波相数、信道化后时域分辨率的解耦,增加了系统设计和信道化技术应用的便捷性。