共查询到20条相似文献,搜索用时 31 毫秒
1.
The conflictual demand of faster and larger designs is increasingly difficult to answer by the advances of solid state technology alone. At some point, it is expected that designers and manufacturers will have to give up the traditional synchronous design methodology for a Globally Asynchronous Locally Synchronous (GALS) one. Such changes imply more synchronization constraints, but also more flexibility. Consequently, this paper proposes a novel Field-Programmable Gate Arrays (FPGA) architecture that is compatible with existing devices and that can also support GALS designs. The main objective is simple: the proposed architecture must appear unchanged for synchronous design, but it must also include a minimal amount of basic components to prevent metastability for efficient asynchronous communications. Thus, the paper presents the constraint equations required to implement such a circuit. It also presents a pausible clock generator application and simulation results for the proposed architecture. All results demonstrate that with a few additional customized circuits, a standard FPGA cell can become appropriate for GALS methodologies. 相似文献
2.
文章基于GALS(Globally Asynchronous Locally Synchronous)设计理念,提出一个Core的异步接口设计模型:门控时钟停Core机制、握手机制、电平转脉冲逻辑等构成的异步控制信号处理模型:异步FIFO和双FIFO结构构成的异步数据处理模型。此结构允许Core和总线系统在完全异步的时钟域上工作。FPGA验证结果表明.该模型能正确地实现两者问的信号同步,并能满足具体应用的带宽需求。 相似文献
3.
《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2009,17(3):427-438
4.
A voltage scaling technique for energy-efficient operation requires an adaptive power-supply regulator to significantly reduce dynamic power consumption in synchronous digital circuits. A digitally controlled power converter that dynamically tracks circuit performance with a ring oscillator and regulates the supply voltage to the minimum required to operate at a desired frequency is presented. This paper investigates the issues involved in designing a fully digital power converter and describes a design fabricated in a MOSIS 0.8-μm process. A variable-frequency digital controller design takes advantage of the power savings available through adaptive supply-voltage scaling and demonstrates converter efficiency greater than 90% over a dynamic range of regulated voltage levels 相似文献
5.
Chabini N. Wolf W. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2004,12(6):573-589
The problem of minimizing dynamic power consumption by scaling down the supply voltage of computational elements off critical paths is widely addressed in the literature for the case of combinational designs. The problem is NP-hard in general. To address the problem in the case of synchronous sequential digital designs, one needs to move some registers while applying voltage scaling. Moving these registers shifts some computational elements from critical paths, and can be done by basic retiming. Integrating basic retiming and supply voltage scaling to address this NP-hard problem cannot in general be done in polynomial run time. In this paper, we propose to first apply a guided retiming and then to apply supply voltage scaling on the retimed design. We devise new polynomial time algorithms to realize this guided retiming, and the supply voltage scaling on the retimed design. Also, we show that the problem in the case of combinational designs is not NP-hard for some combinational circuits with certain structure, and give a polynomial time algorithm to optimally solve it. Methods to determine lower bounds on the optimal reduction of dynamic power consumption are also provided. Experimental results on known benchmarks have shown that the proposed approach can reduce dynamic power consumption by factors as high as 61% for single-phase designs with minimal clock period. Also, they have shown that it can solve optimally the problem, and produce converter-free designs with reduced dynamic power consumption. For large size circuits from ISCAS'89 benchmark suite, the proposed algorithms run in 15 s-1 h. 相似文献
6.
7.
A proposed synthesizable pseudo fractional-N clock generator with improved duty cycle output is presented by the pseudo fractional-N frequency synthesizer unit for SoC chips and the dynamic frequency scaling applications. The different clock frequencies can be generated by following the design flowchart. It has been fabricated in a 0.13 μm CMOS technology and work with a supply voltage of 1.2 V. According to measured results, the frequency range of the proposed synthesizable pseudo fractional-N clock generator is from 12.5 MHz to 1 GHz and the peak-to-peak jitter is less than 5% of the output period. Duty cycle error rate of the output clock frequency is 1.5% and the measured power dissipation of the pseudo fractional-N frequency synthesizer unit is 146 μW at 304 MHz. 相似文献
8.
Talpes E. Marculescu D. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2005,13(5):591-603
Enabled by the continuous advancement in fabrication technology, present-day synchronous microprocessors include more than 100 million transistors and have clock speeds well in excess of the 1-GHz mark. Distributing a low-skew clock signal in this frequency range to all areas of a large chip is a task of growing complexity. As a solution to this problem, designers have recently suggested the use of frequency islands that are locally clocked and externally communicate with each other using mixed clock communication schemes. Such a design style fits nicely with the recently proposed concept of voltage islands that, in addition, can potentially enable fine-grain dynamic power management by simultaneous voltage and frequency scaling. This paper proposes a design exploration framework for application-adaptive multiple-clock processors which provides the means for analyzing and identifying the right interdomain communication scheme and the proper granularity for the choice of voltage/frequency islands in case of superscalar, out-of-order processors. In addition, the presented design exploration framework allows for comparative analysis of newly proposed or already published application-driven dynamic power management strategies. Such a design exploration framework and accompanying results can help designers and computer architects in choosing the right design strategy for achieving better power-performance tradeoffs in multiple-clock high-end processors. 相似文献
9.
《Circuits and Systems II: Express Briefs, IEEE Transactions on》2009,56(1):21-25
10.
Frappe A. Flament A. Stefanelli B. Kaiser A. Cathelin A. 《Solid-State Circuits, IEEE Journal of》2009,44(10):2722-2732
An all-digital RF signal generator using DeltaSigma modulation and targeted at transmitters for mobile communication terminals has been implemented in 90 nm CMOS. Techniques such as redundant logic and non-exact quantization allow operation at up to 4 GHz sample rate, providing a 50 MHz bandwidth at a 1 GHz center frequency. The peak output power into a 100 Omega diff. load is 3.1 dBm with 53.6 dB SNDR. By adjusting the sample rate, carriers from 50 MHz to 1 GHz can be synthesized. RF signals up to 3 GHz can be synthesized when using the first image band. As an example, UMTS standard can be addressed by using a 2.6 GHz clock frequency. The measured ACPR is then 44 dB for a 5 MHz WCDMA channel at 1.95 GHz with output power of -16 dBm and 3.4% EVM. At 4 GHz clock frequency the total power consumption is 120 mW (49 mW for DeltaSigma modulator core) on a 1 V supply voltage, total die area is 3.2 mm2 (0.15 mm2 for the active area). 相似文献
11.
Ching-Che Chung Chen-Yi Lee 《Solid-State Circuits, IEEE Journal of》2004,39(3):469-475
A new DLL-based approach for all-digital multiphase clock generation is presented. By using the time-to-digital converter (TDC) with fixed-step search scheme, the proposed all-digital and cell-based solution can overcome the false-lock problem in conventional designs. Furthermore, the proposed all-digital multiphase clock generator (ADMCG) can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity in many different applications. The test chip shows that our proposal demonstrates a wide frequency range to meet the needs of many digital communication applications. 相似文献
12.
Goran Jovanović Mile Stojčev Tatjana Nikolić 《International Journal of Electronics》2013,100(6):779-792
The clock is one of the most critical signals in any synchronous system. As CMOS technology has scaled, supply voltages have dropped chip power consumption has increased and the effects of jitter due to clock frequency increase have become critical and jitter budget has become tighter. This article describes design and development of low-cost mixed-signal programmable jitter generator with high resolution. The digital technique is used for coarse-grain and an analogue technique for fine-grain clock phase shifting. Its structure allows injection of various random and deterministic jitter components in a controllable and programmable fashion. Each jitter component can be switched on or off. The jitter generator can be used in jitter tolerance test and jitter transfer function measurement of high-speed synchronous digital circuits. At operating system clock frequency of 220?MHz, a jitter with 4?ps resolution can be injected. 相似文献
13.
Nowka K.J. Carpenter G.D. MacDonald E.W. Ngo H.C. Brock B.C. Ishii K.I. Nguyen T.Y. Burns J.L. 《Solid-State Circuits, IEEE Journal of》2002,37(11):1441-1447
A PowerPC system-on-a-chip processor which makes use of dynamic voltage scaling and on-the-fly frequency scaling to adapt to the dynamically changing performance demands and power consumption constraints of high-content, battery powered applications is described. The PowerPC core and caches achieve frequencies as high as 380 MHz at a supply of 1.8 V and active power consumption as low as 53 mW at a supply of 1.0 V. The system executes up to 500 MIPS and can achieve standby power as low as 54 /spl mu/W. Logic supply changes as fast as 10 mV//spl mu/s are supported. A low-voltage PLL supplied by an on-chip regulator, which isolates the clock generator from the variable logic supply, allows the SOC to operate continuously while the logic supply voltage is modified. Hardware accelerators for speech recognition, instruction-stream decompression and cryptography are included in the SOC. The SOC occupies 36 mm/sup 2/ in a 0.18 /spl mu/m, 1.8 V nominal supply, bulk CMOS process. 相似文献
14.
本文首先概述了TD-SCDMA终端的耗电特性,接着对动态电压与频率调节技术进行了分析,最后运用动态管理技术提出了一种基于动态电压与频率调节技术的终端省电方案,有效地延长了终端的工作时间. 相似文献
15.
Eun-Gu Jung Jeong-Gun Lee Kyoung-Son Jhang Jeong-A Lee Dongsoo Har 《Journal of Signal Processing Systems》2007,46(2-3):133-151
In this paper, a novel asynchronous layered interface for a high performance on-chip bus is designed in a Globally Asynchronous Locally Synchronous (GALS) style. The proposed asynchronous layered interface with distributed and modularized control units supports multiple outstanding in-order/out-of-order transactions to achieve high performance. In the layered architecture, extension of an asynchronous layered interface performing complex functions is readily achieved without repeating the implementation of the whole bus interface. Simulations are carried out to measure the performance and power consumption of implemented asynchronous on-chip bus with the proposed asynchronous layered interface. Simulation results demonstrate that throughput of the asynchronous on-chip bus with multiple outstanding out-of-order transactions is increased by 30.9%, while power consumption overhead is 16.1% and area overhead is 56.8%, as compared to the asynchronous on-chip bus with a single outstanding transaction. 相似文献
16.
《Solid-State Circuits, IEEE Journal of》2009,44(4):1167-1177
17.
Dong-Young Chang Un-Ku Moon 《Solid-State Circuits, IEEE Journal of》2003,38(8):1401-1404
A low-voltage opamp-reset switching technique (ORST) that does not use clock boosting, bootstrapping, switched-opamp (SO), or threshold voltage scaling is presented. This technique greatly reduces device reliability issues. Unlike the SO technique, the opamps stay active for all clock phases and, therefore, the ORST is suitable for high-speed applications. This new switching technique is applied to the design of a 10-bit 25-MS/s pipelined analog-to-digital converter (ADC). The prototype ADC was fabricated in a 0.35-/spl mu/m CMOS process and demonstrates 55-dB signal-to-noise ratio, 55-dB spurious-free dynamic range, and 48-dB signal-to-noise-plus-distortion ratio performance with a 1.4-V power supply. The total power consumption is 21 mW. The ADC's minimum operating power supply is 1.3 V (|V/sub TH,P/| = 0.9 V) and the maximum operating frequency is 32 MS/s. The ORST is fully compatible with future low-voltage submicron CMOS processes. 相似文献
18.
《Solid-State Circuits, IEEE Journal of》2006,41(9):2077-2082
A delay-locked loop (DLL)-based clock generator for dynamic frequency scaling has been developed in a 0.35-$muhbox m$ CMOS technology. The proposed clock generator can generate clock signals ranging from 120 MHz to 1.8 GHz and change the frequency dynamically in a short time. If the clock generator scales its output frequency dynamically by programming with the same last bit, it takes only one clock cycle to lock. In addition, the clock generator inherits advantages of a DLL. The proposed DLL-based clock generator occupies 0.07$hbox mm^2$ and has a peak-to-peak jitter of$pm $ 6.6 ps at 1.3 GHz. 相似文献
19.
Yo-Hao Tu Jen-Chieh Liu Kuo-Hsing Cheng Chih-Hsun Hsu 《Analog Integrated Circuits and Signal Processing》2017,93(1):157-167
This paper proposes a low supply voltage all-digital clock-deskew buffer with in-phase and quadrature phase (I/Q) outputs on an intra-chip. In some application-specific integrated chips or silicon intellectual properties might enter hibernation mode to conserve energy. The long locking time induces a large standby current, which results in greater power consumption. Furthermore, I/Q clock signals are widely adopted in the communication systems and double data rate memories. The proposed all-digital clock-deskew buffer can operate from 220 to 570 MHz at 0.5 V and the power consumption is 1.95 mW at 570 MHz. This buffer can also supply a quadrature phase output using a proposed two-step edge detector. 相似文献
20.
描述一个基于TSMC 0.18μm数字工艺的12 bit 100 Ms/s流水线模数转换器的设计实例。该模数转换器采用1.5bit每级结构,电源电压为1.8V。包括十级1.5 bit/stage和最后一级2bit Flash模数转换器,共产生22bit数字码,数字码经过数字校正电路产生12 bit的输出。该模数转换器省去了采样保持电路,电路模块包括:各个子流水级、共模电压生成模块、带隙基准电压生成模块、开关电容动态偏置模块、系统时钟生成模块、时间延迟对齐模块和数字校正电路模块。为了实现低功耗设计,在电路设计中综合采用了输入采样保持放大器消去、按比例缩小和动态偏置电路等技术。ADC实测结果,当以100 MHz的采样率对10MHz的正弦输入信号进行采样转换时,在其输出得到了73.23dB的SFDR,62.75dB的SNR,整体功耗仅为113mW。 相似文献