Analysis and measurement of timing jitter induced by radiated EMI noise in automatic test equipment

This paper deals with the generation, measurement and modeling of the jitter encountered in the signals of a testhead board for automatic test equipment (ATE). A novel model is proposed for the jitter; this model takes into account the radiated electromagnetic interference (EMI) noise in the head of an ATE. The RMS value of the jitter is measured at the output signal of the testhead board to validate the proposed model. For measuring the RMS value, a novel circuitry has been designed on a daughter board to circumvent ground noise and connectivity problems arising from the head environment. An H-field is applied externally at the loop filter of a phase-locked loop (PLL), thus permitting the measurement of the RMS jitter to verify the transfer function between radiated EMI and jitter variation. The error between measured and predicted jitters is within a 15% level at both 200 kHz and 500 kHz.     

PLL jitter reduction by utilizing a ferroelectric capacitor as a VCO timing element

Ferroelectric capacitors have steadily been integrated into semiconductor processes due to their potential as storage elements within memory devices. Polarization reversal within ferroelectric capacitors creates a high nonlinear dielectric constant along with a hysteresis profile. Due to these attributes, a phase-locked loop (PLL), when based on a ferroelectric capacitor, has the advantage of reduced cycle-to-cycle jitter. PLLs based on ferroelectric capacitors represent a new research area for reduction of oscillator jitter.     

Ultrasound array transmitter architecture with high timing resolution using embedded phase-locked loops

Coarse time quantization of delay profiles within ultrasound array systems can produce undesirable side lobes in the radiated beam profile. The severity of these side lobes is dependent upon the magnitude of phase quantization error--the deviation from ideal delay profiles to the achievable quantized case. This paper describes a method to improve interchannel delay accuracy without increasing system clock frequency by utilizing embedded phase-locked loop (PLL) components within commercial field-programmable gate arrays (FPGAs). Precise delays are achieved by shifting the relative phases of embedded PLL output clocks in 208-ps steps. The described architecture can achieve the necessary interelement timing resolution required for driving ultrasound arrays up to 50 MHz. The applicability of the proposed method at higher frequencies is demonstrated by extrapolating experimental results obtained using a 5-MHz array transducer. Results indicate an increase in transmit dynamic range (TDR) when using accurate delay profiles generated by the embedded-PLL method described, as opposed to using delay profiles quantized to the system clock.     

Crosstalk bounded uncorrelated jitter (BUJ) for high-speed interconnects

Bounded uncorrelated jitter (BUJ), a subcomponent of total jitter, is commonly caused by crosstalk coupling from adjacent interconnects on printed circuit boards (PCB). However, the characteristics of BUJ are still not well understood. Neither a mathematical model of jitter, nor an algorithm to generate histograms for BUJ has been developed to this date. Such a model and algorithm would empower designers to predict BUJ to achieve total jitter budget without lengthy simulations and measurements. In this paper, we first review the characteristics of a crosstalk pulse induced by an aggressor signal on a quiet trace. Then, by applying the superposition principle, a jitter model to calculate the time difference between the distortion-free and the distorted edge crossings of the victim signal was developed. This model is also extended to calculate the worst case timing difference, BUJ/sub p-p/. In addition, an algorithm to generate the histogram distribution of BUJ is also developed. The developed algorithm has fast execution times of 10-20 s, compared to simulation and measurement times of 10-30 min.     

Special issue on BIT CMOS built-in test architecture for high-speed jitter measurement

Timing measurements for gigahertz clock frequencies require high accuracy and resolution. This paper proposes a scalable built-in self-test (BIST) method that measures accumulated period jitter over a programmable number of periods, without using another reference clock. This on-chip method uses a charge pump to convert time to a voltage, which is digitized by an all-digital flash analog-to-digital converter (ADC). The ADC employs multiple chains of inverter strings composed of three series inverters instead of the popular analog comparators. The inverter thresholds set the reference voltages for triggering given an input dc value. The output is calibrated and converted to jitter measurement. The design using a 0.25 /spl mu/m BiCMOS process, with an input range of 625 MHz-1 GHz, shows that a resolution of 70 ps root mean square (rms) jitter can be achieved, while occupying 0.0575 mm/sup 2/ area with a very conservative layout style. The design has been fabricated and tested, and the test results are presented.     

Generation and Measurement of Phase Jitter Using Phase-Lock Techniques

The phase-locked loop (PLL) is applied to generating and measuring large phase jitter that can be encountered in digital transmission systems. It is shown that jitter can be generated and measured by a PLL operated as a phase modulator and phase demodulator, respectively. Equations and examples are given for practical PLL designs to generate and measure jitter of a certain amplitude range and bandwidth. Practical considerations such as 1) phase detector range, 2) limited voltage-controlled oscillator sensitivity, 3) frequency tolerances, 4) pull-in time, and 5) calibration are included. PLL's designed in this way can be useful in evaluating digital transmission systems. Jitter measuring sets have been designed to measure jitter on the 1.5, 6.3, 45, and 274 Mbit/s signals used in the LD-4 digital cable system [1]. A jitter set for measuring jitter on 45 Mbit/s signals is described in this paper.     

Fabrication of precision fiber-optic time delays with in situ monitoring for subpicosecond accuracy

We have developed a technique to produce precise fiber-optic time delays with subpicosecond accuracy and <0.1-dB loss by heating and stretching optical fiber in a fusion splicer. A fiber Mach-Zehnder interferometer allows in situ measurement of these precise delays using a simple alignment process and requiring only a weak optical signal. To demonstrate this capability, we assembled a six-stage feed-forward delay line that can be used to generate 64 optical pulses with 9.5 +/- 0.8-ps pulse spacings and 4.8-dB total insertion loss.     

Uncertainty of signal reconstruction in the case of jittery andnoisy measurements

Time domain measurements are distorted by the measurement system if the bandwidth of the system is not sufficiently high compared to that of the signal to be measured. If the distortion is known the measured signal can be compensated for it (inverse filtering or deconvolution). Since the measurement is always corrupted by noise, the reconstruction is an estimation task, i.e., the reconstructed signal may vary depending on the actual noise record. Our aim is to investigate the errors related to the signal reconstruction, and to provide an error bound around the reconstructed time domain waveform. Based on their nature we can distinguish between systematic and stochastic errors. In this paper, we investigate the stochastic type of errors and suggest a method to calculate the uncertainty (variance) of the reconstruction. We developed a method for the calibration of high-speed sampling systems. Both stationary and jitter noises will be investigated     

Time-division multiplexing of large serial fiber-optic Bragg grating sensor arrays

Time-division multiplexing is a promising method for the interrogation of fiber-optic Bragg grating sensors arrays for measurement of strain and temperature. We examine the performance of these systems to determine the parameters for high-sensitivity, low-cross-talk operation. It is shown that the performance can be greatly improved by use of a short time resolution in the demultiplexing process. We propose a new method of demultiplexing with an electro-optic modulator to read out the sensor pulses by gating the signal with 400-ps resolution. The system is demonstrated experimentally to provide 0.15-muepsilon/ radicalHz strain resolution in a 50-Hz bandwidth within a full-scale range of 8000 muepsilon. The system parameters are capable of handling at least 50 time-addressed sensors on a single fiber.     

Novel on-chip circuit for jitter testing in high-speed PLLs

We propose a novel on-chip circuit to measure the jitter present at the output of phase-locked loops (PLLs) used for generating phase-synchronous, frequency-multiplied clocks. This measure is performed at every period of the PLL reference clock, and a digital output encoded by means of a thermometer code is obtained. Such a digital output is then analyzed in order to confirm on-chip whether or not the jitter is within specifications. Our proposed circuit is able to test PLLs providing an output frequency in the gigahertz range. Compared to alternate techniques, that proposed here requires lower costs in terms of area overhead (requiring an area <12% of the PLLs' area) and circuit complexity, while featuring higher or comparable accuracy and lower or comparable test time.     

BIST for Measuring Clock Jitter of Charge-Pump Phase-Locked Loops

This paper presents a built-in self-test (BIST) circuit that measures the clock jitter of the charge-pump phase-locked loops (PLLs). The jitter-measurement structure is based on a novel time-to-digital converter (TDC) which has a high resolution. A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows that the resolution is about 1 ps and that the measurement error is smaller than 20%.     

Uncertainty analysis of absolute concentration measurement with continuous-wave cavity ringdown spectroscopy

To evaluate the uncertainty of concentration measurement using cavity ringdown spectroscopy, we analytically derived expressions for uncertainty for parameters, such as temperature, laser frequency, and ringdown time deviation, from the model equation. The uncertainties that are due to systematic errors in a practical cavity ringdown system were assessed through an experimental study of the PQ(35) transition in an A band of molecular oxygen. We found that, except for the line strength that is regarded as a reference value independent of the measurement, the laser frequency jitter is the largest uncertainty source in the system. Some practical requirements for minimizing the uncertainty in concentration measurements are discussed. We also demonstrated determination of the line strength of the PQ(35) transition line of oxygen to be 8.63(3) x 10(-27) cm(-1) with a relative uncertainty of less than 0.4%.     

Review of low timing jitter mode-locked fiber lasers and applications in dual-comb absolute distance measurement

Passively mode-locked fiber lasers emit femtosecond pulse trains with excellent short-term stability. The quantum-limited timing jitter of a free running femtosecond erbium-doped fiber laser working at room temperature is considerably below one femtosecond at high Fourier frequency. The ultrashort pulse train with ultralow timing jitter enables absolute time-of-flight measurements based on a dual-comb implementation, which is typically composed of a pair of optical frequency combs generated by femtosecond lasers. Dead-zone-free absolute distance measurement with sub-micrometer precision and kHz update rate has been routinely achieved with a dual-comb configuration, which is promising for a number of precision manufacturing applications, from large step-structure measurements prevalent in microelectronic profilometry to three coordinate measurements in large-scale aerospace manufacturing and shipbuilding. In this paper, we first review the sub-femtosecond precision timing jitter characterization methods and approaches for ultralow timing jitter mode-locked fiber laser design. Then, we provide an overview of the state-of-the-art dual-comb absolute ranging technology in terms of working principles, experimental implementations, and measurement precisions. Finally, we discuss the impact of quantum-limited timing jitter on the dual-comb ranging precision at a high update rate. The route to highprecision dual-comb range finder design based on ultralow jitter femtosecond fiber lasers is proposed.     

2.45 GHz 0.8 mW voltage-controlled ring oscillator (VCRO) in 28 nm fully depleted silicon-on-insulator (FDSOI) technology

MOS bulk transistor is reaching its limits: sub-threshold slope (SS), drain induced barrier lowering (DIBL), threshold voltage (VT) and VDD scaling slowing down, more power dissipation, less speed gain, less accuracy, variability and reliability issues. Fully depleted devices are mandatory to continue the technology roadmap. FDSOI technology relies on a thin layer of silicon that is over a buried oxide (BOx). Called ultra thin body and buried oxide (UTBB) transistor, FDSOI transistors correspond to a simple evolution from conventional MOS bulk transistor. The capability to bias the back-gate allows us to implement calibration techniques without adding transistors in critical blocks. We have illustrated this technique on a very low power voltage-controlled oscillator (VCO) based on a ring oscillator (RO) designed in 28 nm FDSOI technology. Despite the fact that such VCO topology exhibits a larger phase noise, this design will address aggressively the size and power consumption reduction. Indeed we are using the efficient back-gate biasing offered by the FDSOI MOS transistor to compensate the mismatches between the different inverters of the ring oscillator to decrease jitter and phase noise. We will present the reasons which led us to use the FDSOI technology to reach the specifications of this PLL. The VCRO exhibits a 0.8 mW power consumption, with a phase noise about --94 dBc/Hz@1 MHz.     

Moment-matching method for extracting beam jitter and boresight in experiments with satellites of small physical cross section

The boresight and atmospheric jitter errors in a satellite tracking experiment are currently estimated by matching the probability density function (PDF) of the received signal counts with a set of PDFs of the signal for several combinations of jitter and boresight errors and then the best choice of jitter and boresight error is accepted via the chi-square test. Here a technique that can estimate atmospheric beam jitter and boresight error directly in a satellite active tracking experiment using the moments of the returns off the satellites is proposed. That is, we use the theoretical PDF for the signal return from a small target and compute the corresponding theoretical PDF moments. We can then form a few equations from these moments with only two unknowns, namely, the jitter and boresight. Solving for the unknowns is then unambiguous and very rapid. The method is valid for small physical cross-section targets and has been verified by using simulation and experimental data. Extending the case to asymmetric jitter and asymmetric boresight is possible.     

Joint design of optimum partial response target and equalizer for recording channels with jitter noise

We address joint design of optimum generalized partial response (GPR) target and equalizer for perpendicular recording channels with jitter noise. We develop a new cost function which accounts for the data-dependent nature of jitter noise based on the minimum mean square error (MMSE) criterion. Using the step-response-based channel model, we derive expressions for the statistics required to compute the optimum equalizer and target in the presence of jitter noise. We also derive a bit-response-based model for the jitter noise channel. We present an approach for doing simulations as well as analytical computations for the jitter noise channel without resorting to the widely used Taylor series approximations. Our computational and simulation results show that, while the targets designed without accounting for the jitter lead to error-floor effect in the bit-error-rate performance, the targets designed by our approach give significant performance improvement under high jitter conditions, with no sign of error-floor effect for the range of signal-to-noise ratios considered.     

Optimized design and process for making a DC voltage reference based on MEMS

A micromechanical moving plate capacitor has been designed and fabricated for use as a dc voltage reference. The reference is based on the characteristic pull-in property of a capacitive microelectromechanical system (MEMS) component. The design is optimized for stability. A new silicon-on-insulator (SOI) process has been developed to manufacture the component. We also report on improved feedback electronics and the latest measurement results.     

基于锁相环的解调技术研究

介绍了调相信号的锁相解调技术基本原理以及利用集成锁相环NE564实现对信号的锁相解调。为了解调出不失真的波形,利用集成锁相环NE564和LM725CN芯片设计PM调制解调系统,可以直接实现信号的调制解调功能,利用相位能稳定跟踪的特点避免了频率失锁的缺陷,提高了测量精度。该系统具有操作简单、稳定性强的优点,并在激光外差干涉信号的解调中具有较强的实用性。     

Micro-jitter attenuation of spaceborne cooler by using a blade-type hyperelastic shape memory alloy passive isolator

In this study, the primary design objective is to develop a passive isolator that can guarantee structural safety of the cooler assembly in a launch vibration environment without a launch locking mechanism, while effectively isolating the cooler-induced micro-jitter during the on-orbit operation of the cooler. To achieve the design objective, we focused on the utilization of characteristics of the hyperelastic shape memory effects. The major advantage of the isolator is that the micro-jitter isolation performance is much less sensitive to the aligned position of the isolator in comparison with the conventional isolator. Moreover, implementation of an additional 0g compensation device during a satellite level on-ground test, such as a jitter measurement test, is not required. In this study, the basic characteristics of the isolator were measured using the torque test and free vibration test. The micro-jitter attenuation capability and position sensitivity of the proposed isolator design were validated by the micro-jitter measurement test.     

可编程数字控制精密延时电路设计

设计一种基于斜波式发生器原理可编程数字控制精密延时电路,用恒流源电路充放电和18位的DA转换器分别接入高速比较器的两端,DA转换器预先设定一电压基准,恒流源充电电容达到电压基准,高速比较器开始反转,形成一个触发脉冲信号,然后充电电容通过高速二极管快速放电重新计时。设计成18bit数字控制可编程动态范围2ps的采集时间间隔,提高采集信号的精度和频率。