5MHz高稳定低相噪VCXO与锁相稳频技术

文中介绍了研制５ＭＨｚ高稳低相噪压控晶体振荡器（ＶＣＸＯ）以及利用锁相稳频技术获得长、短稳皆优的频标信号的一种行之有效的方法。     

Linearization of direct FM frequency modulators

Voltage controlled crystal oscillator (VCXO) frequency modulators have found increasing use in recent years in portable frequency modulation (FM) equipment as an alternative to a standard crystal oscillator followed by a phase modulator. The advantages of using a direct FM VCXO over an indirect FM phase modulator are considered. A model for the crystal and frequency control element will be developed and basic circuit design considerations will be presented. Conditions necessary to minimize audio distortion generated by the VCXO modulator will be dealt with in detail.     

Comparison of power deposition by in-phase 433 MHz andphase-modulated 915 MHz interstitial antenna array hyperthermia systems

The interstitial microwave antenna array hyperthermia (IMAAH) system produces a pattern of specific absorption rate (SAR) that is nonuniform within a 2-cm square array when driven in phase at 915 MHz. It was found that phase modulation makes the time-averaged SAR pattern significantly more uniform in planes perpendicular to the antennas. To drive antennas in phase at 433 MHz similarly improves SAR uniformity when the antennas are of resonance length     

A Novel DCXO Module for Clock Synchronization in MPEG2 Transport System

This paper presents a unique on-chip digital control crystal oscillator (DCXO) module that is used for clock synchronization in MPEG2 data transport system. This module is built inside a phase-locked loop (PLL) and is achieved through flying-adder frequency synthesis architecture. It is designed at 27 MHz with a tuning range of ${pm}10$ kHz. The linearity at the range of 27 MHz ${pm}10$ kHz is measured as 0.001%. The frequency resolution is 1.6 Hz. This DCXO and its associated PLL consume 10 mW and occupies 0.15 mm$^{2}$ in a 90-nm CMOS process. The contribution of this work is that this built-in DCXO can completely eliminate the need of external voltage-control crystal oscillator (VCXO) chip or on-chip VCXO block in MPEG2 clock synchronization and thus significantly reduces the system cost. This module has been used in a real HDTV SoC chip.      

人体通信信道相位特性研究

采用实验统计方法研究人体信道在1~200 MHz频段下的传播延时和相位特性。实验采用13名志愿者分别进行4个传播路径的群延时测量,并将测试频段划分为1~100 MHz和100~200 MHz两个子频段进行研究,探讨4个传播路径和两个子频段下的延时特性。统计分析表明:信号在人体通信信道的传播延时和传播路径无关;100~200 MHz频段内的传播延时均比1~100 MHz内的传播延时大。1~200 MHz频段内相位归一化曲线表明:在20~40 MHz频段信号畸变较大。根据最大似然估计算法(Maximum Likelihood Estimation,MLE)和Akaike信息量准则(Akaike Information Criterion,AIC),信号相位归一化偏差值符合Lognormal分布。     

622MHz current-mode sense amplifier

A current-mode sense amplifier, operating at 622 MHz, in a 0.8 μm CMOS process is proposed. The basic ideas are to modify the reset mechanism and precharge timing of the earlier CBLSA design to allow robust sensing with single phase clocking, as well as TSPC compatible output timing     

900 MHz压控振荡器设计

采用集总元件变容二极管和超高频三极管设计900 MHz压控振荡器,根据ADS2006A软件仿真确定了压控振荡器的电路参数,并对相关指标如相位噪声、调谐带宽、稳定系数、输出功率和谐波电平等进行了仿真,通过调整电路参数,优化电路结构,实现了工作频率为1 GHz、调谐带宽为90 MHz的压控振荡器,其相位噪声在偏移中心频率10 kHz处为-105 dBc/Hz,在100 kHz处为-120 dBc/Hz,该设计大大降低了系统成本.     

In situ measurements of the complex propagation constant in rocks for frequencies from 1 MHz to 10 MHz

The complex propagation constant for frequencies between 1 MHz and 10 MHz has been measured for propagation between bore holes in granite rock at a site near Raymond, Colo., USA. The measurement technique consisted in Comparisons of the phase and amplitude of signals received on two identical dipole antennas spaced at different distances on a radial from an isolated transmitter. The conductivity and permittivity of the medium calculated from the propagation constant are compared with laboratory measurements of samples from the same boreholes, and reasonably good agreement is obtained.     

A 250-622 MHz deskew and jitter-suppressed clock buffer usingtwo-loop architecture

A 250-622 MHz clock buffer has been developed, using a two-loop architecture: a delay-locked loop (DLL) for deskew, and a frequency-locked loop (FLL) for reference frequency supply to the DLL. The DLL incorporates a current-mode phase detector which utilizes a flip-flop metastability to detect a phase difference in the order of 20 ps. A measured jitter is suppressed to less than 40 ps RMS over the operating frequency range. A DLL acquisition time of 150 ns typical is simulated at 400 MHz. A 0.4-μm CMOS technology is used to fabricate the chip     

A 900 MHz low power LC-VCO with improved phase noise performance

In this paper, we present the design and development of a low-power LC-VCO with improved phase noise performance by implementing a new capacitor divider varactor configuration and a 2nd order notch filter. We propose a new time-weighted approach to model the effective capacitance experienced by the oscillating signal over the oscillation period. The modeled effective capacitance is used in the calculation of the oscillation frequency, which agrees well with the simulation results. Two VCOs are designed and fabricated in TSMC 0.18 μm technology. The oscillation frequency is tunable from 759 to 910 MHz with a tuning range of 18%. At 900 MHz carrier, the measured phase noise is ?126.1 dBc/Hz at 1 MHz frequency offset with 4.5 mW power consumption.     

Phase Shifter for a 915 MHz Phased Array Hyperthermia System

This paper describes a design for an analog phase shifter operating at 915 MHz and suitable for use in a phased array microwave hyperthermia system. Here, the major operating constraint was minimization of amplitude variation over a 1800 phase shift, whereas previous phase shifters were designed to obtain a linear relationship between phase and control voltage. The result is a simple, inexpensive hybrid coupler phase shifter that operates over a narrow bandwidth and provides 180°of continuous phase shift with input powers up to 1 W.     

905MHz低相噪声表面波振荡器的设计

本文分析了声表面波谐振器的性能 ,论述了声表面波振荡器的工作原理及设计方法 ,最终完成中心频率为 90 5MHz的振荡电路 ,相位噪声低于 - 110dBc/Hz/ 1kHz。文中对影响相位噪声的因素进行了分析讨论     

用于434/868MHz FSK/OOK CMOS发射机的锁相环设计

一种可输出434/868MHz信号的Σ-Δ分数分频锁相环在0.35μmCMOS工艺中集成。该发射机系统采用直接调制锁相环分频比的方式实现FSK调制,OOK的调制则通过功率预放大器的开-关实现。为了降低芯片的成本和功耗,发射机采用了电流数字可控的压控振荡器(VCO),以及片上双端-单端转换电路,并对分频器的功耗设计进行研究。经测试表明,锁相环在868MHz载波频偏为10kHz、100kHz和3MHz处的相位噪声分别为-75dBc/Hz、-104dBc/Hz和-131dBc/Hz,其中的VCO在100kHz频偏处的相位噪声为-108dBc/Hz。在发送模式时,100kHz相邻信道上的功率与载波功率之比小于-50dB。在直流电压2.5V的工作条件下,锁相环的电流为12.5mA,包括功率预放大器和锁相环在内的发送机总面积为2mm2。     

A 200 MHz quadrature digital synthesizer/mixer in 0.8 μm CMOS

A 200 MHz quadrature direct digital frequency synthesizer/complex mixer (QDDFSM) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc. The frequency resolution is 0.047 Hz with a corresponding switching speed of 5 ns and a tuning latency of 14 clock cycles. The chip is also capable of frequency, phase, and quadrature amplitude modulation. These modulation capabilities operate up to the maximum clocking frequency. The chip provides the capability of parallel operation of multiple chips with throughputs up to 800 MHz. The 0.8 μm triple level metal N-well CMOS chip has a complexity of 52000 transistors with a core area of 2.6×6.1 mm². Power dissipation is 2 W at 200 MHz and 5 V     

200MHz高频晶体振荡器研制

研制了一种200 MHz高频晶体振荡器,概述了产品的组成及工作原理,给出了该高频晶体振荡器的详细设计方法.仿真与实测结果表明,该晶体振荡器不仅具有优良的相位噪声,同时也达到了预期的抗振设计要求.     

基于MAX7033的315MHz/433 MHz ASK超外差式接收电路设计

所设计的315 MHz/433 MHz ASK超外差式接收机电路采用MAX7033高集成度、低功耗CMOS、超外差式幅移键控(ASK)接收机,接收频率范围为300MHz～450 MHz,射频信号输入范围为-114 dBm～0 dBm,数据速率可达33 kb/s曼彻斯特码率(66 kb/s NRZ).介绍了MAX7033的主要技术性能、内部结构、工作原理和应用电路.     

Mobile antenna gain at 900 MHz

A program has been initiated to investigate the effect of the urban multipath environment on mobile antennas at 900 MHz. The program involves the constructuion of several mobile antennas, careful measurement of these antennas on an antenna range to determine their characteristics in a controlled environment, then measurement of their characteristics in the multipath environment of cities. Measured results are compared to computed results to permit generalized conclusions to be reached. This paper presents the results of the first phase of the program; measurements made in the controlled pattern range environment.     

Fully integrated CMOS phase-locked loop with 15 to 240 MHz lockingrange and ±50 ps jitter

A fully integrated phase-locked loop (PLL) in a digital 0.5 μm CMOS technology is described. The PLL has a locking range of 15 to 240 MHz. The static phase error is less than 1100 ps with a peak-to-peak jitter of ±50 ps at a 100 MHz output frequency. The PLL has a resistorless architecture achieved by the implementation of feedforward current injection into the current controlled oscillator     

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor

A 500 MHz, 32 bit RISC microprocessor has been experimentally developed using an 8-stage pipelined architecture and high-speed circuits, including a 500 MHz 1 kilobyte double-stage pipelined cache, a 1.8 ns register file, a double-stage binary look-ahead carry (BLC) adder circuit, and a 500 MHz phase locked loop (PLL) frequency multiplier. Newly developed circuit-integrating techniques include a stacked power-line structure, which serves as a noise shield and also provides low bounce, a low voltage-swing interface circuit with on-chip adjustable termination resistors, a small-skew clock distribution method, and a clock synchronization circuit which provides small-skew clock among LSI chips. About 200000 transistors are integrated into a 7.90 mm×8.84 mm die area with 0.4 μm CMOS fabrication technology. Power dissipation is 6 W at a 500 MHz operation and 3.3 V supply voltage     

A 50 MHz phase- and frequency-locked loop

A monolithic phase/frequency-locked loop has been developed for operation at up to 50 MHz. The loop combines wide capture range and narrow bandwidth, making it ideal for timing recovery in digital transmission systems. The 24-pin device features an electronically-tuned voltage-controlled LC oscillator and includes the input differentiation and full-wave rectification circuitry required for clock recovery from unipolar nonreturn-to-zero (NRZ) data.