Three-point-support method based on position determination of supports and wafers to eliminate gravity-induced deflection of wafers

The flatness measurement of large and thin wafers is affected greatly by gravity. Inverting method is often used to cancel the effect. However, it is required that the positions of the supports and wafers are perfectly symmetric about the inversion axis. In this study a three-point-support method based on position determination of supports and wafers was proposed. The supporting balls and the wafer were placed in arbitrary positions and their positions were obtained by measurement and fed into the FEM model which was developed to calculate the gravity-induced deflection (GID). The methods to acquire the positions of the supports and the wafer were proposed. The position measurement accuracy of the supports was improved greatly by circle fitting to the profile of the supporting ball. Wafer edge point was obtained accurately as the intersection point between the wafer surface line and the edge profile. The method to measure the wafer thickness using only one displacement sensor on the same equipment was presented. The simulation results were verified by experimental results. The centering device for the wafer and the positioning accuracy requirements of the supports are not needed any more. The effect of the positions of the supports and the wafer was reduced to be less than 1 μm for a 300 mm diameter and 397 μm thickness wafer with GID over 140 μm. This method could also be used for accurate flatness measurement of other large and thin panels.     

硅片边缘化学机械抛光的微小去除量测量

针对硅片化学机械抛光工艺的材料去除量非常微小并难以测量的问题,本文介绍一种采用表面粗糙度测量仪,对硅片边缘化学机械抛光的材料去除量进行一种简易、快速的测量方法,且该方法同时还可准确地测量硅片边缘抛光表面粗糙度值。检测结果表明,本方法较好地解决了硅片边缘化学机械抛光表面检测问题。     

Loss budget of a setup for measuring mechanical dissipations of silicon wafers between 300 and 4 K

A setup for measuring mechanical losses of silicon wafers has been fully characterized from room temperature to 4 K in the frequency range between 300 Hz and 4 kHz: it consists of silicon wafers with nodal suspension and capacitive and optical vibration sensors. Major contributions to mechanical losses are investigated and compared with experimental data scanning the full temperature range; in particular, losses due to the thermoelastic effect and to the wafer clamp are modeled via finite element method analysis; surface losses and gas damping are also estimated. The reproducibility of the measurements of total losses is also discussed and the setup capabilities for measuring additive losses contributed by thin films deposited on the wafers or bonding layers. For instance, assuming that additive losses are due to an 80-nm-thick wafer bond layer with Young modulus about ten times smaller than that of silicon, we achieve a sensitivity to bond losses at the level of 5x10(-3) at 4 K and at about 2 kHz.     

Dynamic position measurement technique for flash-on-the-fly wafer exposure

A wafer alignment technique is described for flash-on-the-fly operation of pulsed excimer laser exposure sources. The positioning requirements of the measurement system are defined and possible alignment patterns are discussed. A chevron grating is proposed as the basic measuring element and a ‘zeroth’ layer reference was used to improve image contrast. An array of etched pits bounded by the (111) crystal planes of the silicon wafer formed the reference pattern. Experimental results confirm that chevron gratings are a viable means of deriving alignment signals from wafers and the etched pit reference pattern gave good contrast throughout the process steps.     

内置皮拉尼计的硅通孔圆片级MEMS真空封装研究

针对现有的圆片级真空封装存在检测难、易泄漏等问题,提出了内置皮拉尼计的硅通孔圆片级MEMS真空封装方法。研制了用于圆片级真空封装导线互连的硅通孔,探讨了玻璃盖板与硅圆片之间阳极键合工艺与硅圆片与硅圆片之间的金硅共晶键合工艺,研制了用于检测封装壳体内部真空度的皮拉尼计; 研制了内置皮拉尼计的4英寸硅通孔圆片级真空封装,研制了低温激活非蒸散型吸气剂。实验研究表明,该研究解决了长时间保持真空度的问题。     

Effect of wafer size on material removal rate and its distribution in chemical mechanical polishing of silicon dioxide film

Chemical mechanical polishing (CMP) is a semiconductor fabrication process. In this process, wafer surfaces are smoothed and planarized using a hybrid removal mechanism, which consists of a chemical reaction and mechanical removal. In this study, the effects of wafer size on the material removal rate (MRR) and its uniformity in the CMP process were investigated using experiments and a mathematical model proposed in our previous research; this model was used to understand the MRR and its uniformity with respect to wafer size. Under constant process conditions, the MRR of a silicon dioxide (SiO₂) film increased slightly along with an increase in wafer size. The increase in MRR may be attributed to the acceleration of the chemical reaction due to a rise in process temperature. Based on the results obtained, the k and α values in the mathematical model are useful parameters for understanding the effect of wafer size on the MRR and its distribution under a uniform, relative velocity. These parameters can facilitate the prediction of CMP results and the effective design of a CMP machine.     

Measurement of the Minority Carrier Diffusion Length in Thin Wafers of Semiconductor Crystals

A method for the measurement of the minority carrier diffusion length and the estimation of the surface recombination rate in thin silicon wafers is described. The method is based on the measurement of the photocurrent flowing through a wafer with identical shallow-lying p–n junctions occupying a sufficiently large area on both sides of the wafer (a phototransistor with a disrupted base). Measurements are performed at two polarities of the bias voltage and two diameters of the radiation beam. Practical recommendations concerning the implementation of this method are given.     

化学机械抛光过程中护环对硅片表面接触压强分布和宏观轮廓的影响

为了获得单晶硅片化学机械抛光过程中护环对接触压强分布的影响规律,根据有护环化学机械抛光实际出发,建立了抛光过程的接触力学模型和边界条件,利用有限元的方法对有护环抛光接触状态接触压强分布进行了计算和分析,并利用抛光实验对计算获得结果进行了验证;获得了硅片与抛光垫间的接触表面压强分布形态,以及护环几何参数对压强分布的影响规律;结果表明护环抛光接触压强的分布也存在不均匀性,而且在硅片外径邻域内接触压强最大,这些也能导致被加工硅片产生平面度误差和塌边,选择合理地护环几何参量和负载比,可以改善接触压强场分布的均匀性。     

Effects of Self-Assembled Monolayer and PFPE Lubricant on Wear Characteristics of Flat Silicon Tips

The effects of self-assembled monolayer (SAM) and perfluoropolyether (PFPE) lubricant on the wear characteristics of flat silicon tips were investigated. The wear test consisted of sliding the silicon tips fabricated on a flat silicon specimen against SAM and PFPE (Z-tetraol) coated silicon (100) wafer. The tips were slid at a low speed for about 15 km under an applied load of 39.2 μN. The wear volume of the tip was obtained by measuring the tip profile using an Atomic Force Microscope (AFM). It was found that the coatings were effective in reducing the wear of the tips by an order of magnitude from 10⁻⁶ to 10⁻⁷.     

润湿性梯度集油表面制备及摩擦性能研究*

为了解决润滑油发生迁移，使接触面润滑油中断，导致润滑失效的问题，制备一种具有高集油性能的疏油-亲油-疏油的梯度表面。采用化学气相沉积的方法，在硅片表面沉积一层单分子膜，并采用接触角测量仪、UMT摩擦磨损试验机、共聚焦显微镜等对该样品进行表征，研究该类表面在限量供油条件下的润滑性能。结果表明：将油滴滴在疏油/亲油交界处，油滴能够迅速地从疏油区域向亲油区域运动；点接触往复运动摩擦实验结果表明，梯度表面硅片的摩擦因数明显低于原始的硅片，且梯度表面硅片的表面磨痕深度比原始硅片浅。各种实验结果表明，所制备的疏油-亲油-疏油梯度表面能够起到集油的作用，避免了润滑油中断的问题。     

Simultaneous measurement of emissivity and temperature of silicon wafers using a polarization technique

The emissivity of a silicon wafer under various conditions was theoretically and experimentally investigated. A quantitative relationship between the ratio of p-polarized to s-polarized radiances, and the polarized emissivity was obtained, irrespective of the emissivity change of silicon wafers due to oxide film thickness under wide variations of impurity concentration. We propose a new radiation thermometry method that can measure both the temperature and the spectral polarized emissivity of a silicon wafer, and we estimate the uncertainty of these measurements. Currently, the expanded uncertainty of the temperature measurement is estimated to be 3.52 K (2k) and 3.80 (2k) for p-polarization and s-polarization, respectively, at temperatures above 900 K.     

High precision chemical mechanical polishing of highly-boron-doped Si wafer used for epitaxial substrate

The surface waviness with concentric circular pattern is generated on highly-boron-doped Si wafer by chemical–mechanical polishing (CMP) with amine system polishing slurry. To investigate the generation mechanism of the waviness, the mechanical and chemical characteristics were clarified using the silicon crystal samples with various boron concentration level ranging from 2.9 × 10¹⁷ cm⁻³ to 1.3 × 10²⁰ cm⁻³. The conventional silicon substrate used as epitaxial wafer has boron concentration of about 2.5 × 10¹⁸ cm⁻³, a region at which the radical change of etching rate is induced with amine system chemical reagent. The mechanical micro-hardness of highly-boron-doped Si is 30% higher than that of lightly-doped Si. It is found that SiB bond in crystal lattice is firmed up and stabilized for mechanical stress and chemical reaction. To cancel the difference in CMP rate based on boron concentration deviation, increasing the mechanical action in CMP was proposed and performed. The precision CMP was performed using the harder polishing pad and a smooth surface without waviness was obtained.     

工件旋转法磨削硅片的磨粒切削深度模型

半导体器件制造中,工件旋转法磨削是大尺寸硅片正面平坦化加工和背面薄化加工最广泛应用的加工方法。磨粒切削深度是反映磨削条件综合作用的磨削参量,其大小直接影响磨削工件的表面/亚表面质量,研究工件旋转法磨削的磨粒切削深度模型对于实现硅片高效率高质量磨削加工具有重要的指导意义。通过分析工件旋转法磨削过程中砂轮、磨粒和硅片之间的相对运动,建立磨粒切削深度模型,得到磨粒切削深度与砂轮直径和齿宽、加工参数以及工件表面作用位置间的数学关系。根据推导的磨粒切削深度公式,进一步研究工件旋转法磨削硅片时产生的亚表面损伤沿工件半径方向的变化趋势以及加工条件对磨削硅片亚表面损伤的影响规律,并进行试验验证。结果表明,工件旋转法磨削硅片的亚表面损伤深度沿硅片半径方向从边缘到中心逐渐减小,随着砂轮磨粒粒径、砂轮进给速度、工件转速的增大和砂轮转速的减小,加工硅片的亚表面损伤也随之变大,试验结果与模型分析结果一致。     

Pad surface and coefficient of friction correlation analysis during friction between felt pad and single-crystal silicon

In wafer polishing pad surface plays a crucial role in the polishing process. With the increase of friction time between pad and wafer, the pad becomes flattened or glazed with particles clogging the pores of the pad and forming a layer of slurry residue and wafer particles, leading to changes of COF, material removal rates and higher defects on the wafer surface. Thus, this study aims to determine the correlation between pad surface deformation, slurry adhesive rate and Coefficient of friction (COF) during friction between felt pad and single -crystal silicon, to analyze the relationship between pad condition and COF. The real-time COF between felt pad and single-crystal silicon wafer are tested which are sorted in groups depending on various loads and oscillation frequencies and surfaces of felt pads measuring by Scanning electron microscope (SEM) are compared. The correlation between pad surface deformation and abrasive adhesion and COF is evaluated through analyzing the experiment results.

     

一种平面对准机构的运动学分析与参数标定研究

以太阳能硅片丝网印刷装备为研究平台,采用并联机构与视觉系统实现硅片和丝网的对准,得到并联机构运动学正反解,完成运动学参数补偿与误差分析;提出了一种区别于传统视觉标定的视觉自标定方法,所得优化参数使机械装配上引起的对准误差最小化。     

Numerical study on thermal stress cutting of silicon wafers using two-line laser beams

We propose a method of cleaving silicon wafers using two-line laser beams. The base principle is separating the silicon wafer using crack propagation caused by laser-induced thermal stress. Specifically, this method uses two-line laser beams parallel to the cutting line such that the movements of the laser beam along the cutting line can be omitted, which is necessary when using a point beam. To demonstrate the proposed method, 3D numerical analysis of a heat transfer and thermo-elasticity model was performed. Crack propagation was evaluated by comparing the stress intensity factor (SIF) at the crack tip with the fracture toughness of silicon, where crack propagation is assumed begin when the SIF exceeds the fracture toughness. The influences of laser power, line beam width, and distance between two laser beams were also investigated. The simulation results showed that the proposed method is appropriate for cleaving silicon wafers without any thermal damage.

     

Warping of silicon wafers subjected to back-grinding process

This study investigates warping of silicon wafers in ultra-precision grinding-based back-thinning process. By analyzing the interactions between the wafer and the vacuum chuck, together with the machining stress distributions in damage layer of ground wafer, the study establishes a mathematical model to describe wafer warping during the thinning process using the elasticity theory. The model correlates wafer warping with machining stresses, wafer final thickness, damage layer thickness, and the mechanical properties of the monocrystalline silicon. The maximum warp and the warp profile are measured on the wafers thinned to various thicknesses under different grinding conditions, and are used to verify the modeling results.     

一种快速检测单晶硅亚表面损伤层厚度的方法

为了保证单晶硅晶圆在精研与抛光过程中的品质与质量,亟待寻求一种快速、简单、经济的硅材料亚表面损伤程度的检测方法。基于HF溶液对单晶硅损伤层的选择性刻蚀特性,提出一种快速检测单晶硅亚表面损伤层厚度的方法。透射电镜观测结果显示,HF溶液能选择性地刻蚀单晶硅划痕区域的亚表面损伤层,证实了该方法检测结果的有效性。利用该方法研究了载荷和速度对单晶硅亚表面划痕损伤的影响。结果表明,当外加载荷为单晶硅临界屈服载荷的1.1倍及以下时,单晶硅亚表面的划痕损伤层厚度随刻画速度的增大而减小;而当外加载荷达到临界屈服载荷的12.5倍时,单晶硅亚表面的划痕损伤对刻画速度的变化不敏感。该方法可方便快捷地检测单晶硅划痕区域亚表面的损伤层厚度,有望应用于单晶硅晶圆平坦化过程的损伤检测与控制。     

A GRINDING-BASED MANUFACTURING METHOD FOR SILICON WAFERS: DECOMPOSITION ANALYSIS OF WAFER SURFACES

It is difficult for the lapping-based manufacturing method currently used to manufacture the majority of silicon wafers to meet the ever-increasing demand for flatter wafers at lower costs. A grinding-based manufacturing method for silicon wafers has been investigated. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. The generation mechanisms of the dimples and bumps in the central areas on ground wafers have also been studied. This paper reports another study on the grinding-based method, aiming to reduce the cost of chemical-mechanical polishing – the final material removal process in manufacturing of silicon wafers. Using design of experiments, investigations were carried out to understand the influences of grinding process variables on the peak-to-valley values of the polished wafer surfaces. It was found that the peak-to-valley values over the entire wafer surfaces did not show any relationship with grinding process variables. However, after analyzing the surface profiles by decomposing them into different frequencies, it was observed that there is a correlation between grinding process variables and certain surface feature components. Based on this finding, it is recommended to optimize the grinding process variables by minimizing the peak-to-valley values for each surface feature component, one at a time. This methodology has not been published for wafer grinding and is of practical use to the wafer industry.     

A GRINDING-BASED MANUFACTURING METHOD FOR SILICON WAFERS: DECOMPOSITION ANALYSIS OF WAFER SURFACES

It is difficult for the lapping-based manufacturing method currently used to manufacture the majority of silicon wafers to meet the ever-increasing demand for flatter wafers at lower costs. A grinding-based manufacturing method for silicon wafers has been investigated. It has been demonstrated that the site flatness on the ground wafers (except for a few sites at the wafer center) could meet the stringent specifications for future silicon wafers. The generation mechanisms of the dimples and bumps in the central areas on ground wafers have also been studied. This paper reports another study on the grinding-based method, aiming to reduce the cost of chemical-mechanical polishing - the final material removal process in manufacturing of silicon wafers. Using design of experiments, investigations were carried out to understand the influences of grinding process variables on the peak-to-valley values of the polished wafer surfaces. It was found that the peak-to-valley values over the entire wafer surfaces did not show any relationship with grinding process variables. However, after analyzing the surface profiles by decomposing them into different frequencies, it was observed that there is a correlation between grinding process variables and certain surface feature components. Based on this finding, it is recommended to optimize the grinding process variables by minimizing the peak-to-valley values for each surface feature component, one at a time. This methodology has not been published for wafer grinding and is of practical use to the wafer industry.