Instability of light illumination stress on amorphous In–Ga–Zn–O thin‐film transistors

Amorphous In–Ga–Zn–O thin‐film transistors (TFTs) have attracted increasing attention due to their electrical performance and their potential for use in transparent and flexible devices. Because TFTs are exposed to illumination through red, green, and blue color filters, wavelength‐varied light illumination tests are required to ensure stable TFT characteristics. In this paper, the effects of different light wavelengths under both positive and negative V_GS stresses on amorphous In–Ga–Zn–O TFTs are investigated. The TFT instability that is dependent on optical and electrical stresses can be explained by the charge trapping mechanism and interface modification.     

Driver‐circuits‐integrated LCDs based on novel amorphous In‐Ga‐Zn‐oxide TFT

Abstract— A liquid‐crystal panel integrated with a gate driver and a source driver by using amorphous In—Ga—Zn‐oxide TFTs was designed, prototyped, and evaluated. By using the process of bottom‐gate bottom‐contact (BGBC) TFTs, amorphous In—Ga—Zn‐oxide TFTs with superior characteristics were provided. Further, for the first time in the world, a 4‐in. QVGA liquid‐crystal panel integrated with a gate driver and a source driver was developed by using BGBC TFTs formed from an oxide semiconductor. By evaluating the liquid‐crystal panel, its functionality was successfully demonstrate. Based on the findings, it is believed that the novel BGBC amorphous In—Ga—Zn‐oxide TFT will be a promising candidate for future large‐screen backplanes having high definition.     

Back‐channel‐etched thin‐film transistor using c‐axis‐aligned crystal In–Ga–Zn oxide

Our crystalline In–Ga–Zn oxide (IGZO) thin film has a c‐axis‐aligned crystal (CAAC) structure and maintains crystallinity even on an amorphous base layer. Although the crystal has c‐axis alignment, its a‐axis and b‐axis have random arrangement; moreover, a clear grain boundary is not observed. We fabricated a back‐channel‐etched thin‐film transistor (TFT) using the CAAC‐IGZO film. Using the CAAC‐IGZO film, more stable TFT characteristics, even with a short channel length, can be obtained, and the instability of the back channel, which is one of the biggest problems of IGZO TFTs, is solved. As a result, we improved the process of manufacturing back‐channel‐etched TFTs.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Development of flexible displays using back‐channel‐etched In–Sn–Zn–O thin‐film transistors and air‐stable inverted organic light‐emitting diodes

We developed flexible displays using back‐channel‐etched In–Sn–Zn–O (ITZO) thin‐film transistors (TFTs) and air‐stable inverted organic light‐emitting diodes (iOLEDs). The TFTs fabricated on a polyimide film exhibited high mobility (32.9 cm²/Vs) and stability by utilization of a solution‐processed organic passivation layer. ITZO was also used as an electron injection layer (EIL) in the iOLEDs instead of conventional air‐sensitive materials. The iOLED with ITZO as an EIL exhibited higher efficiency and a lower driving voltage than that of conventional iOLEDs. Our approach of the simultaneous formation of ITZO film as both of a channel layer in TFTs and of an EIL in iOLEDs offers simple fabrication process.     

Fabrication of flexible organic light‐emitting‐diode display with a flexible color filter driven by In—Ga—Zn—Oxide TFTs

Abstract— A novel flexible active‐matrix organic light‐emitting‐diode (OLED) display fabricated on planarized stainless—used‐steel substrates with a resolution of 85 dpi in a 4.7‐in. active area has been demonstrated. Amorphous indium—gallium—zinc—oxide thin‐film transistors were used as the backplane for the OLED display with high device performance, high electrical stability, and long lifetime. A full‐color moving image at a frame frequency of 60 Hz was also realized by using a flexible color filter directly patterned on a plastic substrate with a white OLED as the light source.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Impact of humidity on the electrical performance of amorphous oxide semiconductor thin‐film transistors

An indium–gallium–zinc oxide or a zinc–tin oxide thin‐film transistor (TFT) fabricated when the relative humidity in the laboratory is less than 50% is found to exhibit good electrical performance, with an abrupt, distortion‐free transfer curve and a turn‐on voltage close to 0 V. In contrast, when such an amorphous oxide semiconductor (AOS) TFT is fabricated at a relative humidity greater than 50%, its “as‐fabricated” electrical performance is very poor, typically characterized by a large amount of hysteresis, a strongly negative turn‐on voltage, and a kink‐like distortion in the subthreshold region of its transfer curve. However, the electrical performance of such a poor‐quality TFT is observed to improve over time, if it is simply stored in the dark at room temperature without being subjected to electrical stress. This recovery usually requires weeks (months) for an unpassivated (passivated) AOS TFT. Recovery is tentatively ascribed to the gradual removal of moisture from the AOS TFT channel layer.     

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

In this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO₂ passivation.     

Amorphous In–Ga–Zn–O thin‐film transistors prepared by magnetron sputtering using Kr and Xe instead of Ar

Heavier noble gases Kr and Xe instead of the lighter Ar during the magnetron‐sputtering deposition of amorphous indium–gallium–zinc oxide films are introduced in fabricating their thin‐film transistors (TFTs). Heavy noble gases can reduce damage to film induced by ion bombardment during the sputtering depositions. Higher field‐effect mobility with better gate bias stability can be obtained in the heavier‐noble‐gas sputtered TFTs. Raman spectroscopic analysis and X‐ray reflectometry respectively suggest that the disordered structure in the film is suppressed, and the film becomes denser by introducing heavy noble gases, corresponding to the improvement of TFT performance.     

Instability dependent upon bias and temperature stress in amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors

Abstract— The effects of gate‐bias stress, drain‐bias stress, and temperature on the electrical parameters of amorphous‐indium gallium zinc oxide (a‐IGZO) thin‐film transistors have been investigated. Results demonstrate that the devices suffer from threshold‐voltage instabilities that are recovered at room temperature without any treatments. It is suggested that these instabilities result from the bias field and temperature‐assisted charging and discharging phenomenon of preexisting traps at the near‐interface and the a‐IGZO channel region. The experimental results show that applying a drain‐bias stress obviously impacts the instability of a‐IGZO TFTs; however, the instability caused by drain bias is not caused by hot‐electron generation as in conventional MOSFETs. And the degradation trend is affected by thermally activated carriers at high temperature.     

Solution‐processed oxide semiconductors for low‐cost and high‐performance thin‐film transistors and fabrication of organic light‐emitting‐diode displays

Abstract— High‐performance solution‐processed oxide‐semiconductor (OS) thin‐film transistors (TFTs) and their application to a TFT backplane for active‐matrix organic light‐emitting‐diode (AMOLED) displays are reported. For this work, bottom‐gated TFTs having spin‐coated amorphous In‐Zn‐O (IZO) active layers formed at 450°C have been fabricated. A mobility (μ) as high as 5.0 cm²/V‐sec, ?0.5 V of threshold voltage (VT), 0.7 V/dec of subthreshold swing (SS), and 6.9 × 10⁸ of on‐off current ratio were obtained by using an etch‐stopper (ES) structure TFT. TFTs exhibited uniform characteristics within 150 × 150‐mm² substrates. Based on these results, a 2.2‐in. AMOLED display driven by spin‐coated IZO TFTs have also been fabricated. In order to investigate operation instability, a negative‐bias‐temperature‐stress (NBTS) test was carried out at 60°C in ambient air. The IZO‐TFT showed ?2.5 V of threshold‐voltage shift (ΔVT) after 10,800 sec of stress time, comparable with the level (ΔVT = ?1.96 V) of conventional vacuum‐deposited a‐Si TFTs. Also, other issues regarding solution‐processed OS technology, including the instability, lowering process temperature, and printable devices are discussed.     

Modeling of threshold‐voltage‐shift dependency on drain bias in amorphous‐silicon thin‐film transistors in active‐matrix organic light‐emitting‐diode displays

Abstract— A theoretical model to interpret appearances of the threshold voltage shift in hydrogenated amorphous‐silicon (a‐Si:H) thin‐film transistors (TFTs) is developed to better understand the instability of a‐Si:H TFTs for the driving transistors in active‐matrix organic light‐emitting‐diode (AMOLED) displays. This model assumes that the defect creation at channel in a‐Si:H is proportional to the carrier concentration, leading to the defect density varying along the channel depending on the bias conditions. The model interprets a threshold‐voltage‐shift dependency on the drain‐stress bias. The model predicts the threshold voltage shift stressed under a given gate bias applying the drain saturation voltage is 66% of that with zero drain bias, and it even goes down to 50–60% of that when stressed by applying twice the drain saturation voltage.     

a‐InGaZnO thin‐film transistors for AMOLEDs: Electrical stability and pixel‐circuit simulation

Abstract— Inverted‐staggered amorphous In‐Ga‐Zn‐O (a‐InGaZnO) thin‐film transistors (TFTs) were fabricated and characterized on glass substrates. The a‐InGaZnO TFTs exhibit adequate field‐effect mobilities, sharp subthreshold slopes, and very low off‐currents. The current temperature stress (CTS) on the a‐InGaZnO TFTs was performed, and the effect of stress temperature (TSTR), stress current (ISTR), and TFT biasing condition on their electrical stability was investigated. Finally, SPICE modelling for a‐InGaZnO TFTs was developed based on experimental data. Several active‐matrix organic light‐emitting‐display (AMOLED) pixel circuits were simulated, and the potential advantages of using a‐InGaZnO TFTs were discussed.     

In‐pixel temperature sensor for high‐luminance active matrix micro‐light‐emitting diode display using low‐temperature polycrystalline silicon and oxide thin‐film‐transistors

We propose an in‐pixel temperature sensor using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistor (TFTs) for high‐luminance active matrix (AM) micro‐light‐emitting diode (LED) displays. By taking advantage of the different off‐current characteristics of p‐type LTPS TFTs and n‐type a‐IGZO TFTs under temperature change, we designed and fabricated a temperature sensor consists of only LTPO TFTs without additional sensing component or material. The fabricated sensor exhibits excellent temperature sensitivity of up to 71.8 mV/°C. In addition, a 64 × 64 temperature sensor array with 3T sensing pixel and integrated gate driver has also been fabricated, which demonstrates potential approach for maxing out the performance of high‐luminance AM micro‐LED display with real‐time in‐pixel temperature monitoring.     

Single‐source dual‐layer amorphous IGZO thin‐film transistors for display and circuit applications

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O₂/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.     

Letter: Mechanisms for on/off currents in dual‐gate a‐Si:H thin‐film transistors using indium‐tin‐oxide top‐gate electrodes

Abstract— Two types of dual‐gate a‐Si:H TFTs were made with transparent indium‐tin‐oxide (ITO) top‐gate electrodes of different lengths to investigate the static characteristics of these devices. By changing the length of the ITO top gate, we found that the variations in the on‐currents of these dual‐gate TFTs with dual‐gate driving are due to the high resistance of the parasitic intrinsic a‐Si:H regions between the back electron channel and the source/drain contact. In the off‐state of the dual‐gate‐driven TFTs, the Poole‐Frenkel effect is also enhanced due to back‐channel hole accumulation in the vicinity of the source/drain contact. Furthermore, we observed for the first time that under illumination the dual‐gate‐driven a‐Si:H TFTs exhibit extremely low photo‐leakage currents, much lower than that of single‐gate‐driven TFTs in a certain range (reverse subthreshold region) of negative gate voltages. The high on/off current ratio under backside illumination makes dual‐gate TFTs suitable devices for use as switching elements in liquid‐crystal displays (LCDs) or for other applications.     

Experimental decomposition of the positive bias temperature stress‐induced instability in self‐aligned coplanar InGaZnO thin‐film transistors and its modeling based on the multiple stretched‐exponential functions

Decomposition of the positive gate‐bias temperature stress (PBTS)‐induced instability into contributions of distinct mechanisms is experimentally demonstrated at several temperatures in top‐gate self‐aligned coplanar amorphous InGaZnO thin‐film transistors by combining the stress‐time‐divided measurements and the subgap density‐of‐states (DOS) extraction. It is found that the PBTS‐induced threshold voltage shift (ΔV_T) consists of three mechanisms: (1) increase of DOS due to excess oxygen in the active region; (2) shallow; and (3) deep charge trapping in the gate insulator components. Corresponding activation energy is 0.75, 0.4, and 0.9 eV, respectively. The increase of DOS is physically identified as the electron‐capture by peroxide. Proposed decomposition is validated by reproducing the PBTS time‐evolution of I–V characteristics through the technology computer‐aided design simulation into which the extracted DOS and charge trapping are incorporated. It is also found that the quantitative decomposition of PBTS‐induce ΔV_T accompanied with the multiple stretched‐exponential models enables an effective assessment of the complex degradation nature of multiple PBTS physical processes occurring simultaneously. Our results can be easily applied universally to any device with any stress conditions, along with guidelines for process optimization efforts toward ultimate PBTS stability.