Negative bias illumination stress assessment of indium gallium zinc oxide thin‐film transistors

Electrical performance stability of indium gallium zinc oxide (IGZO) thin‐film transistors (TFTs) is evaluated under negative bias illumination stress (NBIS). A bottom‐gate IGZO TFT whose top surface is passivated with zinc tin silicon oxide (ZTSO) exhibits a dramatic improvement in NBIS stability compared with that of an unpassivated, bottom‐gate IGZO TFT. Oxygen chemisorption/desorption at the channel layer top surface is proposed to explain why an unpassivated TFT exhibits significantly more NBIS than a passivated TFT.     

Effect of source/drain overlap region on device performance in a‐IGZO thin‐film transistors

Abstract— In this paper, the effect of source/drain overlap length on the amorphous indium gallium zinc oxide (a‐IGZO) TFT performance has been investigated. Results of this paper show that as source/drain overlap length decreases to a negative value forming S/D offset, the threshold voltage and S parameters of a‐IGZO TFTs increased and the field‐effect mobility decreased. The V_T variation increases sharply as the channel length decreases because of the large resistance R_offset when it is formed at a‐IGZO source/drain. In the experiment, R_offset of each 1 μm, evaluated from the transfer length method (TLM), shows approximately 54–66 kΩ. This means thatthe source/drain overlap length is a very important control parameter for uniform device characteristics of a‐IGZO TFTs.     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

High performance a‐IGZO thin‐film transistors with mf‐PVD SiO2 as an etch‐stop‐layer

In this work, we report on high‐performance bottom‐gate top‐contact (BGTC) amorphous‐Indium‐Gallium‐Zinc‐Oxide (a‐IGZO) thin‐film transistor (TFT) with SiO₂ as an etch‐stop‐layer (ESL) deposited by medium frequency physical vapor deposition (mf‐PVD). The TFTs show field‐effect mobility (μ_FE) of 16.0 cm²/(V.s), sub‐threshold slope (SS^?1) of 0.23 V/decade and off‐currents (I_OFF) < 1.0 pA. The TFTs with mf‐PVD SiO₂ ESL deposited at room temperature were compared with TFTs made with the conventional plasma‐enhanced chemical vapor deposition (PECVD) SiO₂ ESL deposited at 300 °C and at 200 °C. The TFTs with different ESLs showed a comparable performance regarding μ_FE, SS^?1, and I_OFF, however, significant differences were measured in gate bias‐stress stability when stressed under a gate field of +/?1 MV/cm for duration of 10⁴ s. The TFTs with mf‐PVD SiO₂ ESL showed lower threshold‐voltage (V_TH) shifts compared with TFTs with 300 °C PECVD SiO₂ ESL and TFTs with 200 °C PECVD SiO₂ ESL. We associate the improved bias‐stress stability of the mf‐PVD SiO₂ ESL TFTs to the low hydrogen content of the mf‐PVD SiO₂ layer, which has been verified by Rutherford‐Back‐Scattering‐Elastic‐Recoil‐Detection technique.     

Single‐source dual‐layer amorphous IGZO thin‐film transistors for display and circuit applications

In this study, the authors report on high‐quality amorphous indium–gallium–zinc oxide thin‐film transistors (TFTs) based on a single‐source dual‐layer concept processed at temperatures down to 150°C. The dual‐layer concept allows the precise control of local charge carrier densities by varying the O₂/Ar gas ratio during sputtering for the bottom and top layers. Therefore, extensive annealing steps after the deposition can be avoided. In addition, the dual‐layer concept is more robust against variation of the oxygen flow in the deposition chamber. The charge carrier density in the TFT channel is namely adjusted by varying the thickness of the two layers whereby the oxygen concentration during deposition is switched only between no oxygen for the bottom layer and very high concentration for the top layer. The dual‐layer TFTs are more stable under bias conditions in comparison with single‐layer TFTs processed at low temperatures. Finally, the applicability of this dual‐layer concept in logic circuitry such as 19‐stage ring oscillators and a TFT backplane on polyethylene naphthalate foil containing a quarter video graphics array active‐matrix organic light‐emitting diode display demonstrator is proven.     

Uniformity and bias‐temperature instability of bottom‐gate zinc oxide thin‐film transistors (ZnO TFTs)

Abstract— Short‐range uniformity and bias‐temperature (BT) instability of ZnO TFTs with SiO^x/SiN^x stacked gate insulators which have different surface treatments have been investigated. The short‐range uniformity of ZnO TFTs was drastically improved by N²O plasma treatment of the gate insulator. The variation in the gate voltage where a drain current of 1‐nA flows (Vgs at an Ids of 1 nA) was dramatically reduced from ±1.73 V to ±0.07 V by N²O plasma treatment of the gate insulator. It was clarified that the variations in the subthreshold characteristics of the ZnO TFTs could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the variation of trap densities in deep energy levels from 0.9–2.0 × 10¹⁷ to 1.2–1.3×10¹⁷ cm^?3‐eV^?1. From the BT stress tests, a positive shift of Vgs at an Ids of 1 nA could be reduced by N²O plasma treatment of the gate insulator due to a decrease in the charge traps in the gate insulator. When the gate‐bias stress increases, state creation occured in the ZnO TFTs in addition to the charge trapping in the gate insulator. However, N²O plasma treatment of the gate insulator has little effect on the suppression of the state creation in ZnO TFTs under BT stress. The surface treatment of the gate insulator strongly affects the short‐range uniformity and the BT instability of Vth in the ZnO TFTs.     

Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Active‐matrix organic light‐emitting diode displays with indium gallium zinc oxide thin‐film transistors and normal,inverted, and transparent organic light‐emitting diodes

Abstract— Active‐matrix organic light‐emitting diode (AMOLED) displays have gained wide attention and are expected to dominate the flat‐panel‐display industry in the near future. However, organic light‐emitting devices have stringent demands on the driving transistors due to their current‐driving characteristics. In recent years, the oxide‐semiconductor‐based thin‐film transistors (oxide TFTs) have also been widely investigated due to their various benefits. In this paper, the development and performance of oxide TFTs will be discussed. Specifically, effects of back‐channel interface conditions on these devices will be investigated. The performance and bias stress stability of the oxide TFTs were improved by inserting a SiO^x protection layer and an N²O plasma treatment on the back‐channel interface. On the other hand, considering the n‐type nature of oxide TFTs, 2.4‐in. AMOLED displays with oxide TFTs and both normal and inverted OLEDs were developed and their reliability was studied. Results of the checkerboard stimuli tests show that the inverted OLEDs indeed have some advantages due to their suitable driving schemes. In addition, a novel 2.4‐in. transparent AMOLED display with a high transparency of 45% and high resolution of 166 ppi was also demonstrated using all the transparent or semi‐transparent materials, based on oxide‐TFT technologies.     

Impact of humidity on the electrical performance of amorphous oxide semiconductor thin‐film transistors

An indium–gallium–zinc oxide or a zinc–tin oxide thin‐film transistor (TFT) fabricated when the relative humidity in the laboratory is less than 50% is found to exhibit good electrical performance, with an abrupt, distortion‐free transfer curve and a turn‐on voltage close to 0 V. In contrast, when such an amorphous oxide semiconductor (AOS) TFT is fabricated at a relative humidity greater than 50%, its “as‐fabricated” electrical performance is very poor, typically characterized by a large amount of hysteresis, a strongly negative turn‐on voltage, and a kink‐like distortion in the subthreshold region of its transfer curve. However, the electrical performance of such a poor‐quality TFT is observed to improve over time, if it is simply stored in the dark at room temperature without being subjected to electrical stress. This recovery usually requires weeks (months) for an unpassivated (passivated) AOS TFT. Recovery is tentatively ascribed to the gradual removal of moisture from the AOS TFT channel layer.     

Transfer‐curve assessment of oxide thin‐film transistors

Abstract— Oxide electronics is an emerging area that is well positioned to strongly and positively impact next‐generation display technology. A metal‐oxide thin‐film transistor (TFT) is the fundamental component of oxide electronics. Unfortunately, some of the claims made in the literature about the performance of oxide TFTs are, in this author's opinion, unreliable. This is true of turn‐on voltage, subthreshold swing, and, especially, channel mobility. Measurement artifacts can lead to unreliable performance estimates. The goal of this contribution is to enumerate some of these artifacts and to outline a general testing procedure for avoiding common oxide‐TFT assessment pitfalls.     

Impact of source/drain contacts formation of self‐aligned amorphous‐IGZO TFTs on their negative‐bias‐illumination‐stress stabilities

In this study, we have compared the performance of self‐aligned a‐IGZO thin‐film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiN_x interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field‐effect mobility (μ_FE) of over 10.0 cm²/(V.s), sub‐threshold slope (SS^‐1) of 0.5 V/decade, and current ratio (I_ON/I_OFF) over 10⁸. However, under negative‐bias‐illumination‐stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma‐treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel.     

Instability of light illumination stress on amorphous In–Ga–Zn–O thin‐film transistors

Amorphous In–Ga–Zn–O thin‐film transistors (TFTs) have attracted increasing attention due to their electrical performance and their potential for use in transparent and flexible devices. Because TFTs are exposed to illumination through red, green, and blue color filters, wavelength‐varied light illumination tests are required to ensure stable TFT characteristics. In this paper, the effects of different light wavelengths under both positive and negative V_GS stresses on amorphous In–Ga–Zn–O TFTs are investigated. The TFT instability that is dependent on optical and electrical stresses can be explained by the charge trapping mechanism and interface modification.     

Solution‐processed oxide semiconductors for low‐cost and high‐performance thin‐film transistors and fabrication of organic light‐emitting‐diode displays

Abstract— High‐performance solution‐processed oxide‐semiconductor (OS) thin‐film transistors (TFTs) and their application to a TFT backplane for active‐matrix organic light‐emitting‐diode (AMOLED) displays are reported. For this work, bottom‐gated TFTs having spin‐coated amorphous In‐Zn‐O (IZO) active layers formed at 450°C have been fabricated. A mobility (μ) as high as 5.0 cm²/V‐sec, ?0.5 V of threshold voltage (VT), 0.7 V/dec of subthreshold swing (SS), and 6.9 × 10⁸ of on‐off current ratio were obtained by using an etch‐stopper (ES) structure TFT. TFTs exhibited uniform characteristics within 150 × 150‐mm² substrates. Based on these results, a 2.2‐in. AMOLED display driven by spin‐coated IZO TFTs have also been fabricated. In order to investigate operation instability, a negative‐bias‐temperature‐stress (NBTS) test was carried out at 60°C in ambient air. The IZO‐TFT showed ?2.5 V of threshold‐voltage shift (ΔVT) after 10,800 sec of stress time, comparable with the level (ΔVT = ?1.96 V) of conventional vacuum‐deposited a‐Si TFTs. Also, other issues regarding solution‐processed OS technology, including the instability, lowering process temperature, and printable devices are discussed.     

Effects of gate‐bias stress on ZnO thin‐film transistors

Abstract— The effects of gate‐bias and thermal stress on the stability issues of zinc oxide thin film transistors (ZnO TFTs) deposited on glass substrates were investigated. The shift in threshold voltage for devices undergoing various post‐growth annealing conditions using a stretched‐exponential formalism was analyzed. The analysis indicated that the extracted parameters such as the time constant and the effective energy barrier (E^τ) can be correlated to the device trap states associated with the annealing conditions. Improvement in the channel conductance and interface quality, hence the resultant device stability, can therefore be resumed when subject to a thermal treatment at 400°C for 30 minutes compared with those annealed for a shorter time.     

Comparative study of source–drain contact metals for amorphous InGaZnO thin‐film transistors

In this work, we compared the thin‐film transistor (TFT) characteristics of amorphous InGaZnO TFTs with six different source–drain (S/D) metals (MoCr, TiW, Ni, Mo, Al, and Ti/Au) fabricated in bottom‐gate bottom‐contact (BGBC) and bottom‐gate top‐contact (BGTC) configurations. In the BGTC configuration, nearly every metal can be injected nicely into the a‐IGZO leading to nice TFT characteristics; however, in the BGBC configuration, only Ti/Au is injected nicely and shows comparable TFT characteristics. We attribute this to the metal‐containing deposits in the channel and the contact oxidation during a‐IGZO layer sputtering in the presence of S/D metal. In bias‐stress stability, TFTs with Ti/Au S/D metal showed good results in both configurations; however, in the BGTC configuration, not all the TFTs showed as good bias results as Ti/Au S/D metal TFTs. We attribute this to backchannel interface change, which happened because of the metal‐containing deposits at the backchannel during the final the SiO₂ passivation.     

Circuits and AMOLED display with self‐aligned a‐IGZO TFTs on polyimide foil

A process to make self‐aligned top‐gate amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field‐effect mobility of 12.0 cm²/(V.s), sub‐threshold slope of 0.5 V/decade, and current ratio (I_ON/OFF) of >10⁷. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (?1.0 MV/cm) bias direction after extended stressing time of 10⁴ s. We achieve a stage‐delay of ~19.6 ns at V_DD = 20 V measured in a 41‐stage ring oscillator. A top‐emitting quarter‐quarter‐video‐graphics‐array active‐matrix organic light‐emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V_DD), the brightness of the display exceeds 150 cd/m².     

a‐InGaZnO thin‐film transistors for AMOLEDs: Electrical stability and pixel‐circuit simulation

Abstract— Inverted‐staggered amorphous In‐Ga‐Zn‐O (a‐InGaZnO) thin‐film transistors (TFTs) were fabricated and characterized on glass substrates. The a‐InGaZnO TFTs exhibit adequate field‐effect mobilities, sharp subthreshold slopes, and very low off‐currents. The current temperature stress (CTS) on the a‐InGaZnO TFTs was performed, and the effect of stress temperature (TSTR), stress current (ISTR), and TFT biasing condition on their electrical stability was investigated. Finally, SPICE modelling for a‐InGaZnO TFTs was developed based on experimental data. Several active‐matrix organic light‐emitting‐display (AMOLED) pixel circuits were simulated, and the potential advantages of using a‐InGaZnO TFTs were discussed.     

Memory effects of all‐solution‐processed oxide thin‐film transistors using ZnO nanoparticles

Abstract— Non‐volatile memory effects of an all‐solution‐processed oxide thin‐film transistor (TFT) with ZnO nanoparticles (NPs) as the charge‐trapping layer are reported. The device was fabricated by using a soluble MgInZnO active channel on a ZrHfO^x gate dielectric. ZnO NPs were used as the charge‐trapping site at the gate‐insulator—channel interface, and Al was used for source and drain electrodes. Transfer characteristics of the device showed a large clockwise hysteresis, which can be used to demonstrate its memory function due to electron trapping in the ZnO NP charge‐trapping layer. This memory effect has the potential to be utilized as a memory application on displays and disposable electronics.     

Influence of channel‐deposition conditions and gate insulators on performance and stability of top‐gate IGZO transparent thin‐film transistors

Abstract— Amorphous‐oxide‐semiconductor thin‐film transistors (TFTs) have gained wide attention in recent years due to their many merits. In this paper, a series of top‐gate transparent thin‐film transistors (TFTs) based on amorphous‐indium—gallium—zinc—oxide (a‐IGZO) semiconductors have been fabricated and investigated. Specifically, low‐temperature SiNx and SiOx were used as the gate insulator and different Ar/O² gas‐flow ratios were used for a‐IGZO channel deposition to study the influences of gate insulators and channel‐deposition conditions. In addition to the investigation of device performance, the stability of these TFTs was also examined by applying constant‐current stressing. It was found that a high mobility of 30‐45 cm²/V‐sec and small threshold‐voltage shift in constant‐current stressing can be achieved using SiNx with suitable hydrogen‐content stoichiometry as the gate insulator and the carefully adjusted Ar/O² flow ratio for channel deposition. These results may be associated with hydrogen incorporation into the channel, the lower defect trap density, and the better water/oxygen barrier properties (impermeability) of the low‐temperature SiNx.     

Modeling of current—voltage characteristics for double‐gate a‐IGZO TFTs and its application to AMLCDs

Abstract— The equations for the transfer characteristics, subthreshold swing, and saturation voltage of double‐gate (DG) a‐IGZO TFTs, when the top‐ and bottom‐gate electrodes are connected together (synchronized), were developed. From these equations, it is found thatsynchronized DG a‐IGZO TFTs can be considered as conventional TFTs with a modified gate capacitance and threshold voltage. The developed models were compared with the top or bottom gate only bias conditions. The validity of the models is discussed by using the extracted TFT parameters for DG coplanar homojunction TFTs. Lastly, the new pixel circuit and layout based on a synchronized DG a‐IGZO TFT is introduced.