Novel top‐gate zinc oxide thin‐film transistors (ZnO TFTs) for AMLCDs

Abstract— High‐performance top‐gate thin‐film transistors (TFTs) with a transparent zinc oxide (ZnO) channel have been developed. ZnO thin films used as active channels were deposited by rf magnetron sputtering. The electrical properties and thermal stability of the ZnO films are controlled by the deposition conditions. A gate insulator made of silicon nitride (SiN_x) was deposited on the ZnO films by conventional P‐CVD. A novel ZnO‐TFT process based on photolithography is proposed for AMLCDs. AMLCDs having an aperture ratio and pixel density comparable to those of a‐Si:H TFT‐LCDs are driven by ZnO TFTs using the same driving scheme of conventional AMLCDs.     

Effects of gate‐bias stress on ZnO thin‐film transistors

Abstract— The effects of gate‐bias and thermal stress on the stability issues of zinc oxide thin film transistors (ZnO TFTs) deposited on glass substrates were investigated. The shift in threshold voltage for devices undergoing various post‐growth annealing conditions using a stretched‐exponential formalism was analyzed. The analysis indicated that the extracted parameters such as the time constant and the effective energy barrier (E^τ) can be correlated to the device trap states associated with the annealing conditions. Improvement in the channel conductance and interface quality, hence the resultant device stability, can therefore be resumed when subject to a thermal treatment at 400°C for 30 minutes compared with those annealed for a shorter time.     

Memory effects of all‐solution‐processed oxide thin‐film transistors using ZnO nanoparticles

Abstract— Non‐volatile memory effects of an all‐solution‐processed oxide thin‐film transistor (TFT) with ZnO nanoparticles (NPs) as the charge‐trapping layer are reported. The device was fabricated by using a soluble MgInZnO active channel on a ZrHfO^x gate dielectric. ZnO NPs were used as the charge‐trapping site at the gate‐insulator—channel interface, and Al was used for source and drain electrodes. Transfer characteristics of the device showed a large clockwise hysteresis, which can be used to demonstrate its memory function due to electron trapping in the ZnO NP charge‐trapping layer. This memory effect has the potential to be utilized as a memory application on displays and disposable electronics.     

In‐pixel temperature sensor for high‐luminance active matrix micro‐light‐emitting diode display using low‐temperature polycrystalline silicon and oxide thin‐film‐transistors

We propose an in‐pixel temperature sensor using low‐temperature polycrystalline silicon and oxide (LTPO) thin‐film transistor (TFTs) for high‐luminance active matrix (AM) micro‐light‐emitting diode (LED) displays. By taking advantage of the different off‐current characteristics of p‐type LTPS TFTs and n‐type a‐IGZO TFTs under temperature change, we designed and fabricated a temperature sensor consists of only LTPO TFTs without additional sensing component or material. The fabricated sensor exhibits excellent temperature sensitivity of up to 71.8 mV/°C. In addition, a 64 × 64 temperature sensor array with 3T sensing pixel and integrated gate driver has also been fabricated, which demonstrates potential approach for maxing out the performance of high‐luminance AM micro‐LED display with real‐time in‐pixel temperature monitoring.     

Zinc oxide by ALD for thin‐film‐transistor application

Abstract— High‐quality ZnO thin films for transparent thin‐film transistors (TFTs) were successfully prepared by using an injection‐type source delivery system for atomic layer deposition (ALD). By using this delivery system, the source delivery pulse time was dramatically reduced to 0.002 sec to minimize processing time. The growth of ZnO thin film at a relatively low temperature of 150°C shows good characteristics. The process factors on the reactants for film growth were characterized. The bottom‐contact bottom‐gate ZnO TFT shows good electrical properties with solid saturation.     

a‐InGaZnO thin‐film transistors for AMOLEDs: Electrical stability and pixel‐circuit simulation

Abstract— Inverted‐staggered amorphous In‐Ga‐Zn‐O (a‐InGaZnO) thin‐film transistors (TFTs) were fabricated and characterized on glass substrates. The a‐InGaZnO TFTs exhibit adequate field‐effect mobilities, sharp subthreshold slopes, and very low off‐currents. The current temperature stress (CTS) on the a‐InGaZnO TFTs was performed, and the effect of stress temperature (TSTR), stress current (ISTR), and TFT biasing condition on their electrical stability was investigated. Finally, SPICE modelling for a‐InGaZnO TFTs was developed based on experimental data. Several active‐matrix organic light‐emitting‐display (AMOLED) pixel circuits were simulated, and the potential advantages of using a‐InGaZnO TFTs were discussed.     

Oxide engineering of ZnO thin‐film transistors for flexible electronics

Abstract— In this paper, we show that ZnO thin‐film transistors (TFTs) are potentially a higher performance alternative to organic and amorphous‐Si TFTs for macroelectronics on plastic substrates. Specifically, we fabricated nanocrystalline ZnO thin‐film transistors using low‐temperature processing, compatible with flexible electronics on plastic substrates. The ZnO semiconductor was rf magnetron sputtered, and the Al₂O₃ gate dielectric was deposited either by electron‐beam evaporation or atomic layer deposition. By controlling the partial pressure of oxygen pO₂) during ZnO sputtering, we could engineer the field‐effect mobility of ZnO transistors to be between 2 and 42 cm²/V‐sec, attractive for high‐performance electronic applications. We contend that pO₂ controls the oxygen‐vacancy content or stoichiometry of ZnO, and that allows control of transistor field‐effect mobility. Although most of the devices described here were fabricated on Si substrates, devices we made on a thin (50 μm thick) polyimide substrate had about equivalent performance, affirming the compatibility of our processes with plastic substrates. Finally, we show that properties of our nanocrystalline ZnO transistors can be explained by transport models that account for grain‐boundary trapping of mobile carriers.     

A course on thin‐film transistor circuit design for modern displays

A new subject‐specific course on thin‐film transistor (TFT) circuit design is introduced, covering related knowledge of display technologies, TFT device physics, processing, characterization, modeling and circuit design. A design project is required for students to deepen the understanding even more and get hands‐on design experience. This course can be an intense 1‐week course to offer a full training of design engineers in an organized way to meet the ever‐increasing needs in display industry for TFT circuit design specialists. It can also be organized in one semester for electrical engineering Master's and Ph.D. students.     

Multioutputs single‐stage gate driver on array with wide temperature operable thin‐film‐transistor liquid‐crystal display for high resolution application

A hydrogenated amorphous silicon (a‐Si:H) thin‐film transistor (TFT) gate driver with multioutputs (eight outputs per stage) for high reliability, 10.7‐inch automotive display has been proposed. The driver circuit is composed of one SR controller, eight driving TFTs (one stage to eight outputs) with bridging TFTs. The SR controller, which starts up the driving TFTs, could also prevent the noise of gate line for nonworking period. The bridging TFT, using width decreasing which connects between the SR controller and the driving TFT, could produce the floating state which is beneficial to couple the gate voltage, improves the driving ability of output, and reaches consistent rising time in high temperature and low temperature environment. Moreover, 8‐phase clocks with 75% overlapping and dual‐side driving scheme are also used in the circuit design to ensure enough charging time and reduce the loading of each gate line. According to lifetime test results, the proposed gate driver of 720 stages pass the extreme temperature range test (90°C and ?40°C) for simulation, and operates stably over 800 hours at 90°C for measurement. Besides, this design is successfully demonstrated in a 10.7‐inch full HD (1080 × RGB×1920) TFT‐liquid‐crystal display (LCD) panel.     

Instability of light illumination stress on amorphous In–Ga–Zn–O thin‐film transistors

Amorphous In–Ga–Zn–O thin‐film transistors (TFTs) have attracted increasing attention due to their electrical performance and their potential for use in transparent and flexible devices. Because TFTs are exposed to illumination through red, green, and blue color filters, wavelength‐varied light illumination tests are required to ensure stable TFT characteristics. In this paper, the effects of different light wavelengths under both positive and negative V_GS stresses on amorphous In–Ga–Zn–O TFTs are investigated. The TFT instability that is dependent on optical and electrical stresses can be explained by the charge trapping mechanism and interface modification.     

Influence of channel‐deposition conditions and gate insulators on performance and stability of top‐gate IGZO transparent thin‐film transistors

Abstract— Amorphous‐oxide‐semiconductor thin‐film transistors (TFTs) have gained wide attention in recent years due to their many merits. In this paper, a series of top‐gate transparent thin‐film transistors (TFTs) based on amorphous‐indium—gallium—zinc—oxide (a‐IGZO) semiconductors have been fabricated and investigated. Specifically, low‐temperature SiNx and SiOx were used as the gate insulator and different Ar/O² gas‐flow ratios were used for a‐IGZO channel deposition to study the influences of gate insulators and channel‐deposition conditions. In addition to the investigation of device performance, the stability of these TFTs was also examined by applying constant‐current stressing. It was found that a high mobility of 30‐45 cm²/V‐sec and small threshold‐voltage shift in constant‐current stressing can be achieved using SiNx with suitable hydrogen‐content stoichiometry as the gate insulator and the carefully adjusted Ar/O² flow ratio for channel deposition. These results may be associated with hydrogen incorporation into the channel, the lower defect trap density, and the better water/oxygen barrier properties (impermeability) of the low‐temperature SiNx.     

Characteristics improvement of top‐gate self‐aligned amorphous indium gallium zinc oxide thin‐film transistors using a dual‐gate control

In this work, we have reported dual‐gate amorphous indium gallium zinc oxide thin‐film transistors (a‐IGZO TFTs), where a top‐gate self‐aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a‐IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (I_ON), sub‐threshold slope (SS^?1), output resistance, and bias‐stress instabilities are improved in comparison with single‐gate control self‐aligned a‐IGZO TFTs. We have also investigated the applicability of the dual‐gate a‐IGZO TFTs in logic circuitry such as 19‐stage ring oscillators.     

Flexible thin‐film transistors application of amorphous tin oxide‐based semiconductors

The structural, optical, and electrical properties of Si‐doped SnO₂ (STO) films were investigated in terms of their potential applications for flexible electronic devices. All STO films were amorphous with an optical transmittance of ~90%. The optical band gap was widened as the Si content increased. The Hall mobility and carrier density were improved in the SnO₂ with 1 wt% Si film, which was attributed to the formation of donor states. Si (1 wt%) doped SnO₂ thin‐film transistor exhibited a good device performance and good stability with a saturation mobility of 6.38 cm²/Vs, a large I_on/I_off of 1.44 × 10⁷, and a SS value of 0.77 V/decade. The device mobility of a‐STO TFTs at different bending radius maintained still at a high level. These results suggest that a‐STO thin films are promising for fabricating flexible TFTs.     

Letter: Solution‐processed flexible zinc‐tin oxide thin‐film transistors on ultra‐thin polyimide substrates

In this letter, solution‐processed flexible zinc‐tin oxide (Z_0.35T_0.65O_1.7) thin‐film transistors with electrochemically oxidized gate insulators (AlOx:Nd) fabricated on ultra‐thin (30 µm) polyimide substrates are presented. The AlOx:Nd insulators exhibited wonderful stability under bending and excellent insulating properties with low leakage current, high dielectric constant, and high breakdown field. The device exhibited a mobility of 3.9 cm²/V · s after annealing at 300 °C. In addition, the flexible device was able to maintain the electricity performance under various degrees of bending, which was attributed to the ultra‐thin polyimide substrate.     

High‐performance vacuum‐processed metal oxide thin‐film transistors: A review of recent developments

Since 2010, vacuum‐processed oxide semiconductors have greatly improved with the publication of more than 1,300 related papers. Although the number of researches on oxide semiconductors has continued to increase year by year, the average field‐effect mobility of oxide semiconductor thin‐film transistors (TFTs) has not shown significant improvement; from 2010 to 2018; the average field‐effect mobility of vacuum‐processed n‐type oxide TFTs is around 20 cm²/Vs. To investigate the obstacles for performance improvements, the latest progress and researches on vacuum‐processed oxide semiconductor TFTs for high performance over the past decade are highlighted, along with the pros and cons of each technology. Finally, complementary metal oxide semiconductor (CMOS) logic circuits composed of both n‐ and p‐type oxide semiconductor TFTs are introduced, and future prospects for this state‐of‐the‐art research on the oxide semiconductors are presented.     

Laser‐irradiated zinc oxide thin‐film transistors fabricated by solution processing

Abstract— This study investigates the effects of subjecting zinc oxide (ZnO) thin films to laser irradiation. The optical, structural, and electrical properties of the as‐deposited and laser‐irradiated films at different laser energies were studied. The transmittances without/with laser irradiation showed a net increase from 85 to 92% (@550 nm) for 250‐nm ZnO films, indicating an improvement in sample crystal linity. In addition, laser treatment decreased the ZnO band gap. Composition structure analysis shows that the crystallinity increased when the laser energy increased. Thin‐film transistors (TFTs) with a ZnO active layer were fabricated. The mobility of as‐deposited ZnO TFT devices (0.19 cm²/V‐sec) increased more than 2.5 times for ZnO of unirradiated laser treatment (0.49 cm²/V‐sec).     

Solution‐processed oxide thin‐film transistors using aluminum and nitrate precursors for low‐temperature annealing

Abstract— In this article, a solution process for oxide thin‐film transistors (TFTs) at low‐temperature annealing was investigated. Solution‐process engineering, including materials and precursors, plays an important role in oxide thin‐film deposition on large glass and flexible substrates at low temperature. Reactive material could reduce the alloy reaction temperature for a multicomponent oxide system. A volatile precursor could also reduce annealing temperature in the formation of metal‐oxide thin films. A solution process with reactive Al and a volatile nitrate precursor can demonstrates competitive oxide TFTs at 350°C.     

Experimental decomposition of the positive bias temperature stress‐induced instability in self‐aligned coplanar InGaZnO thin‐film transistors and its modeling based on the multiple stretched‐exponential functions

Decomposition of the positive gate‐bias temperature stress (PBTS)‐induced instability into contributions of distinct mechanisms is experimentally demonstrated at several temperatures in top‐gate self‐aligned coplanar amorphous InGaZnO thin‐film transistors by combining the stress‐time‐divided measurements and the subgap density‐of‐states (DOS) extraction. It is found that the PBTS‐induced threshold voltage shift (ΔV_T) consists of three mechanisms: (1) increase of DOS due to excess oxygen in the active region; (2) shallow; and (3) deep charge trapping in the gate insulator components. Corresponding activation energy is 0.75, 0.4, and 0.9 eV, respectively. The increase of DOS is physically identified as the electron‐capture by peroxide. Proposed decomposition is validated by reproducing the PBTS time‐evolution of I–V characteristics through the technology computer‐aided design simulation into which the extracted DOS and charge trapping are incorporated. It is also found that the quantitative decomposition of PBTS‐induce ΔV_T accompanied with the multiple stretched‐exponential models enables an effective assessment of the complex degradation nature of multiple PBTS physical processes occurring simultaneously. Our results can be easily applied universally to any device with any stress conditions, along with guidelines for process optimization efforts toward ultimate PBTS stability.     

Comparative study on extraction methods of threshold voltage for thin‐film transistors

In this work, we proposed three methods on extracting threshold voltage of ploy‐silicon thin‐film transistors, such as, extrapolation of the linear region, transconductance linear extrapolation, and second derivation. Based on these different methods, one can extract various values of threshold voltages, as well as their temperature dependence. In room temperature, the second derivation method is the most appropriate for thin‐film transistors. More remarkably, the different methods show the different temperature dependence of mobility, corresponding to different charge transport mechanisms. That is, hopping dominates the transport mechanism for extrapolation of the linear region method, while it will occur to transform from band‐like to hopping mechanism for the second derivative method.     

Impact of bending on flexible metal oxide TFTs and oscillator circuits

Thin‐film circuits on plastic capable of high‐frequency signal generation have important applications in large‐area, flexible hybrid systems, enabling efficient wireless transmission of power and information. We explore oscillator circuits using zinc‐oxide thin‐film transistors (ZnO TFTs) deposited by the conformal, layer‐by‐layer growth technique of plasma‐enhanced atomic layer deposition. TFTs on three substrates—glass, 50‐µm‐thick freestanding polyimide, and 3.5‐µm‐thick spin‐cast polyimide—are evaluated to identify the best candidate for high‐frequency flexible oscillators. We find that TFTs on ultrathin plastic can endure bending to smaller radii than TFTs on commercial 50‐µm‐thick freestanding polyimide, and their superior dimensional stability furthermore allows for smaller gate resistances and device capacitances. Oscillators on ultrathin plastic with minimized parasitics achieve oscillation frequencies as high as 17 MHz, well above the cutoff frequency f_T. Lastly, we observe a bending radius dependence of oscillation frequency for flexible TFT oscillators and examine how mitigating device parasitics benefits the oscillator frequency versus power consumption tradeoff.