TD-SCDMA中基于块判决反馈的联合检测算法及其VLSI实现

为了降低TD-SCDMA的终端成本,该文提出了一种基于块判决反馈的联合检测算法。与已有的联合检测算法相比,该算法以微小的性能损失为代价,极大地降低了计算复杂度,从而使得TD-SCDMA的联合检测协处理器面积小、功耗低、实现容易。在该算法的基础上,该文给出了终端联合检测协处理器的VLSI架构。在0.18m的工艺下该协处理器只有16万门。     

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.     

Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF(2m)

An error tolerant hardware efficient very large scale integration (VLSI) architecture for bit parallel systolic multiplication over dual base, which can be pipelined, is presented. Since this architecture has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The length of the largest delay path and area of this architecture are less compared to the bit parallel systolic multiplication architectures reported earlier. The architecture is implemented using Austria Micro System's 0.35 m CMOS (complementary metal oxide semiconductor) technology. This architecture can also operate over both the dual-base and polynomial base.     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

Scalable Network Architecture for Flow‐Based Traffic Control

Many control schemes have been proposed for flow‐level traffic control. However, flow‐level traffic control is implemented only in limited areas such as traffic monitoring and traffic control at edge nodes. No clear solution for end‐to‐end architecture has been proposed. Scalability and the lack of a business model are major problems for deploying end‐to‐end flow‐level control architecture. This paper introduces an end‐to‐end transport architecture and a scalable control mechanism to support the various flow‐level QoS requests from applications.     

Low‐Complexity Massive MIMO Detectors Based on Richardson Method

In the uplink transmission of massive (or large‐scale) multi‐input multi‐output (MIMO) systems, large dimensional signal detection and its hardware design are challenging issues owing to the high computational complexity. In this paper, we propose low‐complexity hardware architectures of Richardson iterative method‐based massive MIMO detectors. We present two types of massive MIMO detectors, directly mapped (type1) and reformulated (type2) Richardson iterative methods. In the proposed Richardson method (type2), the matrix‐by‐matrix multiplications are reformulated to matrix‐vector multiplications, thus reducing the computational complexity from O(U²) to O(U). Both massive MIMO detectors are implemented using a 65 nm CMOS process and compared in terms of detection performance under different channel conditions (high‐mobility and flat fading channels). The hardware implementation results confirm that the proposed type1 Richardson method‐based detector demonstrates up to 50% power savings over the proposed type2 detector under a flat fading channel. The type2 detector indicates a 37% power savings compared to the type1 under a high‐mobility channel.     

Architecture design,performance analysis and VLSI implementation of a reconfigurable shared buffer for high‐speed switch/router

Modern switches and routers require massive storage space to buffer packets. This becomes more significant as link speed increases and switch size grows. From the memory technology perspective, while DRAM is a good choice to meet capacity requirement, the access time causes problems for high‐speed applications. On the other hand, though SRAM is faster, it is more costly and does not have high storage density. The SRAM/DRAM hybrid architecture provides a good solution to meet both capacity and speed requirements. From the switch design and network traffic perspective, to minimize packet loss, the buffering space allocated for each switch port is normally based on the worst‐case scenario, which is usually huge. However, under normal traffic load conditions, the buffer utilization for such configuration is very low. Therefore, we propose a reconfigurable buffer‐sharing scheme that can dynamically adjust the buffering space for each port according to the traffic patterns and buffer saturation status. The target is to achieve high performance and improve buffer utilization, while not posing much constraint on the buffer speed. In this paper, we study the performance of the proposed buffer‐sharing scheme by both a numerical model and extensive simulations under uniform and non‐uniform traffic conditions. We also present the architecture design and VLSI implementation of the proposed reconfigurable shared buffer using the 0.18 µm CMOS technology. Our results manifest that the proposed architecture can always achieve high performance and provide much flexibility for the high‐speed packet switches to adapt to various traffic patterns. Furthermore, it can be easily integrated into the functionality of port controllers of modern switches and routers. Copyright © 2008 John Wiley & Sons, Ltd.     

Low power & mobile hardware accelerators for deep convolutional neural networks

This article provides a comprehensive review of recent developments in the field of computational hardware for mobile low power machine learning hardware accelerators. The article provides an introduction to neural networks, convolutional neural networks and details recent developments in state of the art deep convolutional neural networks. The key considerations in the design of low power hardware accelerators are discussed with reference to a conceptual system. Strategies for reducing the energy cost of memory access and computation in state of the art hardware accelerators are detailed. This includes techniques such as dataflow, reduced precision, model compression and sparsity. Recent reported digital mobile accelerators for deep convolutional neural networks with power consumptions of less than 3.3 W are observed to have 4x-20x better efficiency than the reference GPU accelerator at 16-bit precision, and can achieve 20x-1171x better efficiency at less than 4-bit precision. Efficiency improvements of 20x-1171x over a GPU is observed for reported mobile accelerators with reduced precision.     

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.     

Design and Implementation of 256‐Point Radix‐4 100 Gbit/s FFT Algorithm into FPGA for High‐Speed Applications

The third‐party FFT IP cores available in today's markets do not provide the desired speed demands for optical communication. This study deals with the design and implementation of a 256‐point Radix‐4 100 Gbit/s FFT, where computational steps are reconsidered and optimized for high‐speed applications, such as radar and fiber optics. Alternative methods for FFT implementation are investigated and Radix‐4 is decided to be the optimal solution for our fully parallel FPGA application. The algorithms that we will implement during the development phase are to be tested on a Xilinx Virtex‐6 FPGA platform. The proposed FFT core has a fully parallel architecture with a latency of nine clocks, and the target clock rate is 312.5 MHz.     

A probabilistic‐based approach for direction‐of‐arrival estimation and localization of multiple sources

This article contributes to science at two points. The first contribution is at a point of introducing a novel direction‐of‐arrival (DOA) estimation method which based on subspaces methods called Probabilistic Estimation of Several Signals (PRESS). The PRESS method provides higher resolution and DOA accuracy than current models. Second contribution of the article is at a point of localizing the unknown signal source. The process of localization achieved by using DOA information for the first time. The importance of localization exists in a large area of engineering applications. The aim is to determine the location of multiple sources by using PRESS with minimum effort of computation. We used the maximum probabilistic process in this study. Initially, all the signals are collected by the array of sensors and accurately identified using the proposed algorithm. The receiver at the best in test estimates the source location using only the knowledge of the geographical latitude and longitude values of the array of sensors. Several test points with an accurately calculated angle of arrival enable us to draw linear lines towards the transmitter. The transmitter location can be accurately identified with the line of interceptions. Simulation and numerical results show the outstanding performance of both the DOA estimation method and transmitter localization approach compared with many classical and new DOA estimation methods. The PRESS localization method first tested at 19°, 26°, and 35° with an signal‐to‐noise ratio (SNR) value of ‐5 dB. The PRESS method produced results with an extremely low bias of 0 and 0.00080°. The simulation tests are repeated and produced results with zero bias, which give the exact location of the unknown source.     

Combined ML and QR Detection Algorithm for MIMO‐OFDM Systems with Perfect ChanneI State Information

An effective signal detection algorithm with low complexity is presented for multiple‐input multiple‐output orthogonal frequency division multiplexing systems. The proposed technique, QR‐MLD, combines the conventional maximum likelihood detection (MLD) algorithm and the QR algorithm, resulting in much lower complexity compared to MLD. The proposed technique is compared with a similar algorithm, showing that the complexity of the proposed technique with T=1 is a 95% improvement over that of MLD, at the expense of about a 2‐dB signal‐to‐noise‐ratio (SNR) degradation for a bit error rate (BER) of 10⁻³. Additionally, with T=2, the proposed technique reduces the complexity by 73% for multiplications and 80% for additions and enhances the SNR performance about 1 dB for a BER of 10⁻³.     

Design and implementation of a scalable switch architecture for efficient high‐speed data multicasting

This paper presents the design and implementation of a new scalable cell‐based multicast switch fabric for broadband communications. Using distributed control and modular design, the multicast balanced gamma switch features a scalable, high performance architecture for unicast, multicast and combined traffic under both uniform and non‐uniform traffic conditions. The important design characteristic of the switch is that a distributed cell replication function for multicast cells is integrated into the functionality of the switch element with the self‐routing and contention resolution functions. Thus, no dedicated copy network is required. In the paper, we discuss in detail the design issues associated with the multicast functionality of the switch using 0.18 µm CMOS technology and discuss the scalability of the switch in terms of architectural, implementation, and performance scalability. Synthesized results are provided for measures of circuit complexity and timing. Copyright © 2006 John Wiley & Sons, Ltd.     

Multiuser two‐way relay processing and power control methods for cognitive radio networks

We consider a cognitive radio system where a secondary network shares the spectrum band with a primary network. Aiming at improving the frequency efficiency of the secondary network, we set a multiantenna relay station in the secondary network to perform two‐way relaying. Three linear processing schemes at the relay station based on zero forcing, zero forcing‐maximum ratio transmission, and minimum mean square error criteria are derived to guarantee the quality of service of primary users and to suppress the intrapair and interpair interference among secondary users (SUs). In addition, the transmit power of SUs is optimized to maximize the sum rate of SUs and to limit the interference brought to PUs. Numerical results show that the proposed multiuser two‐way relay processing schemes and the optimal power control policies can efficiently limit the interference caused by the secondary network to primary users, and the sum rate of SUs can also be greatly improved. Copyright © 2011 John Wiley & Sons, Ltd.     

New explicit current/voltage equation for p‐i‐n solar cells including interface potential drops and drift/diffusion transport

Analytical modeling of p‐i‐n solar cells constitutes a practical tool to extract material and device parameters from fits to experimental data, and to establish optimization criteria. This paper proposes a model for p‐i‐n solar cells based on a new approximation, which estimates the electric field taking into account interface potential drops at the intrinsic‐to‐doped interfaces. This leads to a closed‐form current/voltage equation that shows very good agreement with device simulations, revealing that the inclusion of the interface potential drops constitutes a major correction to the classical uniform‐field approach. Furthermore, the model is able to fit experimental current/voltage curves of efficient nanocrystalline Si and microcrystalline Si p‐i‐n solar cells under illumination and in the dark, obtaining material parameters such as mobility‐lifetime product, built‐in voltage, or surface recombination velocity. Copyright © 2012 John Wiley & Sons, Ltd.     

Reduced‐rank space–time adaptive interference suppression for navigation systems based on QR decomposition and approximations of basis functions

This paper presents a novel reduced‐rank space–time adaptive processing (STAP) algorithm for interference suppression in global positioning system (GPS) receivers with low computational complexity for protection against the multipath and jamming interferences. The proposed STAP algorithm is based on the least‐squares (LS) criterion to jointly optimize a projection matrix, which is used for dimensionality reduction, and the reduced‐rank filter. The main novelties are the design of the projection matrix based on approximations of basis functions, the pattern matching between the projection matrix and the received data, and the derivation of a QR decomposition‐based reduced‐rank recursive LS algorithm for practical implementations. The proposed scheme works on an instantaneous basis, i.e. at each time instant, the most suitable pattern and the rank of the projection matrix are selected to reduce the dimensionality of the received data aiming at minimizing the squared error, while using an improved search algorithm to save the effort in finding the best projection matrix. Simulation results in a GPS system show that compared to existing reduced‐rank and full‐rank algorithms, the proposed algorithm has a much lower computational complexity, and remarkably better performance for interference suppression. Copyright © 2011 John Wiley & Sons, Ltd.