Error Detecting Dual Basis Bit Parallel Systolic Multiplication Architecture over GF（2^m）

An error tolerant hardware efficient verylarge scale integration （VLSI） architecture for bitparallel systolic multiplication over dual base, which canbe pipelined, is presented. Since this architecture has thefeatures of regularity, modularity and unidirectionaldata flow, this structure is well suited to VLSIimplementations. The length of the largest delay pathand area of this architecture are less compared to the bitparallel systolic multiplication architectures reportedearlier. The architecture is implemented using Austria Micro System＇s 0.35 μm CMOS （complementary metaloxide semiconductor） technology. This architecture canalso operate over both the dual-base and polynomialbase.     

Novel direct designs for 3-input XOR function for low-power and high-speed applications

Novel direct designs for 3-input exclusive-OR (XOR) function at transistor level are proposed in this article. These designs are appropriate for low-power and high-speed applications. The critical path of the presented designs consists of only two pass-transistors, which causes low propagation delay. Neither complementary inputs, nor V _DD and ground exist in the basic structure of these designs. The proposed designs have low dynamic and short-circuit power consumptions and their internal nodes dissipate negligible leakage power, which leads to low average power consumption. Some effective approaches are presented for improving the performance, voltage levels, and the driving capability and lowering the number of transistors of the basic structure of the designs. All of the proposed designs and several classical and state-of-the-art 3-input XOR circuits are simulated in a realistic condition using HSPICE with 90 nm CMOS technology at six supply voltages, ranging from 1.3 V down to 0.8 V. The simulation results demonstrate that the proposed circuits are superior in terms of speed, power consumption and power-delay product (PDP) with respect to other designs.     

Scalable Network Architecture for Flow‐Based Traffic Control

Many control schemes have been proposed for flow‐level traffic control. However, flow‐level traffic control is implemented only in limited areas such as traffic monitoring and traffic control at edge nodes. No clear solution for end‐to‐end architecture has been proposed. Scalability and the lack of a business model are major problems for deploying end‐to‐end flow‐level control architecture. This paper introduces an end‐to‐end transport architecture and a scalable control mechanism to support the various flow‐level QoS requests from applications.     

A new and efficient approach for estimating the accurate time-domain response of single and capacitive coupled distributed RC interconnects

This paper describes a novel yet highly efficient approach for estimating the time-domain response of capacitive coupled distributed RC interconnects. By using this method, the voltage signal at any particular point in such wires can be accurately and quickly obtained with very low computational cost. The proposed model exhibits a very good agreement with HSPICE simulations with worst-case error less than 3% and can be readily implemented in CAD analysis tools. This paper also presents an efficient model to estimate the capacitive crosstalk in high-speed very large scale integration (VLSI) circuits. Experimental results show that the maximum error of our peak noise predictions is less than 2.5%. In addition, this work presents an efficient artificial neural network (ANN)-based technique for modeling the time-domain response of interconnects and crosstalk noise. While existing fast noise estimation metrics may overestimate or underestimate the coupling noise, the simulation results demonstrate the ability of this approach to successfully predict coupling noise with a very good accuracy as compared to HSPICE in modest CPU times. Thereby, the proposed models and techniques can be used to predict the signal integrity for designing high-speed and high-density VLSI circuits.     

Combined ML and QR Detection Algorithm for MIMO‐OFDM Systems with Perfect ChanneI State Information

An effective signal detection algorithm with low complexity is presented for multiple‐input multiple‐output orthogonal frequency division multiplexing systems. The proposed technique, QR‐MLD, combines the conventional maximum likelihood detection (MLD) algorithm and the QR algorithm, resulting in much lower complexity compared to MLD. The proposed technique is compared with a similar algorithm, showing that the complexity of the proposed technique with T=1 is a 95% improvement over that of MLD, at the expense of about a 2‐dB signal‐to‐noise‐ratio (SNR) degradation for a bit error rate (BER) of 10⁻³. Additionally, with T=2, the proposed technique reduces the complexity by 73% for multiplications and 80% for additions and enhances the SNR performance about 1 dB for a BER of 10⁻³.