Broadband RF stage architecture for software-defined radio inhandheld terminal applications

Broadband RF is a general-purpose common RF stage for every standard within a set of RF bands. The RF stage architecture presented in this article is suitable for software-defined radios. This article first defines the conceptual scheme of a handheld software defined radio (SDR) terminal, and then describes how the direct conversion principle is applied to the SDR. The discussion focuses on receiver hardware implementation and systematic control     

基于软件无线电的中短波接收机设计

目前广播系统正由模拟体制向数字化体制过渡,数字版权管理（DRM,Digital Radio Mondiale）系统就是针对30 MHz以下频段的数字广播标准。作为软件无线电的核心技术之一,数字接收机技术得到了越来越普遍的应用。介绍了一种基于软件无线电的中短波接收机的硬件系统结构,这种软件无线电接收机结构可以同时解码音频和数据流,兼容目前的模拟调幅广播和数字调幅广播标准。重点讨论了电调滤波器的设计,最后使用EDA软件进行仿真,并给出了仿真结果。     

Compensation of RF impairment in multi-band receiver based on RF sub-sampling

This paper is studied about multi-band receiver using sub-sampling and time division multiplexing (TDM) techniques. Software defined radio (SDR) has a goal that places the analog to digital converter (ADC) as near the antenna as possible. But current technique actually cannot process ADC about radio frequency (RF) band signals. So one method is being studied that samples RF band signals to intermediate frequency (IF) band. As one of the ways, sub-sampling technique can convert signals from RF band to IF band without oscillator. If sub-sampling technique is used, over 2 bands can convert signals from RF band to IF band. However, due to the filter performance in RF band, it is possible that interference is generated between signals that are converted to low frequency band. And the problem degrades performance. In this paper, we propose one method that uses TDM technique as a solution to avoid interference between signals. By processing TDM and sub-sampling at the same time, the method can get signals without large changes from the conventional structures.     

A high sensitivity and wide dynamic range zero-IF RF receiver for cognitive radio application

This paper presents an RF receiver of zero-Intermediate Frequency (IF) architecture for Cognitive Radio (CR) communication systems. Zero-IF architecture reduce the image reject filter and IF filter, so it is excellent in low cost, compact volume, and low power dissipation. The receiver employs three digital attenuator and a high gain, high linearity low noise amplifier to achieve wide dynamic range of 70 dB and high receiving sensitivity of −81 dBm. A fully balanced I/Q demodulator and a differential Local Oscillator (LO) chips are used to minimize the negative effects caused by second-order distortion and LO leakage. In order to select an 8 MHz-channel from 14 continuous ones located in UHF band (694–806 MHz) accurately, approach of channel selectivity circuits is proposed. The RF receiver has been designed, fabricated, and test. The measured result shows that the noise figure is 3.4 dB, and the error vector magnitude is 7.5% when the input power is −81 dBm.     

Design of Dual‐Mode Digital Down Converter for WCDMA and cdma2000

We propose an efficient digital IF down converter architecture for dual‐mode WCDMA/cdma2000 based on the concept of software defined radio. Multi‐rate digital filters and fractional frequency conversion techniques are adopted to implement the front end of a dual‐mode receiver for WCDMA and cdma2000. A sub‐sampled digital IF stage was proposed to support both WCDMA and cdma2000 while lowering the sampling frequency. Use of a CIC filter and ISOP filter combined with proper arrangement of multi‐rate filters and common filter blocks resulted in optimized hardware implementation of the front end block in 292k logic gates.     

A Disruptive Receiver Architecture Dedicated to Software-Defined Radio

The next generation of mobile terminals is faced with the emergence of the software-defined radio (SDR) concept. The communication devices tend to provide various wireless services through a multi-functional, multi-mode and multi-standard terminal. The SDR concept aims at designing a re-configurable radio architecture accepting all cellular or noncellular standards working in the 0-5-GHz frequency range. Some technical challenges have to be solved in order to address this concept. Working in the digital domain may be a solution but the analog-to-digital conversion cannot be done at Radio Frequencies, at an acceptable resolution and at an acceptable level of power consumption. The idea proposed here was to interface an analog pre-processing circuit between the antenna and a digital signal processor to pre-condition the RF signal. It uses the principle of a fast Fourier transform to carry out basic functions with high accuracy in a low-cost technology like CMOS. This paper presents the design and the behavioral simulations of this analog discrete-time device which gives the hardware flexibility required for a cognitive radio component.     

一种宽频段软件无线电平台的设计与实现

针对现代战术通信中背负式或手持电台体积小、功耗小和对不同频段信号兼容性好的应用需求,结合零中频采样和射频直接采样技术,设计了一种可覆盖较宽通信频段的软件无线电平台。通过将模数和数模转换模块与数字信号处理模块集成在一块印制板上,大大减小了该平台的体积。通过平台软件架构的设计,保证不同通信波形体制的实现。最后,通过调频(Frequency Modulation, FM)和正交相移键控(Quadrature Phase Shift Keying, QPSK)波形测试验证了该平台整个频段信号通信性能良好。该平台具有通信频道宽、结构简单、可靠性高等优点,满足小型化、低功耗和对不同频段信号具有高兼容性的使用需求。     

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.     

RF beamforming for MIMO cognitive user

Using Multiple Input Multiple Output (MIMO) architecture in cognitive radio (CR) secondary users improves the system performance in terms of interference cancellation and data rate enhancement but at the expense of adding complexity and cost. A solution to reduce this complexity is employing radio frequency (RF) beamforming networks at the transmitter/receiver front-ends. In this paper, we consider a MIMO secondary user equipped with such RF beamforming network. Moreover, we find the transmit/receive optimum RF beamforming network for a MIMO spatial multiplexing system. We evaluate the performance of the optimally designed RF beamforming technique over a Rician channel via computer simulations. The simulation results are assessed for different RF beamforming structures and the number of primary transmitters which cause interference on the secondary receiver.     

基于Simulink的单比特数字接收机设计

瞬时测频接收机拥有大工作带宽以及高截获概率,是电子战系统的一个重要组成部分,然而它无法对同时到达的多个信号进行测频。单比特接收机是解决这个问题的一种方法,由于它采用了很低的ADC采样位数,以及直接射频采样能力和独特的测频算法,使它具有大带宽、实时测量双音信号频率信息的优异性能。相比于典型的数字接收机,自身结构也得到了极大的简化。提出了一种单比特接收机硬件设计架构,并基于Simulink工具搭建了模型,分析了这种设计的性能。该模型具有高度的灵活性,对于单比特接收机的设计与系统实现具有一定的指导意义。     

Design of a 0.18 μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier (LNA),a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage.Also,a re-designed wideband double balance mixer is implemented in the down conversion stage,which provides better gain,noise figure and linearity performances.Using a TSMC 0.18μm 1P4M RF CMOS process,a compact 1.27 GHz/1.575 GHz dualband GNSS frontend is realized in the proposed low-IF topology.The measurements exhibit the gains of 45 dB and 43 dB,and noise figures are controlled at 3.35 dB and 3.9 dB of the two frequency bands,respectively.The frontend model consumes about 11.8-13.5 mA current on a 1.8 V power supply.The core occupies 1.91 × 0.53 mm2 while the total die area with ESD is 2.45 × 2.36 mm2.     

一种宽带中频数字化处理平台

为解决软件无线电领域无法实时处理宽带中频信号的问题,研究了软件无线电中频数字化处理技术的基础理论和关键技术。设计实现了基于CPCI架构的中频数字化处理平台,介绍该平台的设计原理,并给出平台所用器件的原理框图。借助摩托罗拉超短波电台调制信号,通过该平台上实现的数字下变频和基于正交解调的FM算法对该信号的成功处理,验证了该设计平台能够实时处理宽带中频信号。     

自适应前馈功放中基于软件无线电的数字接收

对自适应前馈功率放大器中基于软件无线电的数字中频接收技术进行了讨论,对基于软件无线电的自适应控制模块中的数字中频接收进行优化设计,并给出了具体的设计方案及实验结果.     

机载通信导航识别系统综合检测设备设计与实现

针对机载通信导航识别(Communication,Navigation and Identification,CNI)系统对轻小型地面保障设备提出的更高要求,在分析CNI系统信号特征对地面保障设备硬件平台需求的基础上,通过对比超外差、射频低通采样和射频带通采样等架构的特点,搭建了一种全新的基于软件无线电的综合检测设备通用平台架构,并给出了硬件平台总体设计和主要模块设计,同时分析了CNI检测部分功能信号的实现.实际工程应用证明,在配置同样检测功能的情况下,该设备在重量、体积、功耗等方面的优势明显,可为其他检测设备设计提供借鉴.     

A Digital Receiver Architecture for Bluetooth in 0.25- μm CMOS Technology and Beyond

A digital receiver architecture for short-range communications systems like Bluetooth is presented. The architecture is tailored to a highly integrated Bluetooth single-chip integrated circuit (IC) and can easily be adapted to other communications systems using a Gaussian frequency-shift keying (GFSK ) modulation scheme. The single-chip IC integrates the complete digital baseband and radio frequency (RF) functionality on a single die and is realized in a 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology targeted for cost efficiency. The superior performance of this digital receiver architecture compared to the state-of-the-art short-range communications receivers is shown. Simulation and measurement results are presented showing a receiver sensitivity of 87 dBm and excellent co-channel and adjacent channel interference performance.     

一种P/L频段高度综合化航空平台的设计

为进一步提升航空平台综合化程度,设计了一种用于航空平台的P/L频段功能高度综合化硬件平台方案。该方案通过射频直接采集2 GHz以下的低频射频信号,在数字域分离出探测、通信、导航、识别以及无源侦察等功能所需基带I/Q信号,最后通过软件完成各种信号的功能处理,实现了对探测、通信、导航、识别以及无源侦察等功能共信道和共信号预处理的高度综合设计。硬件实现验证了该方案能够有效降低硬件系统设计的成本和复杂性,降低系统功耗,有力推进了软件无线电在航空平台综合化中的应用。     

基于软件无线电的伪卫星接收机的设计与实现

提出了基于软件无线电的伪卫星接收机的数学模型和数字平台实现的两种方案：DDC＋DSP方案和FPGA＋DSP方案。通过对这两种方案的比较,得出在伪卫星接收机数字平台的设计中应采用FPGA＋DSP方案。     

Design of a 0.18μm CMOS multi-band compatible low power GNSS receiver RF frontend

This paper presents the design and implementation of a fully integrated multi-band RF receiver frontend for GNSS applications on L-band.A single RF signal channel with a low-IF architecture is adopted for multi-band operation on the RF section,which mainly consists of a low noise amplifier(LNA),a down-converter,polyphase filters and summing circuits.An improved cascode source degenerated LNA with a multi-band shared off-chip matching network and band switches is implemented in the first amplifying stage....     

基于AD6644和AD6620的中频信号处理平台的设计

构建了一种基于高速采样器件AD6644、可鳊程数字下变频器AD6620和高性能DSP开发板的中频信号处理平台,详细分析了它的硬件设计和软件设计。该平台具有很强的通用性和灵活性,为软件无线电技术的研究提供了一个理想的实验平台。     

A multi-mode multi-band RF receiver front-end for a TD-SCDMA/LTE/LTE-advanced in 0.18-μm CMOS process

正A fully integrated multi-mode multi-band directed-conversion radio frequency(RF) receiver front-end for a TD-SCDMA/LTE/LTE-advanced is presented.The front-end employs direct-conversion design,and consists of two differential tunable low noise amplifiers(LNA),a quadrature mixer,and two intermediate frequency(IF) amplifiers.The two independent tunable LNAs are used to cover all the four frequency bands,achieving sufficient low noise and high gain performance with low power consumption.Switched capacitor arrays perform a resonant frequency point calibration for the LNAs.The two LNAs are combined at the driver stage of the mixer,which employs a folded double balanced Gilbert structure,and utilizes PMOS transistors as local oscillator(LO) switches to reduce flicker noise.The front-end has three gain modes to obtain a higher dynamic range.Frequency band selection and mode of configuration is realized by an on-chip serial peripheral interface(SPI) module.The frontend is fabricated in a TSMC 0.18-μm RF CMOS process and occupies an area of 1.3 mm~2.The measured doublesideband (DSB) noise figure is below 3.5 dB and the conversion gain is over 43 dB at all of the frequency bands. The total current consumption is 31 mA from a 1.8-V supply.