MOS器件的质子总剂量效应

介绍了几种加固和非加固MOS电路的质子辐照总剂量效应实验,质子束的能量为9、7、5、2MeV.实验结果表明,在相同的吸收剂量下,MOS器件累积电离辐射损伤与质子能量成正比.还给出了栅极偏压对器件质子辐射损伤的影响,结果认为,对于NMOSFET,不论是加固器件,还是非加固器件,在+5V的栅压偏置下,器件的辐射损伤比0V栅压下的损伤严重,对于加固器件,辐射感生界面态的密度也较高;而加固型PMOSFET,在0V的栅压下,辐射损伤比-5V下严重,且界面态的密度高.     

MOS器件在不同源辐照下总剂量效应的异同性研究

介绍了加固型CMOS电路在^60Co—γ射线源、10MeV以下的质子、1～2MeV的电子等辐射源辐照下的总剂量效应实验。结果表明，在相同吸收剂量和 5V栅压的偏置条件下，1MeV的电子与^60Co—γ射线源对器件的损伤相当。质子与^60Co-γ射线源对器件的辐射损伤，在不同的栅压偏置下有不同的结果。 5V栅压下，能量在10MeV以下的质子对器件的损伤小于^60Co-γ射线源，且质子对器件的辐射损伤随着质子能量的增加而增加；在零栅压的偏置条件下，质子对器件的损伤与^60Co-γ射线源对器件的损伤相当。通过对实验结果的分析认为，用实验室常用的^60Co-γ射线源可以模拟MOS器件在质子、电子辐射环境下的最劣总剂量效应。     

超薄栅MOS器件热载流子应力下SILC的产生机制

通过测量界面陷阱的产生,研究了超薄栅n MOS和p MOS器件在热载流子应力下的应力感应漏电流( SIL C) .在实验结果的基础上,发现对于不同器件类型( n沟和p沟)、不同沟道长度( 1、0 .5、0 .2 75和0 .13 5 μm)、不同栅氧化层厚度( 4和2 .5 nm) ,热载流子应力后的SIL C产生和界面陷阱产生之间均存在线性关系.这些实验证据表明MOS器件减薄后,SIL C的产生与界面陷阱关系非常密切     

HCl氧化物MOS结构质子辐照诱导的界面陷阱效应

用微分电容法研究质子辐照HCl氧化物铝栅MOS结构诱导的界面陷阱,栅氧化层在1 160℃很干燥的、含0～10％HCl的气氛中热生长而成,质子辐照能量为120～300keV,注入总剂量范围为8×10~(13)～1×10~(16)p/cm~2。结果表明,辐照诱导的界面陷阱能级密度随质子能量、剂量增加而增加。然而,氧化层中掺入6％HCl时,辐照诱导的界面陷阱明显减少。这样,已能有效地改变MOS器件的抗辐照性能。实验结果可用H~+二级过程解释。     

MOS电容的热载流子损伤及其与电离辐射损伤的关系

通过对国产加固 N型 MOS电容进行衬底热电子高场注入 ( SHE)及 γ总剂量辐照实验 ,特别是进行总剂量辐射损伤后的热载流子损伤叠加实验 ,从微观氧化物电荷、界面态的感生变化及其界面态的能量分布变化等角度研究比较了 MOS结构热载流子损伤特性及与电离辐射损伤的关系。     

超薄HfN界面层对HfO_2栅介质Ge pMOSFET电性能的改进

通过在高k介质和Ge表面引入一层超薄HfN界面层,实验制备了HfO2/HfON叠层栅介质Ge MOS器件。与没有界面层的样品相比,HfO2/HfON叠层栅介质MOSFET表现出低的界面态密度、低的栅极漏电和高有效迁移率。因此利用HfON作为Ge MOS器件的界面钝化层对于获得小的等效氧化物厚度和高的high-k/Ge界面质量有着重要的意义。     

零偏源MOS结构的栅电荷弛豫机制及近少子带边界面态分布的瞬态谱测定

讨论了小方栅脉冲下零偏置源MOS结构栅电荷弛豫的机制.证明了当费米能级接近少子带边时,引起栅电荷弛豫的起因将由界面态俘获发射电荷的过程变成受其延迟的表面少子扩散漂移过程.对后一过程进行理论分析导出的栅电荷公式与实验取得了一致.在此基础上提出了根据栅电荷波形参数确定栅电荷变化量中界面态贡献的大小,进而测定近少子带边一侧界面态密度的测量原理.获得了覆盖的能量范围一直延伸到距少子带边 0.05 eV处的界面态密度能量分布.在不同类型样品中获得了具有共同特征的结果.     

施主型界面态引起槽栅PMOSFET性能退化的特征

基于流体动力学能量输运模型,对沟道杂质浓度不同的深亚微米槽栅和平面PMOSFET中施主型界面态引起的器件特性的退化进行了研究.研究结果表明同样浓度的界面态密度在槽栅器件中引起的器件特性的漂移远大于平面器件,且电子施主界面态密度对器件特性的影响远大于空穴界面态.特别是沟道杂质浓度不同,界面态引起的器件特性的退化不同.沟道掺杂浓度提高,同样的界面态密度造成的漏极特性漂移增大.     

施主型界面态引起槽栅PMOSFET性能退化的特征

基于流体动力学能量输运模型 ,对沟道杂质浓度不同的深亚微米槽栅和平面 PMOSFET中施主型界面态引起的器件特性的退化进行了研究 .研究结果表明同样浓度的界面态密度在槽栅器件中引起的器件特性的漂移远大于平面器件 ,且电子施主界面态密度对器件特性的影响远大于空穴界面态 .特别是沟道杂质浓度不同 ,界面态引起的器件特性的退化不同 .沟道掺杂浓度提高 ,同样的界面态密度造成的漏极特性漂移增大 .     

对称矩形环栅NMOS器件的建模与验证

介绍了一种对称矩形环栅NMOS器件结构,并对其等效宽长比的计算模型和总剂量效应加固性能进行了研究。通过区域划分、保角变换等方法,对该对称矩形环栅NMOS器件进行建模,给出了其等效宽长比的计算模型。在0.18 μm BCD工艺下进行流片,并对不同尺寸下直栅MOS器件和环栅MOS器件进行辐照对比测试。测试结果表明,对称矩形环栅NMOS器件的等效宽长比计算模型的计算误差可低至5%。辐照总剂量10 kGy条件下,对称矩形环栅NMOS器件的关态泄漏电流仍可维持在一个很低的量级,表现出良好的总剂量效应加固性能。     

SiO2/4H-SiC界面氮化退火

通过1 300℃高温干氧热氧化法在n型4H-SiC外延片上生长了厚度为60 nm的SiO2栅氧化层.为了开发适合于生长低界面态密度和高沟道载流子迁移率的SiC MOSFET器件产品的栅极氧化层退火条件,研究了不同退火条件下的SiO2/SiC界面电学特性参数.制作了MOS电容和横向MOSFET器件,通过表征SiO2栅氧化层C-V特性和MOSFET器件I-V特性,提取平带电压、C-V磁滞电压、SiO2/SiC界面态密度和载流子沟道迁移率等电学参数.实验结果表明,干氧氧化形成SiO2栅氧化层后,在1 300℃通入N2退火30 min,随后在相同温度下进行NO退火120 min,为最佳栅极氧化层退火条件,此时,SiO2/SiC界面态密度能够降低至2.07×1012 cm-2·eV-1@0.2 eV,SiC MOSFET沟道载流子迁移率达到17 cm2·V-1·s-1.     

Gate Bias Effect on the 60-MeV Proton Irradiation Response of 65-nm CMOS nMOSFETs

The response to a 60-MeV proton irradiation of nMOSFETs fabricated in a 65-nm CMOS technology using a 1.4-nm gate oxide is reported. A strong dependence on the gate bias during the exposure is found. Whereas no degradation is observed for 0-V bias, soft or hard breakdown occurs under normal operational conditions, i.e., 1.2 V on the gate. Furthermore, it is noted that the breakdown happens preferentially at the source–gate junctions. Possible mechanisms are discussed, whereby at the moment, it is believed that a synergy between the radiation damage in the thin gate oxide and the gate current flow under constant voltage may explain the observations. Furthermore, it is shown that the tendency for a breakdown at the source–gate junction is correlated with a higher source–gate current prior to irradiation. This could point to some processing-induced prerad local degradation of the gate oxide, which develops into a breakdown leakage site under biased 60-MeV proton irradiation.     

A new AC technique for accurate determination of channel charge and mobility in very thin gate MOSFET's

A new method is described for determining the channel charge and mobility of a MOS transistor as a function of gate bias from the ac admittance measurements. The admittance of the conduction channel of the MOSFET is derived from a transmission line model. The peaks of theG/omegaversus ω curves are used to deduce gate-channel capacitance and mobility. The mobile carrier density and mobility in very thin-oxide MOSFET's can be measured more accurately using this ac method, since a zero lateral field and a uniform mobile charge distribution along the channel is maintained with zero drain-source voltage and interface trap effects are reduced by using high test frequencies. Measured data on the electron mobility versus gate voltage are presented for 90-A gate dielectric MOS transistors.     

NMOSFET器件不同源、不同γ剂量率辐射损伤比较

利用不同剂量率γ射线、低能(小于9MeV)质子和1MeV电子对CC4007RH、CC4011、LC54HC04RH NMOSFET进行了辐照实验,结果表明,在＋5V偏置条件下,9MeV以下质子造成的损伤总是小于⁶⁰Co,而且质子能量越低,损伤越小;对于同等的吸收剂量,1MeV电子和⁶⁰Co造成的损伤差别不大;在高剂量率γ射线辐射下,氧化物陷阱电荷是导致器件失效的主要原因,在接近空间低剂量率辐射环境下,LC54HC04RH电路失效的主要原因是辐射感生界面态陷阱电荷,而CC4007RH器件则是氧化物陷阱电荷.     

Effects of electric fields on annealing of radiation damage in MOSFET's

Radiation damage inp-channel MOS devices by 1.5 MeV electrons has been studied by thermal annealing in conjunction with electric fields between the metallic gate and the substrate. Both positive and negative gate biases retard the process of annealing. Annealing with negative gate bias reveals 1) that during thermal annealing the majority of the electrons that recombine with the positive charge in the oxide originate from the conduction band of the silicon, and 2) that during irradiation a great number of ionized electrons that remain in the oxide do not recombine with the holes, but are trapped in weakly bound states. The effect of positive bias on annealing of radiation damage is obscured by the positive charge induced due to positive bias-temperature treatment alone. No effect of drain-to-source potential on annealing has been observed.     

Improving the reverse recovery of power mosfet integral diodes by electron irradiation

This paper demonstrates that controlled electron irradiation of silicon power MOSFET devices can be used significantly improve the reverse recovery characteristics of their integral reverse conducting diodes without adversely affecting the MOSFET characteristics. By using 3 MeV electron irradiation at room temperature it was found that the reverse recovery charge in the integral diode could be continuously reduced in a well controlled manner from over 500 nC to less than 100 nC without any significant increase in the forward voltage drop of the integral diode under typical operating peak currents. The reverse recovery time was also observed to decrease from 3 microseconds to less than 200 nsec when the radiation dose was increased from 0 to 16 Megarads. The damage produced in gate oxide of the MOSFET due to the electron radiation damage was found to cause an undersirable decrease in the gate threshold voltage. This resulted in excessive channel leakage current flow in the MOSFET at zero gate bias. It was found that this channel leakage current was substantially reduced by annealling the devices at 140°C without influencing the integral diode reverse recovery speed. Thus, the electron irradiation technique was found to be effective in controlling the integral diode reverse recovery characteristics without any degradation of the power MOSFET characteristics.     

MOS栅氧的界面特性和辐照特性研究

通过交流电导法,对经过不同时间N₂O快速热处理(RTP)的MOS电容进行界面特性和辐照特性研究。通过电导电压曲线,分析N₂O RTP对Si-SiO₂界面陷阱电荷和氧化物陷阱电荷造成的影响。结论表明,MOS电容的Si-SiO₂界面陷阱密度随N₂O快速热处理时间先增加再降低;零偏压总剂量辐照使氧化层陷阱电荷显著增加,而Si-SiO₂界面陷阱电荷轻微减少。     

Empirically Verified Thermodynamic Model of Gate Capacitance and Threshold Voltage of Nanoelectronic MOS Devices With Applications to HfO2 and ZrO2 Gate Insulators

A thermodynamic variational model derived by minimizing the Helmholtz free energy of the MOS device is presented. The model incorporates an anisotropic permittivity tensor and accommodates a correction for quantum-mechanical charge confinement at the dielectric/substrate interface. The energy associated with the fringe field that is adjacent to the oxide is of critical importance in the behavior of small devices. This feature is explicitly included in our model. The model is verified using empirical and technology-computer-aided-design-generated capacitance-voltage data obtained on MOS devices with ZrO₂, HfO₂, and SiO₂ gate insulators. The model includes considerations for an interfacial low-k interface layer between the silicon substrate and the high-k dielectric. This consideration enables the estimation of the equivalent oxide thickness. The significance of sidewall capacitance effects is apparent in our modeling of the threshold voltage (V_th) for MOS capacitors with effective channel length at 30 nm and below. In these devices, a variation in high-k permittivity produces large differences in V_th. This effect is also observed in the variance of V_th, due to dopant fluctuation under the gate.     

Radiation resistance of Al2O3MOS devices

Integrated circuits employing MOS devices will play a vital role in tomorrow's civilian and military electronics if their degradation in a radiation environment can be eliminated. One possible approach toward alleviating radiation effects in MOS devices is to use a material with a defect structure that does not allow predominant trapping of either holes or electrons as a gate insulator. This has been done by constructing MOS devices with plasma-grown aluminum oxide. The Al2O3films are formed by first depositing aluminum on freshly cleaned and properly prepared silicon wafers. Subsequently this aluminum is oxidized in an oxygen plasma and device fabrication is then completed. The devices have excellent characteristics and stability, and their fabrication is not restricted by the conditions of the ultra-clean procedures necessary for SiO2-Si devices. Exposure to 1-MeV electron bombardment at various fluence levels and bombardment-bias conditions shows that these structures possess remarkable radiation resistance. Up to a fluence of 1 × 10¹³e/cm², under positive or negative bias, no oxide charge buildup or interface state generation is detectable. Above that fluence, only small shifts are observed. This indicates that an order of magnitude improvement in device hardening can be achieved by the use of this material.