On supporting rapid prototyping of embedded systems with reconfigurable architectures

Reducing time-to-market while improving product quality is a big challenge. This paper proposes a software-supported framework for rapid prototyping that offers a concurrent fast hardware/software system-level design. The introduced framework enables the constant evaluation and verification of the prototype under development, while it provides automatic functionality mapping to hardware via High-Level Synthesis techniques. We evaluate our framework and its software instantiation with a computer vision algorithm. Based on our experimentation, we show that our approach reduces the development time by almost 64×, it prunes the hardware design space by 34×, while maintaining designs that trade-off high Quality-of-Report on the Pareto frontier.     

Co-synthesis and co-simulation of control-dominated embedded systems

This paper presents a methodology for hardware/software co-design with particular emphasis on the problems related to the concurrent simulation and synthesis of hardware and software parts of the overall system. The proposed approach aims at overcoming the problem of having two separate simulation environments by defining a VHDL-based modeling strategy for software execution, thus enabling the simulation of hardware and software modules within the same VHDL-based CAD framework. The proposed methodology is oriented towards the application field of control-dominated embedded systems implemented onto a single chip.     

RTOS modeling in SystemC for real-time embedded SW simulation: A POSIX model

SystemC is committed to support the requirements for an integrated, HW/SW co-design flow, thus allowing the development of complex, multiprocessing, Systems-on Chip (MpSoC). To make this possible, efficient modeling and simulation methodologies for Real-Time, Embedded (RT/E) SW in SystemC have to be developed, so that the designer can verify and refine the application SW together with the rest of the elements of the platform. Accurate modeling of the application SW requires an accurate model of the RTOS. Nevertheless, low-level, dynamic timing characteristics of the RTOS such as time-slicing, priority-based preemptive scheduling, interrupts and exceptions do not have a direct implementation in SystemC. In this paper, techniques are proposed to accurately model the detailed RTOS functionality on top of the SystemC execution kernel. The model allows timed-simulation and refinement of the RT/E SW code in SystemC. The simulation technology has been applied to the development of a high-level, POSIX simulation library in SystemC. The library allows the designer a fast, sufficiently accurate, timed simulation of the application SW running on top of POSIX. As most current RTOSs support this standard, the library is portable to different development frameworks. The library provides the required infrastructure for a complete, multiprocessing, HW/SW co-simulation environment at different abstraction levels using SystemC.     

Improving thermal conductivity of polymer composites in embedded LEDs systems

Polymer embedding of LEDs increases safety and waterproof levels in LED based lighting systems. The embedding allows for mechanical flexibility of these systems. The increase of polymer thermal conductivity has been a research challenge for decades. Here, we suggest materials for enhancing thermal conductivity in polymer embedded LED systems. We demonstrate that thermally conductive fillers into the polymer matrix to form a composite improved heat transfer from the LEDs to the environment. Non metallic boron nitride with a high intrinsic thermal conductivity is a good candidate. Thermal conductivity of basic polymer PDMS with various filler size and polymer ratios is reported here. Here, an in situ measurement tool to fast evaluate the quality of the composites in LED applications is demonstrated. Future work will focus on further increasing the thermal conductivity of the composites by using different mixtures.     

嵌入式系统的现状及发展前景

从嵌入式系统的含义、特点、开发平台及其工业特征出发,深入阐述了嵌入式计算机技术的发展现状,展望了嵌入式系统产业在我国的广阔发展前景。     

一种ADS、Cadence软件联合仿真的LNA设计方法

为提高无线通信系统的接收灵敏度,低噪声放大器的设计尤为重要.基于Avago公司的高电子迁移率晶体管ATF54143芯片的2.4G～2.5G ISM频段范围低噪声放大器的设计,采用安捷伦公司的ADS软件设计、制作原理图并进行仿真,然后利用Cadence公司的Allegro SPB软件设计并制作原理图和PCB版图,最后将PCB版图导入到安捷伦公司的ADS系列软件中进行联合仿真,反复调整得到的仿真结果显示放大器工作在绝对稳定状态,噪声系数（NF）低于0.7,增益可达15dB.     

Efficient co-simulation framework enhancing system-level power estimation for a platform-based SoC design

This paper proposes a hardware–software (HW-SW) co-simulation framework that provides a unified system-level power estimation platform for analyzing efficiently both the total power consumption of the target SoC and the power profiles of its individual components. The proposed approach employs the trace-based technique that reflects the real-time behavior of the target SoC by applying various operation scenarios to the high-level model of target SoC. The trace data together with corresponding look-up table (LUT) is utilized for the power analysis. The trace data is also used to reduce the number of input vectors required to analyze the power consumption of large H/W designs through the trade-offs between the signal probability in the trace results and its effect on the power consumption. The effect of cache miss on power, occurring in the S/W program execution, is also considered in the proposed framework. The performance of the proposed approach was evaluated through the case study using the SoC design example of IEEE 802.11a wireless LAN modem. The case study illustrated that, by providing fast and accurate power analysis results, the proposed approach can enable SoC designers to manage the power consumption effectively through the reconstruction of the target SoC. The proposed framework maps all hardware IPs into FPGA. The trace based approach gets input vectors at transactor of the each IP and gets power consumption indexing a LUT. This hardware oriented technique reports the power estimation result faster than the conventional ones doing it at S/W level.     

Review of battery powered embedded systems design for mission-critical low-power applications

The applications and uses of embedded systems is increasingly pervasive. Mission and safety critical systems relying on embedded systems pose specific challenges. Embedded systems is a multi-disciplinary domain, involving both hardware and software. Systems need to be designed in a holistic manner so that they are able to provide the desired reliability and minimise unnecessary complexity. The large problem landscape means that there is no one solution that fits all applications of embedded systems. With the primary focus of these mission and safety critical systems being functionality and reliability, there can be conflicts with business needs, and this can introduce pressures to reduce cost at the expense of reliability and functionality. This paper examines the challenges faced by battery powered systems, and then explores at more general problems, and several real-world embedded systems.     

Estimating data bus size for custom processors in embedded systems

We propose a method to estimate the data bus width to the requirements of an application that is to run on a custom processor. The proposed estimation method is a simulation-based tool that uses Extreme Value Theory to estimate the width of an off-chip or on-chip data bus based on the characteristics of the application. It finds the minimum number of bus lines needed for the bus connecting the custom processor to other units so that the probability of a multicycle data transfer on the bus is extremely unlikely. The potential target platforms include embedded systems where a custom processor (i.e. an ASIC or a FPGA) in a system-on-a-chip or a system-on-a-board is connected to memory, I/O and other processors through a shared bus or through point-to-point links. Our experimental and analytical results show that our estimation method can reduce the data bus width and cost by up to 66% with an average of 38% for nine benchmarks. The narrower data bus allows us to increase the spacing between the bus lines using the silicon area freed from the eliminated bus lines. This reduces interwire capacitance, which in turn leads to a significant reduction of bus energy consumption. Bus energy can potentially be reduced up to 89% for on-chip data buses with an average of 74% for seven benchmarks. Also, reduction in the interwire capacitance improves the bus propagation delay and on-chip bus propagation delay can be reduced up to 68% with an average of 51% for seven benchmarks using a narrower custom data bus.     

EM alignment using phase for secure embedded systems

If electromagnetic (EM) waves emanating from a wireless device during a cryptographic computation leak sufficient information, it may be possible for an attacker to reconstruct the secret key. Despite the complexities of a Java-based PDA device, this paper presents a new phase based technique for aligning EM frames for subsequent time based DEMA. The proposed technique involves: fast Fourier transform, phase-substitution, inverse fast Fourier transform and time based DEMA. Results are repeatable over several different secret keys. Unlike previous research the new technique does not require perfect alignment of EM frames, and demonstrates robustness in the presence of a complex embedded system (including cache misses, operating system events, etc.) with random delays as well as random operations. This research is important for future wireless and complex embedded systems where security is crucial.     

An embedded, FPGA-based computer graphics coprocessor with native geometric algebra support

The representation of geometric objects and their transformation are the two key aspects in computer graphics applications. Traditionally, computer-intensive matrix calculations are involved in modeling and rendering three-dimensional (3D) scenery. Geometric algebra (aka Clifford algebra) is attracting attention as a natural way to model geometric facts and as a powerful analytical tool for symbolic calculations. In this paper, the architecture of Clifford coprocessor (CliffoSor) is introduced. CliffoSor is an embedded parallel coprocessing core that offers direct hardware support to Clifford algebra operators. A prototype implementation on a programmable gate array (FPGA) board is detailed. Initial test results show the potential to achieve a 20× speedup for 3D vector rotations, a 12× speedup for Clifford sums and differences, and more than a 4× speedup for Clifford products, compared to the analogous operations in GAIGEN, a standard geometric algebra library generator for general-purpose processors. An execution analysis of a raytracing application is also presented.     

Modern development methods and tools for embedded reconfigurable systems: A survey

Heterogeneous reconfigurable systems provide drastically higher performance and lower power consumption than traditional CPU-centric systems. Moreover, they do it at much lower costs and shorter times to market than non-reconfigurable hardware solutions. They also provide the flexibility that is often required for the engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, reconfigurable systems are adequate for a very broad class of applications across different industry sectors. What prevents the reconfigurable system paradigm from a broad proliferation is the lack of adequate development methodologies and electronics design tools for this kind of systems. The ideal would be a seamless compilation of a high-level computation process specification into an optimized mixture of machine code executed on traditional CPU-centric processors and on the application-specific decentralized parallel data-flow-dominated reconfigurable processors and hardware accelerators. Although much research and development in this direction was recently performed, the adequate methodologies and tools necessary to implement this compilation process as an effective and efficient hardware/software co-synthesis flow are unfortunately not yet in place. This paper focuses on the recent developments and development trends in the design methods and synthesis tools for reconfigurable systems. Reconfigurable system synthesis performs two basic tasks: system structure construction and application process mapping on the structure. It is thus more complex than standard (multi-)processor-based system synthesis for software-programmable systems that only involves application mapping. The system structure construction may involve the macro-architecture synthesis, the micro-architecture synthesis, and the actual hardware synthesis. Also, the application process mapping can be more complicated and dynamic in reconfigurable systems. This paper reviews the recent methods and tools for the macro- and micro-architecture synthesis, and for the application mapping of reconfigurable systems. It puts much attention to the relevant and currently hot topic of (re-)configurable application-specific instruction set processors (ASIP) synthesis, and specifically, ASIP instruction set extension. It also discusses the methods and tools for reconfigurable systems involving CPU-centric processors collaborating with reconfigurable hardware sub-systems, for which the main problem is to decide which computation processes should be implemented in software and which in hardware, but the hardware/software partitioning has to account for the hardware sharing by different computation processes and for the reconfiguration processes. The reconfigurable system area is a very promising, but quite a new field, with many open research and development topics. The paper reviews some of the future trends in the reconfigurable system development methods and tools. Finally, the discussion of the paper is summarized and concluded.     

Highly configurable platforms for embedded computing systems

Platform chips, which are pre-designed chips possessing numerous processors, memories, coprocessors, and field-programmable gates arrays, are becoming increasingly popular. Platforms eliminate the costs and risks associated with creating customized chips, but with the drawbacks of poorer performance and energy consumption. Making platforms highly configurable, so they can be tuned to the particular applications that will execute on those platforms, can help reduce those drawbacks. We discuss the trends leading embedded system designers towards the use of platforms instead of customized chips. We discuss UCR research in designing highly configurable platforms, highlighting some of our work in highly configurable caches, and in hardware/software partitioning.     

嵌入式单片机在电机控制系统中的应用

在工业领域,电机的运行状态关系到生产的效率和安全,是广大机电控制技术人员关注的重点。随着数字式控制系统的发展,嵌入式单片机在电机控制系统的应用越来越广发,对电机的控制更加的安全、可靠,能使电机长时间处于良好的工作状态,其稳定性也得到了显著的提升。嵌入式单片机在电机控制系统中的应用可以分为软件应用和硬件应用,硬件提供基本的物理框架支撑,软件提供基本的信息、数据处理渠道,也只有这样,才能有效提升电机控制系统的性能,这也是建立高速实时电机控制系统的前提。     

A general time model for the specification and design of embedded real-time systems

Design of complex embedded systems feasible with current and upcoming semiconductor technologies necessitates consideration of real-time from the beginning. However, the commonly used specification techniques do not consider temporal aspects in general like fulfillment of high level timing requirements or dynamic reactions on timing violations. In this paper, we discuss the restrictions of current specification techniques for embedded real-time systems and present a general time model that solves this issue. The time model contains the progress of time, the measurement of time and the specification of timing requirements based on event traces. In contrast to earlier techniques, preconditions determine the actual relevance of a specific timing bound. Exemplified for SDL, a solution for the specification of temporal aspects is shown. The advantages of this solution are discussed in a hardware/software co-design case study from the mobile communication area.     

使用软硬件协同仿真技术的嵌入式系统开发工具包

文章介绍了一种新的工具包。其中，源代码分析器SCP（Source Code Parser）用于将嵌入式软件源代码转换为对应的ANSIC，C＋＋代码，作为目标系统软件的模型。虚拟硬件平台VHP（Virtual Hardware Platform）函数库提供了包括LCD显示器、以太网口在内的虚拟硬件资源，以对硬件进行建模。使用本工具包生成的系统模型是PC上的可执行程序，开发人员可以通过运行模型方便地验证目标系统的功能和性能。     

Qualification procedure for moisture in embedded capacitors

Embedding passives in PCB permits to gain in integration density while enhancing electromagnetic compatibility performances. The choice of the dielectric film is fundamental for large frequency band stability of embedded capacitances. However, these materials are prone to water absorption, which can lead to functional parameter degradations and additional stresses at the interfaces. This paper presents experimental capacitors embedded in FR-4, and finite element simulations of moisture absorption in various dielectric materials. Technological choices, as well as the qualification procedure, can be improved thanks to the simulation results.     

A co-synthesis approach to embedded system design automation

Embedded systems are targeted for specific applications under constraints on relative timing of their actions. For such systems, the use of pre-designed reprogrammable components such as microprocessors provides an effective way to reduce system cost by implementing part of the functionality as a program running on the processor. However, dedicated hardware is often necessary to achieve the requisite timing performance. Analysis of timing constraints is, therefore, key to determination of an efficient hardware-software implementation. In this paper, we present a methodology for embedded system design as a co-synthesis of interacting hardware and software components. We present a decomposition of the co-synthesis problem into sub-problems, that is useful in building a framework for embedded system CAD. In particular, we present operation-level timing constraints and develop the notion of satisfiability of constraints by a given implementation both in the deterministic and probabilistic sense. Constraint satisfiability analysis is then used to define hardware and software portions of functionality. We describe algorithms and techniques used in developing a practical co-synthesis framework, vulcan. Examples are presented to show the utility of our approach.     

基于嵌入式系统的激光扫描检测系统

为了提高回转体零件的加工和检测精度,将光电检测技术与电子计算机技术相结合,设计并研制了一种基于嵌入式系统的激光扫描检测系统,给出了设计原理和软硬件设计方法,并利用该系统对轴径不同的六组标准工件进行测量.实验表明,该系统的平均测量误差为0.00283mm,满足设计指标要求的3μm,能够极大提高回转体零件的尺寸测量精度,具有较好的应用价值.     

Acrylic Nanocomposite Resins for Use in Stereolithography and Structural Light Modulation Based Rapid Prototyping and Rapid Manufacturing Technologies

A novel family of optically transparent acrylic nanocomposites containing up to 30 wt % silica nanoparticles with an average diameter of 20 nm was developed for application in structural light modulation (SLM) and stereolithography (SL) technologies. The uniform dispersion of nanoparticles affords a significantly improved toughness/stiffness‐balance of the photopolymerized and postcured nanocomposites. It is possible to increase stiffness, as expressed by Young's modulus, from 1290 to 1700 MPa without encountering the embrittlement typical for many other conventional filled polymers. Fracture behaviour is examined by means of fracture mechanics investigation and SEM analyses of fracture surfaces. According to TEM analyses and measurement of optical transmittance remarkable uniform dispersion of silica nanoparticles was achieved. The silica nanoparticle concentrations up to 17 wt % give only marginally higher viscosities and do not affect transmittance, while slightly increasing the exposure times needed in photopolymerization. Moreover, the silica nanoparticles afford materials with reduced shrinkage and improved properties. The green effective ankle splay out (EASO) measured on H‐shaped diagnostic specimens, is significantly reduced for the nanocomposite materials from 1.38 mm for the unfilled material to 0.82 mm for nanocomposites containing 30 wt % nanosilica. The building accuracy is increased significantly with increasing content of silica nanofillers.