Hardware-accelerated design space exploration framework for communication systems

The efficient hardware implementation of signal processing algorithms requires a rigid characterization of the interdependencies between system parameters and hardware costs. Pure software simulation of bit-true implementations of algorithms with high computational complexity is prohibitive because of the excessive runtime. Therefore, we present a field-programmable gate array (FPGA) based hybrid hardware-in-the-loop design space exploration (DSE) framework combining high-level tools (e.g. MATLAB, C++) with a System-on-Chip (SoC) template mapped on FPGA-based emulation systems. This combination significantly accelerates the design process and characterization of highly optimized hardware modules. Furthermore, the approach helps to quantify the interdependencies between system parameters and hardware costs. The achievable emulation speedup using bit-true hardware modules is a key enabling the optimization of complex signal processing systems using Monte Carlo approaches which are infeasible for pure software simulation due to the large required stimuli sets. The framework supports a divide-and-conquer approach through a flexible partitioning of complex algorithms across the system resources on different layers of abstraction. This facilitates to efficiently split the design process among different teams. The presented framework comprises a generic state of the art SoC infrastructure template, a transparent communication layer including MATLAB and hardware interfaces, module wrappers and DSE facilities. The hardware template is synthesizable for a variety of FPGA-based platforms. Implementation and DSE results for two case studies from the different application fields of synthetic aperture radar image processing and interference alignment in communication systems are presented.     

基于Linux的无线视频传输系统设计与实现

选用ARM9（S3C2410）处理器为硬件平台,嵌入式Linux操作系统为软件平台,采用WLAN为传输方式,设计并实现了一个无线视频传输系统。提出一个无线视频系统的总框架,介绍系统硬件平台和软件平台的设计与实现,其中主要介绍无线视频系统中的各个模块,包括视频采集模块、无线视频传输模块、视频显示模块。最后验证系统,在接收端可以清楚、连续地显示出发送端所采集到的视频图像。无线视频传输系统可以广泛地应用于视频监控、信息家电、智能小区、远程抄表等领域,而且所研究的嵌入式视频系统设备经过进一步开发和完善,还可以应用于更广阔的领域。     

ACE框架在网络游戏服务器中的设计与应用

由于操作系统及通信平台的多样性,通信软件开发者往往要面对诸多问题,而利用软件设计模式能够帮助开发者成功完成任务并开发出高性能的通信软件。介绍ACE框架在通信领域中的面向对象的设计模式以及使用ACE框架构建通信系统软件所带来的优势,并提出了一种网络服务器架构以及基于模块设计服务器系统软件的思想。最后结合具体应用,详细讲述如何利用ACE中的若干设计模式及组件框架进行网络服务器通信底层模块的设计和实现。     

嵌入式软件系统的一种层次设计方法

嵌入式软件系统一般由实时操作系统、应用层软件及硬件驱动软件等部分构成。本文提出了一种应用在嵌入式软件系统开发中的层次设计方法，采用模块化的软件设计思想，将嵌入式软件系统分为不同的功能模块，不同的软件模块负责不同的功能。设计的总体原则是使嵌入式软件系统具有易移植、可复用、与平台无关等特点。这样可以满足现代大规模软件开发的需求，缩短软件的开发时间，便于软件的管理和控制，从而大大提高软件的质量。     

Automated Design Space Exploration for DSP Applications

We present a performance analysis framework that efficiently generates and analyzes hardware designs for computationally intensive signal processing applications. Our framework synthesizes designs from a high level of abstraction into well-constructed and recognizable hardware structures that perform well in terms of area, throughput and power dissipation. Cost functions provided by our framework allow the user to reduce the design space to a set of efficient hardware implementations that meet performance constraints. We utilize our framework to estimate hardware performance using a set of pre-synthesized mathematical cores which expedites the synthesis process by approximately 14 fold. This reduces the architectural generation and hardware synthesis process from days to several hours for complex designs. Our work aims at performing hardware optimizations at the architectural and arithmetic levels, relieving the user from manually describing the designs at the register transfer level and iteratively varying the hardware structures. We illustrate the efficiency and accuracy of our framework by generating finite impulse response filter structures used in several signal processing applications such as adaptive equalizers and quadrature mirror filters. The results show that hardware filter structures generated by our framework can achieve, on average, a 3 fold increase in power efficiency when compared to manually constructed designs.     

电子战仿真中信号处理系统的软件化设计

在半实物电子战仿真系统中,要求雷达信号处理系统完成多种雷达体制的模拟,传统的基于任务、面向硬件的实现方法不能满足多种雷达工作方式的要求。随着数字化技术和软硬件的不断发展,雷达软件化设计成为雷达信号处理的发展方向。本系统采用雷达软件化的设计方法,从硬件平台和软件结构介绍了系统的实现。该系统可在不同的雷达工作模式间进行切换,充分体现了灵活性、可扩展性和兼容性等特点。     

微机励磁调节器实验仿真平台研制

本文介绍的微机励磁调节器实验仿真平台,包括硬件仿真平台和软件仿真平台。硬件仿真平台是用Proteus对微机各个功能模块的硬件进行仿真,软件仿真平台是利用软件开发环境和硬件仿真平台一起进行的软件各个模块的开发和验证。本文还通过举倒介绍硬件仿真模块的应用和软件仿真模块的功能。硬件仿真平台和软件仿真平台联合仿真能够模拟微机励磁实验,可以辅助实验教学。     

C语言单片机系统软件架构的教学研究

针对C语言单片机系统开发,阐述了单片机系统的软件架构。将多层软件框架模型引入到单片机应用软件开发,给出了基于分层设计的功能模块划分。按照系统功能进行分层隔离封装,降低功能模块间的耦合关系,设计出包含主程序层、应用模块层、功能模块层和MCU硬件驱动层等四层架构模型。该架构为利用C语言进行单片机系统开发提供参考解决方案,有利于提高单片机软件开发的可靠性、拓展性和重用性。     

A design system for on-chip oversampling A/D interfaces

An integrated design system for the analysis, design, and implementation of on-chip A/D interfaces using oversampling A/D converters has been developed. The system unifies a diverse base of design knowledge required for mixed analog and digital circuits and covers the design process from specification to mask layout for a variety of configurations. A hierarchical design estimation approach was used to guide system development, allowing designers to quickly estimate performance at a high level of abstraction and to update these estimates as the design progresses. At lower levels of abstraction, architecture templates are used to encapsulate information about particular filter implementations and to simplify the design process. Designers use performance estimates to guide the design process and to make the critical decisions about the choice of algorithm and architecture. Accurate simulation models have been integrated into the design system to allow examination and verification. Results from a 14-b signal acquisition module are presented to illustrate use of the tools and the typical tradeoffs faced at different levels of abstraction. This system illustrates how various design automation techniques can be combined to provide better optimization for a complex system design and to shorten design cycles for custom converters to a matter of days     

基于移动通信的加密定位模块设计与实现

根据综合考虑业务发展和运营商的实际需求,针对传统加密技术进行拓展,设计出了一种基于移动通信定位技术的新型通用硬件加密模块,对加密模块的设计原理、软硬件系统架构及运行流程等进行了阐述,并通过测试环境进行仿真及验证。结果证明,此方案设计具有高度的可靠性和稳定性。进一步地,该设计方案已通过了安徽广电网络中心的认证,将在安徽广电网络中进行规模应用。     

The Agamid design-space exploration framework

The emergence of many-core processors raises novel demands to system design. Power-limitations and abundant parallelism require for efficient and scalable run-time management. The integration of dedicated hardware to enhance the performance of the run-time management system is gaining an increasing importance. But the design of a run-time manager for many-core generally suffers from exhaustive evaluation time. Previous works do not address for the required flexibility or do not address for reasonable evaluation time of the simulation framework. We propose the novel simulation framework Agamid to foster the development and evaluation of hardware enhanced run-time management for many-core. Our transaction-level framework performs design point evaluation of hardware enhanced run-time management for many-core at the timescale of seconds. We use a hybrid simulation approach considering the run-time management and the user application at different levels of abstraction. The framework provides a generic run-time manager to compare arbitrary management systems and HW/SW partitionings. The implementation of the run-time manager facilitates direct execution at the host machine and a detailed synchronization model. Agamid applies user application workloads by means of transaction-based task graphs. An extendable system-call interface allows arbitrary interaction between the user application and the run-time management system. The thorough calibration of the RTM timing model enables reasonable approximations of the management overhead. Our evaluation considers the accuracy, wall-time and design space exploration capabilities of Agamid. Our findings substantiate the usefulness to integrate the modeling of the run-time management, hardware architecture and user application into a single transaction-level framework.     

基于嵌入式Linux的导弹仿真导引头软件设计与开发

针对仿真导引头并行时序控制任务繁多的问题,将开放源代码的嵌入式Linux操作系统引入系统设计中。通过对AT91RM9200的硬件构架特点及仿真导引头的功能需求的分析,开发了系统软件底层驱动并在AT91RM9200上移植了嵌入式Linux系统。利用内核模块机制,分别开发了各功能模块的驱动程序,并利用嵌入式Linux下的定时器机制和多进程技术,开发了系统应用软件。初步实验结果表明,软件系统工作正常,能够满足各项技术指标要求,验证了本系统设计的有效性。     

SCA中硬件抽象层研究

介绍了SCA中硬件抽象层（Hardware Abstraction Layer Connectivity。HAL-C）的概念及其实现方法。对DSP、FPGA硬件抽象层的实现方案进行了讨论。基于硬件抽象层设计的软件模块将具有很好的可移植性。能有效缩短系统开发周期。提高系统开发效率。     

基于ARM的蓝牙通信模块的设计与实现

为解决工业现场布线复杂的问题,设计了一种基于ARM的蓝牙无线通信模块,介绍了蓝牙模块在嵌入式平台上硬件和软件的设计与实现,细致阐述其设计原理,并重点介绍硬件设计框架和软件参数设置及软件设计流程。该系统以S3C2440为控制核心,无线收发部分以GC-02为蓝牙模块,在Linux操作系统上完成应用程序的开发。在工业现场环境恶劣的情况下应用该模块,经过多次测试数据传输正常,达到预期效果。     

Resilience Articulation Point (RAP): Cross-layer dependability modeling for nanometer system-on-chip resilience

The Resilience Articulation Point (RAP) model aims at provisioning researchers and developers with a probabilistic fault abstraction and error propagation framework covering all hardware/software layers of a System on Chip. RAP assumes that physically induced faults at the technology or CMOS device layer will eventually manifest themselves as a single or multiple bit flip(s). When probabilistic error functions for specific fault origins are known at the bit or signal level, knowledge about the unit of design and its environment allow the transformation of the bit-related error functions into characteristic higher layer representations, such as error functions for data words, Finite State Machine (FSM) state, macro-interfaces or software variables. Thus, design concerns at higher abstraction layers can be investigated without the necessity to further consider the full details of lower levels of design. This paper introduces the ideas of RAP based on examples of radiation induced soft errors in SRAM cells, voltage variations and sequential CMOS logic. It shows by example how probabilistic bit flips are systematically abstracted and propagated towards higher abstraction levels up to the application software layer, and how RAP can be used to parameterize architecture-level resilience methods.     

无人机测试数据的采集研究

无人机测试数据的采集需要完善的采集系统做基础,故而必须设计并构建相应的系统。测试数据采集系统的设计与构建应当以明确设计需求为基础,并以此指导总体方案的有效设计,然后再分别从硬件与软件两大层面进行科学设计,确保主控制器模块、无线数据发射与接收模块、信号调理电路、串行接口电路、数据采集主程序、电压信号数据采集程序、脉冲频率信号采集程序等均符合实际需求。在完成系统设计与构建后,还需要做好相应的终端设计与调试工作,确保采集系统能够完整、准确采集测试数据。     

A programmable architecture for OFDM-CDMA

Combining multicarrier (OFDM) and CDMA technologies is attractive for future wireless broadband communications and software radio realization. Based on the unified framework known as OFCDMA, we develop a programmable structure for OFDM-CDMA transceivers in spite of three different scenarios to combine OFDM and CDMA. By adjusting system parameters without changing the fundamental hardware and software architecture, various system scenarios can be implemented, which might serve as the foundation to design software radio