An Interpolating Digitally Controlled Oscillator for a Wide-Range All-Digital PLL

A digitally controlled oscillator (DCO) for the all-digital phase-locked loop (ADPLL) with both the wide frequency range and the high maximum frequency was proposed by using the interpolation scheme at both the coarse and fine delay blocks of the DCO. The coarse block consists of two ladder-shaped coarse delay chains. The delay of the first one is an odd multiple of an inverter delay and that of the second one is an even multiple. An interpolation operation is performed at the second coarse delay chain, which reduces both the resolution of the coarse delay block and the delay range of the fine block to half. This increases the maximum output frequency of the DCO while it maintains the wide frequency range. The ADPLL with the proposed DCO was fabricated in a 0.18 mum CMOS process with the active area of 0.32 mm² . The measured output frequency of the ADPLL ranges from 33 to 1040 MHz at the supply of 1.8 V. The measured rms and peak-to-peak jitters are 13.8 ps and 86.7 ps, respectively, at the output frequency of 950 MHz. The power consumption is 15.7 mW.     

数字控制振荡器的设计和顶层模型

采用0.18 μm CMOS六层金属工艺,利用带中心抽头的对称螺旋电感和新型电容调谐阵列构成的LC谐振回路,设计并实现了一种低功耗低相位噪声的数字控制振荡器(DCO).流片测试结果表明,相位噪声在1 MHz偏移频率处为-119.77 dBc/Hz.电路采用1.8V电源供电,消耗约4.9mA电流,当电源电压降到1.6V时,消耗约4.1 mA的核心电路电流,此时,相位噪声在1 MHz频偏处仍达到-119.1 dBc/Hz.为了提高全数字锁相环设计效率,采用硬件描述语言,构建了一种适用于全数字锁相环的仿真模型.该模型能大大缩短早期系统级架构选择和算法级行为验证的时间.     

数控高频振荡器的设计

介绍了目前常用的数控延迟单元电路结构,详细分析了这些电路的优缺点.在此基础上,对其中一种电路结构进行了详细的理论分析,改进了电路结构,规范了电路设计的具体步骤,并通过大量的电路模拟,印证了理论分析的正确性.以此延迟单元为核心,在SMIC 0.13μm工艺下,设计实现了一款数控高频振荡器.该振荡器的频率范围高达700 MHz,最高稳定输出频率可达到1 GHz.由于采用全数字实现方式,其功耗最大值不到0.7 mW,版图面积只有26μm×36μm.该电路已成功应用于一个锁相环电路的设计中.     

无线传感网SoC芯片中4.8 GHz压控振荡器设计

采用SMIC 0.18 μm 1P6 M RF CMOS工艺设计了一个4.8 GHz LC压控振荡器,该压控振荡器应用于无线传感SoC芯片射频前端频率综合器中.电路核心采用带电阻反馈的差分负阻结构,因此具有良好的相位噪声性能;2bit的开关电容阵列进一步提高了电路的调谐范围;共源级输出缓冲提供了较好的反向隔离度.所设计的芯片版图面积为600 μm×475μm.在电源电压为1.8 V时,后仿真结果表明,电路调谐范围最高可达40%,有效地补偿了工艺角偏差;在4.95 GHz处,后仿真测得的相位噪声为-125.3 dBc/Hz @ 3 MHz,优于系统要求5.3 dB;核心电路工作电流约5.2 mA.     

A 1 V Wireless Transceiver for an Ultra-Low-Power SoC for Biotelemetry Applications

This paper presents a 1 V RF transceiver for biotelemetry and wireless body sensor network (WBSN) applications, realized as part of an ultra low power system-on-chip (SoC), the Sensiumtrade. The transceiver utilizes FSK/GFSK modulation at a data rate of 50 kbit/s to provide wireless connectivity between target sensor nodes and a central base-station node in a single-hop star network topology operating in the 862-870 MHz European short-range-device (SRD) and the 902-928 MHz North American Industrial, Scientific & Medical (ISM) frequency bands. Controlled by a proprietary media access controller (MAC) which is hardware implemented on chip, the transceiver operates half-duplex, achieving -102 dBm receiver input sensitivity (for 1E-3 raw bit error rate) and up to -7 dBm transmitter output power through a single antenna port. It consumes 2.1 mA during receive and up to 2.6 mA during transmit from a 0.9 to 1.5 V supply. It is fabricated in a 0.13 mum CMOS technology and occupies 7 mm² in a SoC die size of 4 times 4 mm².     

A Digitally Controlled Stimulator for Neurophysiological Applications

A stimulator circuit is presented which is capable of generating pulse train waveforms suitable for neurophysiological experiments are available, as well as special test conditions such as dishabituation. Digital and linear integrated circuits are used to provide precise control over the stimulus parameters.     

Monotonic Wide-Range Digitally Controlled Oscillator Compensated for Supply Voltage Variation

A digitally controlled oscillator (DCO) to be used in an all-digital phase-locked loop (PLL) is presented which offers a wide operating frequency range, a monotonic gain curve, and compensation for instantaneous supply voltage variation. The monotonic and wide oscillation frequency is achieved by interpolating at the fine tuning block between two nodes selected from a coarse delay line. Supply voltage compensation is obtained by dynamically adjusting the strength of the feedback latch of the delay cell in response to the change of the supply voltage.      

一种用于IR-UWB的数控环形振荡器设计

设计了一个应用于超宽带脉冲无线电（IR-UWB）通信系统的数控环形振荡器（DCRO）.DCRO采用3调谐,包括电压粗调谐和开关变容管精调谐,逐级提高调谐精度.提出了一种新型延时单元,采用多环路结构,提高了环形振荡器的振荡频率,降低了功耗.设计采用CSMC 0.18μm互补金属氧化物半导体工艺,电源电压1.8V,使用SpectreRF仿真验证,数控环形振荡器的调谐范围为3～8.6GHz,调谐精度为2MHz,当工作频率在8.6GHz时,偏离主频10MHz处相位噪声为-112.4dBc/Hz,功耗为20mW.     

数字电视接收芯片中数控晶体振荡器的设计

运用负阻模型分析石英晶体振荡器,设计实现了一种用于数字电视接收芯片的数控石英晶体振荡器(DCXO).该DCXO采用Pierce结构,利用基带与振荡器的反馈环路产生的6位自动频率控制信号对振荡器的频率漂移进行校准,得到长期稳定的频率输出.电路采用TSMC混合/RF 0.13 μm CMOS工艺实现,中心频率为24 MHz.在1.2 V电源电压下的仿真结果显示:数控范围72×10-6@24 MHz,调节精度1×10-6/step,启动时间约900 μs,振荡器振荡峰值为0.8 V;在偏离中心频率1 kHz和10 kHz处的相位噪声分别为-141 dBc和-155 dBc.该振荡器除石英晶体外,均集成在片内.     

一个应用于PHS系统的低噪声低功耗全数控LC振荡器

针对PHS通信系统,综合采用了反型数控MOS变容管、数控MOS变容管单元矩阵、动态元素匹配、流水线MASHΣ△调制器等多项旨在提高新型全数控LC振荡器(DCO)性能的电路技术,在SMIC 0.18μm CMOS工艺下设计了一种低噪声低功耗的DCO.经测试得到,该DCO的中心振荡频率为3.1GHz,频率调节范围为120MHz,电源电压为1.8V,电流为2.8mA.当振荡在3.1GHz时,该DCO输出信号在100kHz与1.2MHz频偏处的相位噪声分别为-102.3和-122.6dBc/Hz.测试结果表明,该DCO与国际上DCO设计的最新水平相比,在相位噪声与功耗等方面具有较高的优势.     

一个应用于PHS系统的低噪声低功耗全数控LC振荡器

针对PHS通信系统,综合采用了反型数控MOS变容管、数控MOS变容管单元矩阵、动态元素匹配、流水线MASHΣ△调制器等多项旨在提高新型全数控LC振荡器(DCO)性能的电路技术,在SMIC 0.18μm CMOS工艺下设计了一种低噪声低功耗的DCO.经测试得到,该DCO的中心振荡频率为3.1GHz,频率调节范围为120MHz,电源电压为1.8V,电流为2.8mA.当振荡在3.1GHz时,该DCO输出信号在100kHz与1.2MHz频偏处的相位噪声分别为-102.3和-122.6dBc/Hz.测试结果表明,该DCO与国际上DCO设计的最新水平相比,在相位噪声与功耗等方面具有较高的优势.     

Subthreshold Source-Coupled Logic Circuits for Ultra-Low-Power Applications

This paper presents a novel approach for implementing ultra-low-power digital components and systems using source-coupled logic (SCL) circuit topology, operating in weak inversion (subthreshold) regime. Minimum size pMOS transistors with shorted drain-substrate contacts are used as gate-controlled, very high resistivity load devices. Based on the proposed approach, the power consumption and the operation frequency of logic circuits can be scaled down linearly by changing the tail bias current of SCL gates over a very wide range spanning several orders of magnitude, which is not achievable in subthreshold CMOS circuits. Measurements in conventional 0.18 m CMOS technology show that the tail bias current of each gate can be set as low as 10 pA, with a supply voltage of 300 mV, resulting in a power-delay product of less than 1 fJ. Fundamental circuits such as ring oscillators and frequency dividers, as well as more complex digital blocks such as parallel multipliers designed by using the STSCL topology have been experimentally characterized.     

射频应用的压控振荡器相位噪声的研究

相位噪声是压控振荡器(VCO)的关键参数之一。阐述了VCO相位噪声的特性,分析了时不变和时变两种相位噪声模型,给出了优化相位噪声的方法。     

便携式多媒体SoC的视频处理方案

由于消费者对便携式多媒体设备的强劲需求及技术上的进步，设备制造商面对的挑战是必须把更多的功能和服务集成在越来越小型、价廉和功能多样化的产品中。要了解如何针对这个市场创建高价值及与众不同的多媒体SoC，我们必须先看看目前一般的便携式多媒体设备能够实现的技术范围。     

一个高抗干扰数字自动控制增益的声发射监测系统

工业现场工况监测常常面临两个主要问题：微弱检测信号需要根据实时状况自动变增益放大;在恶劣强电磁场环境下,检测信号能否屏蔽掉绝大部分干扰,传递到计算机进行进一步处理。针对这两个问题,开发了一个高抗干扰数字自动控制增益的声发射监测系统,可适合于强电磁场环境,自动地调整前置放大器的增益。该系统包含一种大动态变化范围的新型数控可变增益放大电路、电源管理电路、模拟信号光纤传输电路和数字信号光纤传输电路。介绍了系统结构、电路原理及实验结果。     

基于数字控制PSM流限模式的AC-DC变换器

设计了一种应用于反激式AC-DC变换器的控制芯片.为了提高AC-DC变换器的工作稳定性,降低成本,实现全负载范围较高的转换效率,采用PSM流限控制模式.PSM流限控制模式结构简单,可有效降低系统成本.系统根据负载情况分段调节流限值,实现各负载点较高的转换效率,减小输出电压纹波,避免轻载时开关频率进入音频范围.芯片主要采...     

一种数字控制可调增益放大器

介绍了一种基于R-2R梯形电阻网络原理的CMOS数字控制可调增益放大器,放大器的增益由数字信号控制线性调节,增益调节的步长可根据不同需要调整变换,进行高精度的线性增益调节。     

一种适用于射频电子标签的超低功耗嵌入式EEPROM

采用Chartered 0.35μm EEPROM工艺设计并实现了一个适用于无源射频电子标签的256位超低功耗EEPROM存储器.芯片实现了块编程和擦写功能,并通过优化敏感放大器和控制逻辑的结构,实现了读存储器时间和功耗的最优化.最后给出了芯片在编程/擦写/读操作情况下的功耗测试结果.在电源电压为1.8V,数据率为640kHz时,EEPROM编程/擦写的平均功耗约为68μA,读操作平均功耗约为0.6μA.     

An Ultra-Low-Power Embedded EEPROM for Passive RFID Tags

采用Chartered 0.35μm EEPROM工艺设计并实现了一个适用于无源射频电子标签的256位超低功耗EEPROM存储器.芯片实现了块编程和擦写功能,并通过优化敏感放大器和控制逻辑的结构,实现了读存储器时间和功耗的最优化.最后给出了芯片在编程/擦写/读操作情况下的功耗测试结果.在电源电压为1.8V,数据率为640kHz时,EEPROM编程/擦写的平均功耗约为68μA,读操作平均功耗约为0.6μA.     

An Ultra-Low-Power Injection Locked Transmitter for Wireless Sensor Networks

This paper presents the principles for designing low-power transmitters for wireless sensor networks. Based on these principles, an injection-locked transmitter is implemented in a standard 0.13-$muhbox m$CMOS process and packaged using chip-on-board assembly. The transmitter utilizes a film bulk acoustic resonator (FBAR) to obtain a stable carrier at 1.9 GHz. At 0 dBm output power, the transmitter achieves an efficiency of 32% at 50 kb/s and 28% at 156 kb/s. With 50% on-off keying, the transmitter consumes 1.6 and 1.8 mW, respectively.