A 10 bit 20 MS/s 3 V supply CMOS A/D converter

A 10 bit CMOS A/D converter with 3 V power supply has been developed for being integrated into system VLSI's. In this A/D converter, redundant binary encoders named “twin encoders” enhance tolerance to substrate noise, together with employing differential amplifiers in comparators. The bias circuit using a replica of the amplifier is developed for biasing differential comparators with 3 V power supply. Subranging architecture along with a multilevel tree decoding structure improves dynamic performance of the ADC at 3 V power supply. The A/D converter is fabricated in double-polysilicon, double-metal, 0.8 μm CMOS technology. The experimental results show that the ADC operates at 20 MS/s and the twin encoders suppress the influence of substrate noise effectively. This ADC has a single power supply of 3 V, and dissipates 135 mW at 20 MS/s operation     

A 150 MS/s 133$~mu$W 7 bit ADC in 90 nm Digital CMOS

In recent years the energy efficiency of A/D converters has been improved significantly. Only 5 years ago an energy efficiency of 1 pJ/conversion step was considered state-of-the-art. Now power efficiencies are reported in fJ/conversion step. In this paper two new converter techniques are presented that further improve upon reported energy efficiencies of A/D converters. The first technique implements the quantization with a comparator-based asynchronous binary search (CABS). The second technique implements the SAR control algorithm on the comparators (SAR-CC) that are also used to do the quantization. Both these techniques have been applied in a fully dynamic 7 bit A/D converter that uses a two-step 1b coarse and 6b fine architecture . The 1b coarse converter is implemented using the SAR-CC principle, the 6b fine converter is implemented using the CABS principle. The 7 bit prototype implementation in 90 nm digital CMOS on a 1 V supply achieves 6.4ENOB, 40 dB SNDR at 150 MS/s consuming 133$~mu{hbox {W}}$ giving 10 fJ/conversion step energy efficiency (FOM). A second prototype implementing a stand-alone 6b CABS converter (the sub-A/D converter of the 7 bit converter) achieves 32 dB SNDR at 250 MS/s with 140$~mu{hbox {W}}$ of power consumption, which results in a FOM of 15 fJ/conversion step.      

一个用于12位40-MS/s低功耗流水线ADC的MDAC电路设计

文中设计了一个用于12位40MHz采样率低功耗流水线ADC的MDAC电路.通过对运放的分时复用,使得一个电路模块实现了两级MDAC功能,达到降低整个ADC功耗的目的.通过对MDAC结构的改进,使得该模块可以达到12bit精度的要求.通过优化辅助运放的带宽,使得高增益运放能够快速稳定.本设计在TSMC0.35μmmixsignal3.3V工艺下实现,在40MHz采样频率下,以奈奎斯特采样频率满幅(Vpp=2V)信号输入,其SINAD为73dB,ENOB为11.90bit,SFDR为89dB.整个电路消耗的动态功耗为9mW.     

用于12 bit 40 MS/s低功耗流水线ADC的采样保持电路

设计了一个可降低12 bit 40 MHz采样率流水线ADC功耗的采样保持电路。通过对运放的分时复用,使得一个电路模块既实现了采样保持功能,又实现了MDAC功能,达到了降低整个ADC功耗的目的。通过对传统栅压自举开关改进,减少了电路的非线性失真。通过优化辅助运放的带宽,使得高增益运放能够快速稳定。本设计在TSMC0.35μm mix signal 3.3 V工艺下实现,在40 MHz采样频率,输入信号为奈奎斯特频率时,其动态范围(SFDR)为85 dB,信噪比(SNDR)为72 dB,有效位数(ENOB)为11.6 bit,整个电路消耗的动态功耗为14 mW。     

A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC

Zero-crossing-based circuits (ZCBC) are introduced as a generalization of comparator-based switched-capacitor circuits (CBSC). To demonstrate this concept, an 8-bit, 200 MS/s, pipelined ADC is implemented in a 0.18 CMOS technology. A dynamic zero-crossing detector and current source replace the functionality of an opamp to realize a precision charge transfer. Furthermore, current source splitting improves linearity at high speeds and bit decision flip-flops replace traditional bit decision comparators for increased speed. The complete ADC draws no static current and consumes 8.5 mW of power. The corresponding FOM is 0.38 pJ/step at 100 MS/s and 0.51 pJ/step at 200 MS/s.     

Analog-to-Digital Converters: Digitizing the Analog World

Challenges in analog-to-digital (A/D) conversion for future scaled complementary metal-oxide-semiconductor (CMOS) technologies are investigated. The analysis of a figure of merit (FOM) that accounts for energy per conversion step indicates that op-amps are one of the most significant performance bottlenecks. New mixed-signal circuit architectures, which are more suitable for A/D conversion in scaled CMOS technologies and are more energy efficient than traditional architectures, are described. These circuits sense the crossing of virtual ground with comparators or zero-crossing detectors instead of forcing the virtual ground with op-amps. The FOM derivations for the comparator and zero-crossing based circuits indicate potentially a large improvement over traditional op-amp based circuits. The designs and experimental results of analog-to-digital converters based on a prototype comparator and zero-crossing are discussed in detail.     

Effects of Quantization in Systolic 2D IIR Beam Filters on UWB Wireless Communications

Ultra-wideband (UWB) wireless beamforming systems may potentially be implemented digitally at multi-gigahertz clock frequencies using low-precision systolic array realizations of two-dimensional (2D) infinite impulse response (IIR) beam plane-wave filters. The finite precision performance of such filters is analyzed in terms of quantization noise. Extensive Monte Carlo simulations are performed using test vectors that are derived from 2D finite-difference time-domain (FDTD) computational electromagnetic models of the UWB channels. The bit error rate (BER) is determined as a function of signal-to-interference ratio (SIR), with and without beamforming, and for various practical combinations of finite internal wordlengths and A/D converter precisions. It is established that 3-bit A/D converters with 3- to 6-bit internal wordlengths are adequate for good performance and that 4-bit A/D converters with 4- to 7-bit internal wordlengths achieve excellent performance.     

A zero-crossing based 10-bit 100 MS/s pipeline ADC with controlled current in 90 nm CMOS

In this paper, a new charging technique for low power zero-crossing based circuit pipeline analog-to-digital converters (ADCs) is presented. The charging current sources are implemented as voltage-controlled current sources in order to charge the sampling capacitors based on the error signal. Using this method, the ADC power consumption is reduced while improving the accuracy. The necessary current control block is shared between consecutive stages further reducing the power consumption and die area. The proposed technique is applied to a 10-bit 100 MS/s pipeline ADC designed in a 90 nm CMOS technology with 1 V power supply. Circuit level simulation results using Cadence Spectre show a signal-to-noise and distortion ratio of 55.6 dB with 3.56 mW power consumption resulting in a figure of merit of 72.3 fJ/conv.step without employing any calibration technique.     

A stereo audio chip using approximate processing for decimation andinterpolation filters

A stereo audio chip uses approximate processing techniques in the digital decimation and interpolation filters to reduce its active power dissipation. One pair of analog-to-digital (A/D) converters and one pair of digital-to-analog (D/A) converters have been integrated in a die area of 10.22 mm² in a 0.5 μm CMOS technology. The total power dissipation of these converters without power management is 200 mW when operated from a 5-V power supply. When the signal is fully active, power reductions of 36% for decimation and 17% for interpolation over fixed-order filters are demonstrated. When the signal is 40 dB below overload, power reductions of 67% for decimation and 44% for interpolation over fixed-order filters are observed. The power reductions are 83.1% for A/D converters, and 82.7% for D/A converters, when the signal is silent for a period of time     

基于DSP的高精度A/D转换器转换特性参数静态测试系统的设计

A/D转换器是许多电子系统中的一个重要器件,其性能好坏直接影响到整个电子系统的性能指标。本文介绍了一种基于DSP和高精度D/A转换器的自动测试系统,可对16位及16位以下的高精度A/D转换器的转换特性参数进行测试。该系统硬件连接简单,软件操作方便,便于携带。     

A/D转换技术的应用与发展

首先分别介绍了当前六大模数转换技术的工作原理、电路结构、性能特点及应用领域,通过从转换速率、转换精度、分辨率、功耗、价格、面积等指标进行分析,将物理结构的设计与实际性能结合比较,总结出各自适合的应用领域.然后,根据对现有模数转换技术特点的分析及实际应用中对模数转换器性能的要求,对当前A/D转换技术向着高性能、低功耗、结构简单方向发展的趋势进行了预测.     

An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.     

Analog-to-digital converter survey and analysis

Analog-to-digital converters (ADCs) are ubiquitous, critical components of software radio and other signal processing systems. This paper surveys the state-of-the-art of ADCs, including experimental converters and commercially available parts. The distribution of resolution versus sampling rate provides insight into ADC performance limitations. At sampling rates below 2 million samples per second (Gs/s), resolution appears to be limited by thermal noise. At sampling rates ranging from ~2 Ms/s to ~4 giga samples per second (Gs/s), resolution falls off by ~1 bit for every doubling of the sampling rate. This behavior may be attributed to uncertainty in the sampling instant due to aperture jitter. For ADCs operating at multi-Gs/s rates, the speed of the device technology is also a limiting factor due to comparator ambiguity. Many ADC architectures and integrated circuit technologies have been proposed and implemented to push back these limits. The trend toward single-chip ADCs brings lower power dissipation. However, technological progress as measured by the product of the ADC resolution (bits) times the sampling rate is slow. Average improvement is only ~1.5 bits for any given sampling frequency over the last six-eight years     

A 10-bit low power SAR A/D converter based on 90 nm CMOS

Traditional and some recently reported low power, high speed and high resolution approaches for SAR A/D converters are discussed. Based on SMIC 65 nm CMOS technology, two typical low power methods reported in previous works are validated by circuit design and simulation. Design challenges and considerations for high speed SAR A/D converters are presented. Moreover, an R-C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process. The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively. With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively, and the power dissipation is measured to be just 3.17 mW.     

一种全差分双通道采样保持的流水线操作AD变换器

介绍了一种基于双通道采样保持电路的流水线操作 AD变换器。设计结合了并行流水线转换电路的思想 ,从而能够有效提高转换速率 ,但是较之并行流水线结构 ,使用的运放较少 ,功耗低 ,而且可以避免并行结构可能存在的匹配问题。这个电路采用 0 .3 5 μm CMOS工艺实现 ,在 Cadence Spectre S环境下通过仿真验证 ,转换速率 40 MS/s时 ,能达到 1 0位精度     

The structure of the limit cycles in sigma delta modulation

It is shown that when the input to a sigma-delta modulator is a DC level that can be expressed as a rational number b/a, when normalized with respect to the quantizer step, the output bit string is periodic with a period that is multiple of the denominator a. On the basis of number theory, the structure of these cycles for single-loop modulators is determined and the noise contribution is computed. Around such levels the noise has two peaks, for which the maximum value and the width are proportional to the relative signal bandwidth and to the inverse of the period of the cycle, respectively. The effect of the limit cycles on the performance of the A/D and D/A converters using sigma-delta modulation is discussed. A comparison between single-loop and double-loop modulators from the point of view of this phenomena is made     

Low Power High-Speed Neuron MOS Digital-to-Analog Converters with Minimal Silicon Area

Digital-to-analog converts utilizing neuron MOS-transistors were designed. Different DACs were implemented and characterized in order to compare various topologies. Criteria to select structures were low power, fast performance and minimal silicon area. A basic 8-bit version is implemented with only one neuron MOS-transistor and eight capacitors. The silicon area of this D/A converter is only 0.04 mm² and the power consumption is 8.4 mW with conversion speed of 200 MS/s. An enhanced 8 and 10 bit versions utilizing neuron PMOS transistor and some extra circuitry are also proposed and tested. The silicon area of the enhanced 10 bit circuit is only 0.03mm² while the performance is as good as in the case of the basic version. The measured differential nonlinearity is 0.38 LSB and integral nonlinearity is 0.55 LSB for the enhanced 10 bit structure.     

Noise analysis for optical frequency conversion using nearlydegenerate four wave mixing in semiconductor optical amplifier

For future wavelength-division-multiplexed (WDM) networks, optical frequency conversion will enable the flexible and efficient use of optical frequency bandwidth. However, the signal degradation at frequency converters limits the maximum size of the network. Noise due to optical frequency conversion using nearly degenerate four wave mixing in a semiconductor optical amplifier is investigated, and it is found that the crosstalk from one of the two pump lasers can impose the power penalty on the bit error rate (BER) characteristics after optical frequency conversion. Analytical expressions for BER are developed and used to evaluate the receiver sensitivity penalty caused by optical frequency conversion. On the basis of these results the optimal setting of the frequency difference between the signal and pump lasers and the power ratio of the two pump lasers are discussed. A 155-Mb/s frequency-shift keying (FSK) transmission with 1750-GHz (14 nm) optical frequency conversion has been carried out, using a novel phase noise cancellation method. The BER performance is in good agreement with the calculated results     

A 2.5-V BiCMOS comparator with current-mode interpolation

A high-speed latched comparator based on a current-mode architecture is presented. It achieves a sampling speed of 150 MS/s at 2.5 V supply, with a power consumption lower than conventional schemes. Its very low kickback noise makes it especially suitable for differential analog-to-digital converters (ADCs). Moreover, it supports precise 2X interpolation in current mode at full clock speed, allowing a further reduction of the ADC power consumption. The comparator was implemented in a 0.8 μm BiCMOS technology     

Framework and Research Methodology of Short-Timescale Pulsed Power Phenomena in High-Voltage and High-Power Converters

Various short-timescale transients exist in power electronic converters, particularly in high-voltage and high-power systems. The timescales of these transients are from nanoseconds to microseconds, including a switching transition of power semiconductor devices, commutating processes, and drive signal transmissions. These transient processes directly affect the performance and reliability of power electronic systems. Therefore, it is necessary to study these short-timescale processes. Based on two high-power prototype power converters, a 6000-V/1250-kW three-level adjustable-speed drive and a 10-kW/600-V dc–dc converter, this paper studies the various abnormal behaviors of the converters that occurred during the operation of these converters. Dead bands and accumulated switching errors are also investigated. A combined microscopic pulsed power and macroscopic control strategy was proposed for the design of power electronic converters. Three new concepts for power electronic converters are introduced and validated in this paper: 1) sneak pulse; 2) energy dead band; and 3) transient commutating topology.