20.8 Gb/s GaAs LSI self-routing switch for ATM switching systems

An 8×8 self-routing hardware switch providing 20.8 Gb/s throughput has been developed for asynchronous transfer mode (ATM) switching systems. The basic architecture of this switch is a Batcher-Banyan network. A new mechanism for data processing and distributing high-speed signals is proposed. This switching system consists of three LSIs using a 0.5-μm gate GaAs MESFET technology. These LSIs are a switching network LSI for exchanging packet cells with eight cell channels, a negotiation network for screening of cells destined for the same output port, and a demultiplexer LSI for converting the cell streams from the switching network LSI to the eight streams per channel. These LSIs are mounted in a 520-pin multichip module package. The total number of logic gates is 13.3 k, and the power dissipation is 24 W. The switching system fully operates at a data rate of 2.6 Gb/s, and its throughput is 20.8 Gb/s     

A 1.8 Gb/s GaAs optoelectronic universal switch LSI withmonolithically integrated photodetector and laser driver

A high-speed monolithic optical interface switch LSI is developed using a GaAs MSM photodetector and large-scale integrated electric circuits. This LSI operates universally as a 1.8 Gb/s optical-input/optical-output four-channel time-division switch, a 1.8 Gb/s optical-input/electrical-output 1:4 demultiplexer, a 2.0 Gb/s electrical-output 4:1 multiplexer, and a 2.8 Gb/s electrical-input/electrical-output 4×4 space-division switch. It uses a new multistage 2×2 switch block with small hardware and high-speed operation. It can be expanded to a 16×16 optical-input/optical-output time-division switch operating at up to 1.8 Gb/s for broadband-ISDN     

A 2.5 Gb/s ATM add-drop unit for B-ISDN based on a GaAs LSI

This paper describes the design and implementation of a high-speed GaAs asynchronous transfer mode (ATM) mux-demux ASIC (AMDA) which is the core LSI circuit in a high-speed ATM add-drop unit (ADU). This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The ADU provides a cell-based interface between systems operating at different data rates (the high-speed interface being 2.5 Gb/s and the low-speed interface being 155/622 Mb/s), or can be used for building local high-speed switches and LANs. Self-timed first-in-first-out (FIFO) buffers are used for handling the speed gaps between domains operating at different clock rates, and a self-timed at receiver's input (STARI) interface is used at all high-speed chip-to-chip links to eliminate timing skews. A printed circuit board (PCB) with two ADUs in a distributed multiplexing-demultiplexing architecture has been developed, and the AMDA demonstrated operation above 4 Gb/s (500 MHz clock frequency) with an associated power dissipation of 5 W in a standard 0.8 μm E/D MESFET process     

A 1.5 Gb/s 8×8 cross-connect switch using a time reservationalgorithm

An input queuing type switching architecture that uses a high-performance contention resolution algorithm to achieve high-speed and large-capacity cross-connect switching is presented. The algorithm, called the time reservation algorithm, features time scheduling and pipeline processing. The performance of this switch is evaluated by computer simulation. The throughput of this switch is about 90%, without requiring high internal operation speeds. Three LSI designs are developed to verify the feasibility of the high-speed switch. They are the input buffer controller LSI, the contention-resolution module LSI, and the space-division switching LSI. The LSIs were constructed with an advanced Si-bipolar high-speed process. Also, 8×8 cross-connect switching boards are introduced. The measured maximum port speed is 1.55 Gb/s     

20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolartransistors for future optical transmission systems

Design principles for achieving good eye opening and circuit optimization to extract high performance from AlGaAs/GaAs heterojunction bipolar transistor (HBT) devices are described. Using the circuit techniques and HBTs with an f_T of 70 GHz and an f_max of 50 GHz, four kinds of SSIs are developed for future optical transmission systems. High-bit-rate operation of over 20 Gb/s (26 GHz toggle flip-flop, 20 Gb/s decision circuit, 20 Gb/s EXCLUSIVE OR/NOR gate, and 28 Gb/s selector IC), extremely fast rise and fall times (20-80%) of 20 and 14 ps, respectively, and good eye opening are obtained. In addition, potential performance gains that might be realized through advanced circuit and device design are appraised, and throughputs as fast as 40 Gb/s are predicted     

A 2.5 Gb/s ATM switch chip set

The design and implementation of two application specific integrated circuits used to build an ATM switch are described. The chip set is composed of the CMC which is an input/output processor of ATM cells implemented on a BICMOS 0.7 μm technology and the ICM, a 0.7 μm CMOS IC, that performs cell switching at 68 MHz. The ATM switch exploits parallelism and segmentation to perform 2.5 Gb/s switching per input/output. The main advantage of the high-speed link rates in the range of Gb/s, is the exploitation of statistical gain with bursty high peak rate sources. Another feature of the high speed ATM switches is that the number of interface devices and stages is reduced on an ATM network. To demonstrate the usefulness of the switch, an evaluation of the network efficiency improvement by using statistical gain is presented in the paper     

A 2 Gb/s expandable space-division switching LSI and networkarchitecture for gigabit-rate broad-band circuit switching

An expandable space-division (SD) switch architecture and a bipolar circuit design for gigabit-per-second crosspoint-switch LSIs are described. An expandable 2-Gb/s 16×16 crosspoint switch LSI which employs a novel switch structure, a novel circuit design, and a super self-aligned process (SST-1A) is developed. A switching module and partial 1:n nonblock, full 1:1 nonblock switching network architecture are also presented. Using the LSI and the switching network architecture, an experimental 620-Mb/s network system is demonstrated     

A 9.6-Gb/s HEMT ATM switch LSI with event-controlled FIFO

An asynchronous-transfer-mode (ATM) switch LSI was designed for the broadband integrated services digital network (B-ISDN) and fabricated using 0.6-μm high-electron-mobility-transistor (HEMT) technology. To enhance the high-speed performance of direct-coupled FET logic (DCFL), event-controlled logic was used instead of conventional static memory for the first-in first-out (FIFO) buffer circuit. The 4.8-mm×4.7-mm chip contains 7100 DCFL gates. The maximum operating frequency was 1.2 GHz at room temperature with a power dissipation of 3.7 W. The single-chip throughput was 9.6 Gb/s. An experimental 4-to-4 ATM switching module using 16 switch LSIs achieved a throughput of 38.4 Gb/s     

2.5Gb/sGaAs激光器高速驱动电路

研制出一种实用化的ＧａＡｓ激光器高速驱动电路,该电路采用源耦合场效应管逻辑电路形式,０．８μｍ栅工艺,全离子注入平面工艺,单电源（－５．２Ｖ）供电。并给出了研究结果：最大驱动电流可达４５ｍＡ,数据传输速率２．５Ｇｂ／ｓ。     

10Gb/s GaAs PHEMT光接收机前置放大器

简要分析了光接收机分布式前置放大器所具有的宽带优势,研制出了一种利用南京电子器件研究所0．5μm标准GaAs PHEMT工艺实现的10 Gb/s分布式前置放大器。该前置放大器采用损耗补偿技术,由七个共源共栅级联的单元组成,测试结果表明,该分布式前置放大器可以工作在10 Gb/s速率上。     

A 4 Gb/s 2-level to 2 Gsymbol/s 4-level converter GaAs IC forsemiconductor optical amplifier QPSK modulators

The design of a 50 Ω impedance matched two-to-four level converter GaAs IC for two-electrode semiconductor optical amplifier (SOA) modulators is presented. The designed IC exhibits eye diagrams with eye openings of better than 0.30 V and a spacing between adjacent output signal levels of 0.33 V for output symbol rates of up to 2 Gsymbol/s corresponding to input bit rates of up to 4 Gb/s. A novel differential super buffer output driver is applied, for which output reflection coefficients |S₂₂| of less than -12 dB for frequencies up to 10 GHz are obtained. A 1 Gb/s optical QPSK microwave link transmission experiment using a packaged sample of the designed IC and a two-electrode semiconductor optical amplifier phase modulator has been conducted     

24Gb/s 0.2μm GaAs PHEMT 2:1复接器

超高速复接器是光通信传输系统中的关键部件之一和速度瓶颈之一。本文利用0．2μm GaAs PHEMT(砷化镓伪高电子迁移率晶体管)工艺，设计出了超高速2：l复接器。应用一种简单而有效的宽带匹配方法，使得外部信号有效地传输到芯片内部。利用源极耦合电容的微分作用，加速晶体管的开、关转换，提高锁存器和D触发器的工作速率。窄传输线当作电感的应用，补偿了电容的影响，同时还减小了芯片面积。设计了一种测试方法，解决了复接器需要多路超高速信号源的问题。芯片通过功能测试验证，数据速率可达到24Gb／s。     

Low power GaAs current-mode 1.2 Gb/s interchip interconnections

A new GaAs current-mode (CM) chip-to-chip interconnection circuit is presented that provides high signal transfer speed with a 50 Ω active termination and reduced input voltage swing. The power dissipation is shown to be 1/8 of an ECL I/O at the same data rate, 4 mW per pin, using a standard 2 V power supply. The driver-receiver operates with a current swing under 1 mA and provides a large noise margin     

A self-learning digital neural network using wafer-scale LSI

A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 μm CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware     

Planar GaAs IC technology: Applications for digital LSI

This technology utilizes multiple localized ion implantations directly into semi-insulating GaAs substrates, with unimplanted areas providing isolation between circuit elements. This approach allows for high yield, high density circuits, with optimization of various types of devices (e.g., GaAs MESFETs, high-speed Schottky-barrier diodes, etc.) made possible by optimizing the implantation profile for each type of device. The application of this fabrication technology for high-speed, ultra low power digital integrated circuits using a new circuit approach called Schottky diode-FET logic (SDFL) is described. Experimental GaAS SDFL logic ICs with LSI/VLSI compatible power levels (200-500 /spl mu/W/gate) and circuit densities (<10/SUP -3/ mm/SUP 2//gate) have been fabricated.     

A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

A 155-MB/s 32×32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system     

Differential current mode serial link for 2 Gb/s in GaAs technology

Today's data communication systems are demanding increasing off-chip data rates. To satisfy this demand, high-speed serial links are used, saving area and power dissipation compared to highly parallel buses. However, power dissipation and noise generated by this system is still a critical issue. In this article, a novel approach using differential current mode is presented, which combines low power dissipation with low noise generated due to the reduced power transmission.     

TORUS-switch: a scalable internal speed-up ATM switch architectureand its 5 Gbit/s switch LSI

A high speed and scalable ATM switch architecture, the TORUS-switch, is proposed. The switch is an internal speed-up crosspoint switch with cylindrical configuration. The self-bit-synchronisation technique is adopted to achieve high speed cell transmission without requiring high-density implementation technology. Distributed contention control based on the fixed output-precedence scheme is adopted. This control is so simple that the control circuit is achieved with only one gate in each crosspoint. A TORUS-switch is fabricated as an ultrahigh speed crosspoint LSI using the advanced Si-bipolar process. Measured results confirm that the TORUS-switch can be used to realise an expandable terabit-rate ATM switch that is also efficient     

A 4 Gbits/s GaAs 16:1 multiplexer/1:16 demultiplexer LSI chip

A GaAs 16:1 multiplexer (MUX)/1:16 demultiplexer (DMUX) LSI chip, which operates at data rates from 50 Mb/s up to 4 Gb/s in a multilayer ceramic package, is described. The LSI chip incorporates trees of 2:1 MUX and 1:2 DMUX. The 2:1 MUX is composed of a master-slave D-flip-flop (DFF) joined with a 2-1 selector. The 1:2 DMUX consists of DFFs which are either a master-slave or the tristage type. The package has 76 pins and consists of five layers, including four power layers, and is applicable up to 7.7 GHz operation. The LSI chip is fabricated using a flat-gate self-aligned implantation for n⁺-layer technology (FG-SAINT process)