The universal opamp and applications in continuous-time resistorless and capacitorless linear weighted voltage addition

A versatile analog building block denoted the universal operational amplifier (opamp) is introduced. The circuit is a generalized version of the fully differential difference opamp with 2n weighted differential inputs. Applications in resistorless and capacitorless continuous-time linear weighted voltage addition are discussed. Experimental results of a test chip prototype are shown that validate the proposed approach. Simulations show potential for high frequency operation of the circuit with gain-bandwidth close to 140 MHz in 0.5-/spl mu/m CMOS technology.     

On-Chip Supply Noise Regulation Using a Low-Power Digital Switched Decoupling Capacitor Circuit

On-chip resonant supply noise in the mid-frequency range (i.e., 50–300 MHz) has been identified as the dominant supply noise component in modern microprocessors. To overcome the limited efficiency of conventional decoupling capacitors in reducing the resonant supply noise, this paper proposes a low-power digital switched decoupling capacitor circuit. By adaptively switching the connectivity of decaps according to the measured supply noise, the amount of charge provided by the decaps is dramatically boosted leading to an increased damping of the on-chip supply network. Analysis on the charge transfer during the switching events shows a 6-13X boost of effective decap value. Simulations verify the enhanced noise decoupling performance as well as the effective suppression of the first-droop noise. A 0.13 $ mu$m test chip including an on-chip resonance generation circuit and on-chip supply noise sensors was built to demonstrate the proposed switched decap circuit. Measurements confirm an 11X boost in effective decap value and a 9.8 dB suppression in supply noise using the proposed circuit. Compared with previous analog techniques, the proposed digital implementation achieves a 91% reduction in quiescent power consumption with improved tolerance to process-voltage-temperature (PVT) variation and tuning capability for obtaining the optimal switching threshold.      

MOSFET寄生电容对E类功率放大器影响的研究

针对Class-E功率放大器传输效率受MOSFET寄生电容的影响,提出了一种提高传输效率的方法。通过调节RLC回路中串联谐振电容的数值,提高旁路电容的数值,调节负载回路,使其超过MOSFET自身的输出寄生电容,以达到提高输出效率的目的。计算及仿真结果表明该方法在13.56 MHz下,可以将Class-E的旁路电容的值提高到120～160 pF,大大超过了IRF510的102.98 pF的寄生输出电容。最后,通过MSO3012混合信号示波器测量电路的传输效率,并对解决方案评估和改进,将Class-E的能量传输效率从改进前的37.1%提高到改进后的54.4%。据此,实现了Class-E在神经假体中数据与能量传输的应用。     

Resonant clocking using distributed parasitic capacitance

A resonant-clock generation and distribution scheme that uses the inherent, parasitic capacitance of the clocked logic as a lumped capacitor in a negative-resistance oscillator is described. Clock energy is resonated between inductors and the parasitic, local clock network to save power over traditional clocking methodologies. Theory predicts that the data passing though the clocked logic will change the clock frequency by less than 1.25%. A resonant clock test chip was designed and fabricated in an IBM 0.13-/spl mu/m partially depleted SOI process. Although the test chip was designed to operate in the gigahertz range using integrated inductors, startup difficulties required the addition of external inductance to reduce the resonant frequency so that the effects of the parasitic capacitance could be measured. The parasitic capacitance is approximately 40 pF per clock phase, resulting in a clock frequency between 106 and 146 MHz, depending on biasing. At its most efficient bias point, the clock dissipated 2.09 mW, which is approximately 35% less power than a conventional, buffer-driven clock. The maximum period jitter measured in the resonant clock due to changing data in the clocked latches was 55 ps at 124 MHz, or 0.68% of the clock period.     

基于CMOS工艺的太赫兹振荡器

在太赫兹频段,无源器件电容电感的品质因数低、电路的寄生参数以及MOS管的截止频率影响使太赫兹振荡器电路难以实现高功率输出。提出一种300 GHz可调谐振荡器,首先,采用改进的交叉耦合双推(Push-Push)振荡器结构,通过输出功率叠加的方法输出二次谐波300 GHz信号,增加了振荡器的输出功率并突破了MOS管截止频率,并通过增加栅极互连电感增加输出功率。其次,太赫兹振荡器摒弃传统片上可变电容调谐的方式,通过调节MOS管衬底电压改变MOS管的栅极寄生电容实现频率调谐,避免太赫兹频段引入低Q值电容,进一步增加了输出功率。提出的太赫兹振荡器采用台积电40 nm CMOS工艺,基波工作频率为154.5 GHz,输出二次谐波为 309.0 GHz,输出功率可达-3.0 dBm,相位噪声为-79.5 dBc/Hz@1 MHz,功耗为28.6 mW,频率调谐范围为303.5~315.4 GHz。     

一种片内集成飞电容的自适应开关电容DC-DC

提出一种电容片内集成、高效率升压模式的DC-DC电源管理芯片,较普通结构相比,文中提出的电路结构具有6组2×,3组3×,2组4×升压模型共11种工作模式,并具有低纹波等优点。通过MIM电容与积累型NMOS电容串联的方式,提高单位面积容值,使得总电容面积大幅减小。采用SMIC 0.18μm CMOS工艺,利用Cadence工具对电路进行仿真验证,所提出自适应开关电容升压电路,在输出电压为3 V时,其效率最高可达到83.6%。在开关频率为20 MHz时,输入电压范围为1~1.8 V,所需总片内集成电容总面积为900 μm×900 μm,输出电压纹波＜40 mV     

高密度低寄生电感硅基半导体电容器的设计及验证

采用在半导体材料表面深刻蚀三维图形以形成稳固蜂窝结构的方法,研究了一种适用于解决高频电路和系统级封装中串扰耦合问题的高密度、低寄生电感、制作及排布容易的硅基电容。结果显示,所制作的电容,其密度可增大至普通平面半导体电容的10倍以上,并较大程度地降低了电容的寄生电感,使其性能大大优于常用商业陶瓷电容,更适用于高频电路和系统级封装中的有效退耦。     

Analytical and Experimental Study on Suppression of Electromagnetic Interference on High Speed Printed Circuit Board for Wireless Communication Systems

In this paper, a novel routing topology is proposed to reduce crosstalk between parallel links used for high data rate application. Generally, microstrip lines are used in high frequency RF printed circuit boards for propagating high speed signals in wireless communication. Since RF front end modules in wireless system supports a wide ultra wide band frequency range from 700 MHz to 12 GHz, package density parasitic effects have been a major issue which degrades system performance. The close proximity of signal transmission lines with a high packing density results signal integrity problems such as crosstalk and timing jitter. A modified coupled microstrip line is proposed to reduce crosstalk by means of increasing capacitive coupling ratio. Our proposed structure reduced far end crosstalk by 4 dB and near end crosstalk by 4 dB than existing structures. The proposed microstrip line increased the maximum data rate from 1 to 3.3 Gb/s and reduced timing jitter by 51 ps at 3.3 Gb/s.     

Parasitic modeling and analysis for a 1-Gb/s CMOS laser driver

A differential laser driver (LD) operating at 1 Gb/s has been designed and tested using NSC 0.35-/spl mu/m CMOS technology. The effect of simultaneous switching noise caused by packaging parasitic was addressed and the parasitic model was developed to predict the exact behavior of circuit performance. With the developed parasitic model, the LD simulation results showed the degradation of the output signal. Thus, the effectiveness of the decoupling capacitor was suggested and investigated through the LD design. However, the test results did not match with the expected results due to the parasitic in the input and output nodes. Hence, the back-annotated analysis was performed with the developed parasitic models and the simulated output of the LD matched with that of the tested results.     

Novel parasitic insensitive SC large pole selectivity (Q) bandpass fitter with less capacitor spread and low pole ‘Q’ sensitivity

A new parasitic insensitive switched capacitor (SC) bandpass filter scheme is presented. The selectivity of the bandpass filter can be made very high without large capacitor spread, hence the proposed circuit consumes less chip area in monolithic integration and passive sensitivities of the circuit are found to be low.     

A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package

We demonstrate an integrated buck dc-dc converter for multi-V/sub CC/ microprocessors. At nominal conditions, the converter produces a 0.9-V output from a 1.2-V input. The circuit was implemented in a 90-nm CMOS technology. By operating at high switching frequency of 100 to 317 MHz with four-phase topology and fast hysteretic control, we reduced inductor and capacitor sizes by three orders of magnitude compared to previously published dc-dc converters. This eliminated the need for the inductor magnetic core and enabled integration of the output decoupling capacitor on-chip. The converter achieves 80%-87% efficiency and 10% peak-to-peak output noise for a 0.3-A output current and 2.5-nF decoupling capacitance. A forward body bias of 500 mV applied to PMOS transistors in the bridge improves efficiency by 0.5%-1%.     

Effective Radii of On-Chip Decoupling Capacitors

Decoupling capacitors are widely used to reduce power supply noise. On-chip decoupling capacitors have traditionally been allocated into the white space available on a die or placed inside the rows in standard cell circuit blocks. The efficacy of on-chip decoupling capacitors depends upon the impedance of the power/ground lines connecting the capacitors to the current loads and power supplies. A design methodology for placing on-chip decoupling capacitors is presented in this paper. A maximum effective radius is shown to exist for each on-chip decoupling capacitor. Beyond this effective distance, a decoupling capacitor is ineffective. Depending upon the parasitic impedance of the power distribution system, the maximum voltage drop seen at the current load is caused either by the first droop (determined by the rise time) or by the second droop (determined by the transition time). Two criteria to estimate the minimum required on-chip decoupling capacitance are developed based on the critical parasitic impedance. In order to provide the required charge drawn by the load, the decoupling capacitor has to be charged before the next switching cycle. For an on-chip decoupling capacitor to be effective, both effective radii criteria should be simultaneously satisfied.     

Efficient Distributed On-Chip Decoupling Capacitors for Nanoscale ICs

A distributed on-chip decoupling capacitor network is proposed in this paper. A system of distributed on-chip decoupling capacitors is shown to provide an efficient solution for providing the required on-chip decoupling capacitance under existing technology constraints. In a system of distributed on-chip decoupling capacitors, each capacitor is sized based on the parasitic impedance of the power distribution grid. Various tradeoffs in a system of distributed on-chip decoupling capacitors are also discussed. Related simulation results for typical values of on-chip parasitic resistance are also presented. The worst case error is 0.003% as compared to SPICE.      

一种跨导线性化低相噪压控振荡器

介绍了一种跨导线性化的宽带压控振荡器,由谐振腔电路、偏置电路、可编程电容阵列组成。提出一种通过电容隔直将有源器件进行交叉耦合的谐振腔结构,实现了有源器件的跨导线性化,大幅减小了有源器件自身的固有噪声,改善了压控振荡器的相位噪声特性。通过可编程电容阵列电路,可在压控振荡器内进行频率调节,扩展了振荡频率范围。测试结果表明,压控振荡器的振荡频率覆盖5 400~7 300 MHz,频率覆盖比达26%,在7 300 MHz时,相位噪声达到-128 dBc/Hz@1 MHz。该压控振荡器可作为高性能频率合成器的核心器件,构成本振信号源,可被广泛应用于无线基站、频谱监测等多种领域。     

深亚微米SoC芯片物理设计中基于串扰的时序收敛方法

当芯片设计进入深亚微米，串扰效应引起大量的设计违规，尤其是对时序收敛产生很大的影响。实际上串扰对电路时序性能的影响非常难估计，它不仅取决于电路互联拓扑，而且还取决于连线上信号的动态特征。文章从串扰延时的产生原因开始分析，并提出了在O．18μm及以下工艺条件下对串扰延时进行预防．分析和修复的时序收敛方法。     

利用半导体pn结结电容构成的沟道式电容器

为满足对电子系统中元器件性能提升、面积减小、成本降低等需求,利用感应耦合等离子体刻蚀技术(ICP),对低阻p型硅采用刻蚀、扩散、磁控溅射Al电极等工艺,使之形成凹槽状三维结构,制造出一种特殊的具有高密度电容量的硅基电容器。其特点是结构简单,电容量大(电容密度可达2.2×10–9F/mm2),容值可调,与现有微电子工艺兼容,可用于200MHz至数GHz的退耦或其他场合。同时由于半导体pn结固有的特性,该电容器可取代传统的贴片电容广泛用于电子系统中的退耦、滤波、匹配、静电和电涌防护等场合。     

系统芯片中AMBA总线串扰故障的自测试方法

系统芯片(SoC)技术的发展使得芯片内总线长度大大增加；芯片速度按照摩尔定律成倍提高(高达GHz)，总线间的串扰(Crosstalk)现象也日益严重，因此关于串扰的故障模型和自测试技术越来越受到关注。本文利用最大侵扰故障MAF(Maximal Aggressor Fault)模型，提出了一种SoC芯片中总线串扰故障的自测试方法。利用该方法，SoC芯片中地址、数据和控制总线的串扰故障均得到了测试，实验结果也表明其硬件开销较其它方案大大降低。     

全差分增益提高运算放大器的分析与设计

通过增益提高技术,一个全差分增益提高套筒式共源共栅运算放大器被提出和设计。该运算放大器得主运算放大器是由全差分套筒式共源共栅放大器构成,并带有一个开关电容共模反馈电路。而增益提高放大器是由全差分析叠式共源共栅放大器构成,它的共模反馈电路是连续时间反馈电路。该运算放大器采用中芯国际0．35μmixed-signal CMOS工艺设计,运算放大器的直流增益可达到129dB,而单位增益频率为161MHz。     

GaN HEMT非线性输出电容寄生参数研究

分析了GaN（氮化镓）HEMT（高电子迁移率晶体管）非线性输出电容寄生参数Cout与功率放大器效率的关系。通过建立非线性电路模型分析得出,Cout与外部合适的匹配电路结合能产生类似电压半正弦波,电流方波的最优效率波形。选用GaN HEMT 器件设计S频段射频功率放大器,实测结果显示该放大器最高漏极效率（DE）为81.7%,功率附加效率（PAE）78.56%,功率为41.16dBm,在100M带宽内PAE也可达74.49%以上,并且结构简单。实测结果验证了原理分析的可靠性。     

A low-power half-delay-line fast skew-compensation circuit

A fast skew-compensation circuit is useful for a chip to safely recover from the halt state because it can quickly compensate the clock skew induced by the on-chip clock driver. A low-power half-delay-line fast skew-compensation circuit (HDSC) is proposed in this work. The HDSC circuit features several new design techniques. The first is a new measure-and-compensate architecture, with which the HDSC circuit gains advantages including an enlarged operation frequency range, more robust operation, more accurate phase alignment, higher scalability for using advanced technologies, and lower power consumption, as compared to the conventional fast skew-compensation circuits. The second is a frequency-independent phase adjuster, with which the delay line can be shortened by half and the maximal power consumption is reduced accordingly if the clock signal has a 50% duty cycle. The third is a fine delay cell, which is used to accompany the half-delay-line, comprising of minimum-sized coarse delay cells, to effectively reduce the static phase error. Extensive circuit simulations are carried out to prove the superiority of the proposed circuit. In addition, an HDSC test chip is implemented for performance verification at high frequencies. The test chip is designed based on a 0.35-/spl mu/m CMOS process, and has a coarse cell delay of 220 ps. It works successfully between 600/spl sim/800 MHz, as designed, with a power consumption of 25/spl sim/36 /spl mu/W/MHz. When measured at 616.9 and 791.6 MHz, the static phase error is 76.8 and 124.5 ps, respectively.