A new on-chip interconnect crosstalk model and experimentalverification for CMOS VLSI circuit design

A new, simple closed-form crosstalk model is proposed. The model is based on a lumped configuration but effectively includes the distributed properties of interconnect capacitance and resistance. CMOS device nonlinearity is simply approximated as a linear device. That is, the CMOS gate is modeled as a resistance at the driving port and a capacitance at a driven port. Interconnects are modeled as effective resistances and capacitances to match the distributed transmission behavior. The new model shows excellent agreement with SPICE simulations. Further, while existing models do not support the multiple line crosstalk behaviors, our model can be generalized to multiple lines. That is, unlike previously published work, even if the geometrical structures are not identical, it can accurately predict crosstalk. The model is experimentally verified with 0.35-μm CMOS process-based interconnect test structures. The new model can be readily implemented in CAD analysis tools. This model can be used to predict the signal integrity for high-speed and high-density VLSI circuit design     

An accurate model for dynamic crosstalk analysis of CMOS gate driven on-chip interconnects using FDTD method

An accurate and time efficient model of CMOS gate driven coupled-multiple interconnects is presented in this paper for crosstalk induced propagation delay and peak voltage measurements. The proposed model is developed using the finite difference time domain (FDTD) technique for coupled RLC interconnects, whereas the alpha power law model is used to represent the transistors in a CMOS driver. As verified by the HSPICE simulation results, the transient response of the proposed model demonstrates high accuracy. Over the random number of test cases, crosstalk induced peak voltage and propagation delay show average errors of 1.1% and 4.3%, respectively, with respect to HSPICE results.     

Interconnect crosstalk noise evaluation in deep-submicron technologies

To solve the crosstalk noise problem in deep-submicron technologies, a statistical method for analyzing crosstalk noise with reduced distributed RC-π model is proposed in this paper. First, quiet aggressor net and tree branch reduction techniques are introduced into the distributed RC-π model, and a new spatial correlation model for both Gaussian and non-Gaussian process variations among segments is created. Then, principal components analysis (PCA) and independent component analysis (ICA) techniques are applied to reduce correlations of process variations. Finally, the moment matching scheme is used to obtain the probability density function (PDF) of crosstalk noise in victim coupled with multiple aggressors. Experimental results show that our method maintains the efficiency of previous approaches, and significantly improves on their accuracy.     

Identifying defects in deep-submicron CMOS ICs

With safety margins for reliability, test, failure analysis, and design verification shrinking, it would be a shame to give up the I_DDQ technique-and luckily, we may not have to. Steps can be taken to maintain its applicability as we rush deeper into the submicron regime. We will first examine why the I_DDQ test serves several interests, then describe the challenge posed by 0.35-0.07 μm transistor geometries, and finally propose several solutions     

标准CMOS工艺在高速模拟电路和数模混合电路中的应用展望

从速度、集成度、功耗和成本等几个方面深入的分析了利用标准CMOS工艺来设计开发高速模拟器件和混合处理芯片的现状及发展潜力。     

CMOS混合信号集成电路中的串扰效应

论述了混合信号集成电路中的串扰效应及其对电路本身的影响,重点讨论了在重掺杂衬底中数字干扰对模拟器件的影响,并给出了数字噪声注入等效电路.同时从制造工艺和设计技术方面讨论了降低串扰效应的方法.     

Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process

A new charge pump circuit has been proposed to suppress the return-back leakage current without suffering the gate-oxide reliability problem in low-voltage CMOS process. The four-phase clocks were used to control the charge-transfer devices turning on and turning off alternately to suppress the return-back leakage current. A test chip has been implemented in a 65-nm CMOS process to verify the proposed charge pump circuit with four pumping stages. The measured output voltage is around 8.8 V with 1.8-V supply voltage to drive a capacitive output load, which is better than the conventional charge pump circuit with the same pumping stages. By reducing the return-back leakage current and without suffering gate-oxide overstress problem, the new proposed charge pump circuit is suitable for applications in low-voltage CMOS IC products.     

An accurate CMOS sample-and-hold circuit

An accurate sample-and-hold (S/H) circuit implemented with a 2-μm double-poly CMOS process is described. Competitive performance in terms of output swing, linearity, and clock feedthrough compensation was obtained using a new circuit topology. The sample and hold operates up to 1 MHz of sampling frequency with less than -60 dB of total harmonic distortion. The accuracy of the held step is better than 0.2 mV. The circuit dissipates 4 mW with a 5-V power supply     

An integrated mass flow sensor with on-chip CMOS interfacecircuitry

A multielement monolithic mass flow sensor which developed for possible use in automotive and industrial process control applications is reported. The chip illustrates the use of a common microstructure (a thin dielectric window/diaphragm) for the simultaneous measurement of flow velocity (rate), flow direction, gas type, and pressure. These transducers are merged with on-chip interface electronics to amplify and multiplex the transducer signals, control on-chip actuators, perform self-test, reduce the number of external leads required, and demonstrate process compatibility with a p-well CMOS process. The on-chip circuitry also implements a bandgap sensor for the measurement of ambient temperature. Thus, the chip simultaneously monitors all parameters needed for the computation of true mass flow, requires only ten external leads, and delivers high-level buffered output signals     

A new on-chip ESD protection circuit with dual parasitic SCRstructures for CMOS VLSI

A new CMOS on-chip electrostatic discharge (ESD) protection circuit which consists of dual parasitic SCR structures is proposed and investigated. Experimental results show that with a small layout area of 8800 μ², the protection circuit can successfully perform negative and positive ESD protection with failure thresholds greater than ±1 and ±10 kV in machine-mode (MM) and human-body-mode (HBM) testing, respectively. The low ESD trigger voltages in both SCRs can be readily achieved through proper circuit design and without involving device or junction breakdown. The input capacitance of the proposed protection circuit is very low and no diffusion resistor between I/O pad and internal circuits is required, so it is suitable for high-speed applications. Moreover, this ESD protection circuit is fully process compatible with CMOS technologies     

Readout circuit for CMOS active pixel image sensor

The design and simulation results of a new readout circuit for a CMOS active pixel image sensor are presented. This scheme removes the fixed pattern noise and reduces the signal degradation while offering an increase in readout speed, compared with the conventional approach     

An elliptic continuous-time CMOS filter with on-chip automatic tuning

A voice-band continuous-time filter is described which was designed based on the technique of fully balanced networks and was fabrication in a 3.5-/spl mu/ CMOS technology. The filter implements a fifth-order elliptic low-pass transfer function with 0.05-dB passband ripple and 3.4 kHz cutoff frequency. A phase-locked loop control system fabricated on the same chip automatically references the frequency response of the filter to an external fixed clock frequency. The cutoff frequency was found to vary by less than 0.1% for an operating temperature range of 0-85/spl deg/C. The absolute value accuracy of the cutoff frequency was 0.5% (standard deviation). With /spl plusmn/5-V power supplies the measured dynamic range of the filter was approximately 100 dB.     

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Latchup failure induced by electrostatic discharge (ESD) protection circuits occurred anomalously in a high-voltage IC product. Latchup issues existed at only three output pins, two of which belonged to the top and the other to the side. The layouts of top and bottom output pins are identical, and side output pins have another identical layouts. In our experiments it was found latchup of two top output pins were originated from the latchup of the side output pin, and therefore heat-induced latchup aggravation issue must be noticed during latchup test. Furthermore, large power line current (Idd) existed during triggering this side output pin and led to subsequent latchup. After thorough layout inspection, the layout of this side output pin is identical to all other side output pins except that it has an additional N-well (NW) resistor of gate-triggered high-voltage PMOS beside. It was later proved by engineering experiments that this NW resistor is the origin of inducing latchup in this product, and a new mechanism was proposed for this latchup failure. Improvements and solutions were also provided to successfully solve the latchup issues of these three output pins.     

An evaluation of deep-submicron CMOS design optimized for operation at 77 K

Using a careful and insightful analysis of the possible benefits of 77 K CMOS in submicron technology from a decade ago [1], the development of 77 K CMOS in present-day deep submicron technology is evaluated. It is found that the basic principles from the earlier study—that the real benefit of 77 K CMOS operation is the ability to provide “pure” scaling of the threshold voltage and thus to allow aggressive super-scaling of MOS transistor dimensions—not only holds in present-day CMOS processes, but is even more important in that regard. A detailed analysis of CMOS technology, digital circuit behavior, and analog circuit behavior is provided. It is noted that not only does properly-designed 77 K CMOS technology provide opportunities; it also addresses some of the most fundamental difficulties facing CMOS technology and CMOS circuit design.     

Integration and electrical isolation in CMOS mixed-signal wirelesschips

The technological trends underlying the application of CMOS technology in wireless applications are leading to the integration of the RF analog functions and the digital baseband processing into a single chip. Two key technical requirements for this integration are the capability to fabricate high Q passive components and the need to maintain electrical isolation between analog and digital components in the resulting mixed-signal chip. Some basic arguments that illustrate the technological conflict between these two important demands are presented, focusing on their implications for the structure of the IC substrate. This structure and the characteristics of the device package play important robs in determining the levels of coupled ground noise that will be present in the mixed-signal IC. A simple, high-level model for coupled ground noise is presented and used to illustrate the impact of design alternatives for the package and for the IC substrate     

A CMOS mixed-signal clock and data recovery circuit for OIF CEI-6G+ backplane transceiver

A CMOS low-power mixed-signal clock and data recovery circuit is presented in this paper. It is designed for OIF CEI-6G+ LR backplane transceiver, and consists of a phase detector, loop filter, phase control logic, and phase interpolator. A unique subsampled architecture makes it possible for a low-power mixed-signal clock recovery loop running at a rate of 6 Gb/s. The proposed architecture has data pattern independent loop bandwidth. Fabricated in a 0.13-/spl mu/m CMOS technology in an area of 280/spl times/100 /spl mu/m/sup 2/, the clock and data recovery loop exhibits a frequency tracking range up to 2000 ppm. The bit error rate is less than 10/sup -12/ with a pseudorandom bit sequence of length 2/sup 31/-1. The power dissipation is 24 mW for clock and data recovery circuits from a single 1.2-V supply.     

An ultra-low-voltage ultra-low-power CMOS active mixer

The scaling of CMOS technology has greatly influenced the design of analog and radio-frequency circuits. In particular, as technology advances, due to the use of lower supply voltage the available voltage headroom is decreased. In this paper, after a brief overview of conventional low-power CMOS active mixer structures, we introduce an active mixer structure with sub-mW-level power consumption that is capable of operating from a supply voltage comparable or lower than the threshold voltage of the transistor. In addition, the proposed architecture provides a performance and conversion gain (CG) that compares favorably or exceeds those of the state-of-the-art designs. As a proof-of-concept, a wide-band DC to 8.5 GHz down-conversion mixer is designed and fabricated in a 90-nm CMOS process. Measurement results show that the mixer achieves a CG as high as 18 dB while consuming 98 μW from a 0.3-V supply.     

An on-chip ECC circuit for correcting soft errors in DRAMs withtrench capacitors

A modified error-correcting code that can correct up to two soft errors on each row (word line) in a dynamic random-access memory (DRAM) chip is proposed. Double-bit soft errors frequently occur in DRAM cells with trench capacitors, when charged alpha particles impinge on the intervening space between two vertical capacitors causing plasma shorts between them. The conventional on-chip error-correcting codes (ECCs) cannot correct such double-bit word-line soft errors, which significantly increase the uncorrectable error rate (UER). An ECC circuit that uses an augmented rectangular product code to detect and correct double-bit soft errors is presented. The proposed circuit automatically corrects the addressed bit if it is faulty, and then quickly locates the other faulty bit. A comprehensive study is made to estimate improvements in soft error rate (SER) and mean time to failure (MTTF). The ability of the circuit to correct soft errors in the presence of multiple-bit errors has also been analyzed by combinatorial enumeration     

Oxygen implantation to suppress parasitic bipolar action in CMOS

Oxygen implantation and subsequent epitaxial silicon deposition have been developed to improve CMOS latchup prevention through reducing the current gains of parasitic bipolar transistors. The buried oxygen implanted layer is well confined, and defects do not extend into the epitaxial silicon layer. The device characteristics of the n- and p-MOSFETs fabricated on a wafer with the oxygen implantation are therefore not affected by the buried implanted layer. The oxygen implanted layer can reduce the minority-carrier lifetime and hence decrease the current gain of the lateral parasitic bipolar transistor. In addition, it introduces a potential barrier which decreases the current collected at the frontside contact of the vertical parasitic bipolar transistor. The common base current gain is reduced by 50% and 80% for the lateral and the vertical parasitic bipolar transistors, respectively. As a consequence, the CMOS latchup immunity is significantly improved